WO2008102448A1 - 半導体装置と半導体装置の製造方法 - Google Patents

半導体装置と半導体装置の製造方法 Download PDF

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Publication number
WO2008102448A1
WO2008102448A1 PCT/JP2007/053299 JP2007053299W WO2008102448A1 WO 2008102448 A1 WO2008102448 A1 WO 2008102448A1 JP 2007053299 W JP2007053299 W JP 2007053299W WO 2008102448 A1 WO2008102448 A1 WO 2008102448A1
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WO
WIPO (PCT)
Prior art keywords
gate electrode
semiconductor device
side wall
insulating film
conduction type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/053299
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English (en)
French (fr)
Inventor
Yosuke Shimamune
Naoyoshi Tamura
Akira Katakami
Akiyoshi Hatada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
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Fujitsu Ltd
Fujitsu Semiconductor Ltd
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Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/053299 priority Critical patent/WO2008102448A1/ja
Publication of WO2008102448A1 publication Critical patent/WO2008102448A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<> </> 　製造工程を簡略化できる、応力印加機構を有するＭＯＳトランジスタ半導体装置とその製造方法を提供する。 　半導体装置は、シリコン基板の第１導電型の活性領域上に形成されたゲート絶縁膜と、その上に形成されたゲート電極を含む絶縁ゲート電極構造と、絶縁ゲート電極構造の両側の活性領域に形成された、第２導電型のソース／ドレイン領域と、絶縁ゲート電極構造の側壁上に形成され、エッチング特性の異なる第１、第２の絶縁層を含むサイドウォールスペーサと、サイドウォールスペーサの下部において、外側側壁面からゲート電極に向かって形成され、ソース／ドレイン領域のシリコン表面を露出し、ゲート電極との間にサイドウォールスペーサの一部を残す横方向スリットと、横方向スリット内でのみ、シリコン表面上にエピタキシャルに成長され、横方向スリットを埋め、シリコンと異なる格子定数を有する第2導電型の応力印加結晶層と、を有する。
PCT/JP2007/053299 2007-02-22 2007-02-22 半導体装置と半導体装置の製造方法 Ceased WO2008102448A1 (ja)

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Application Number Priority Date Filing Date Title
PCT/JP2007/053299 WO2008102448A1 (ja) 2007-02-22 2007-02-22 半導体装置と半導体装置の製造方法

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PCT/JP2007/053299 WO2008102448A1 (ja) 2007-02-22 2007-02-22 半導体装置と半導体装置の製造方法

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009026855A (ja) * 2007-07-18 2009-02-05 Panasonic Corp 半導体装置及びその製造方法
CN103594372A (zh) * 2012-08-17 2014-02-19 中国科学院微电子研究所 半导体器件制造方法
CN103730417A (zh) * 2012-10-10 2014-04-16 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN108807175A (zh) * 2017-04-26 2018-11-13 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN111725294A (zh) * 2019-03-22 2020-09-29 三星电子株式会社 半导体器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005027192A2 (en) * 2003-09-10 2005-03-24 International Business Machines Corporation Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions
JP2006332337A (ja) * 2005-05-26 2006-12-07 Toshiba Corp 半導体装置及びその製造方法
JP2007036205A (ja) * 2005-06-22 2007-02-08 Fujitsu Ltd 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005027192A2 (en) * 2003-09-10 2005-03-24 International Business Machines Corporation Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions
JP2006332337A (ja) * 2005-05-26 2006-12-07 Toshiba Corp 半導体装置及びその製造方法
JP2007036205A (ja) * 2005-06-22 2007-02-08 Fujitsu Ltd 半導体装置およびその製造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009026855A (ja) * 2007-07-18 2009-02-05 Panasonic Corp 半導体装置及びその製造方法
US8178929B2 (en) 2007-07-18 2012-05-15 Panasonic Corporation Semiconductor device and method for fabricating the same
CN103594372A (zh) * 2012-08-17 2014-02-19 中国科学院微电子研究所 半导体器件制造方法
CN103730417A (zh) * 2012-10-10 2014-04-16 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN108807175A (zh) * 2017-04-26 2018-11-13 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN111725294A (zh) * 2019-03-22 2020-09-29 三星电子株式会社 半导体器件及其制造方法
TWI818097B (zh) * 2019-03-22 2023-10-11 南韓商三星電子股份有限公司 包含場效電晶體的半導體裝置及其製作方法
CN111725294B (zh) * 2019-03-22 2024-05-28 三星电子株式会社 半导体器件及其制造方法

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