WO2008102443A1 - 半導体装置とその製造方法 - Google Patents

半導体装置とその製造方法 Download PDF

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Publication number
WO2008102443A1
WO2008102443A1 PCT/JP2007/053210 JP2007053210W WO2008102443A1 WO 2008102443 A1 WO2008102443 A1 WO 2008102443A1 JP 2007053210 W JP2007053210 W JP 2007053210W WO 2008102443 A1 WO2008102443 A1 WO 2008102443A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
semiconductor device
capacitor
interlayer insulating
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/053210
Other languages
English (en)
French (fr)
Inventor
Kouichi Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to JP2009500039A priority Critical patent/JP5168273B2/ja
Priority to PCT/JP2007/053210 priority patent/WO2008102443A1/ja
Priority to KR1020097017283A priority patent/KR101100142B1/ko
Priority to CN2007800516013A priority patent/CN101641781B/zh
Publication of WO2008102443A1 publication Critical patent/WO2008102443A1/ja
Priority to US12/542,243 priority patent/US8004030B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

【課題】強誘電体キャパシタの劣化を防止することが可能な半導体装置とその製造方法を提供すること。 【解決手段】 シリコン基板１０の上方に形成された下地絶縁膜２５と、下地絶縁膜２５の上に形成された強誘電体キャパシタQと、キャパシタQの上に交互に複数形成された層間絶縁膜３５、４８、６２及び金属配線４５、５８、７２と、層間絶縁膜４８が備えるホール５４ａ内に形成され、金属配線４５と電気的に接続された導電性プラグ５７とを有し、層間絶縁膜４８の上面に、第１絶縁性酸化金属膜５０ａ、層間絶縁膜４８よりも比誘電率が低い中間絶縁膜５０ｂ、及び第２絶縁性金属酸化金属膜５０ｃを順に積層してなる第１キャパシタ保護絶縁膜５０が形成され、該第１キャパシタ保護絶縁膜５０にもホール５４ａが形成された半導体装置による。
PCT/JP2007/053210 2007-02-21 2007-02-21 半導体装置とその製造方法 Ceased WO2008102443A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2009500039A JP5168273B2 (ja) 2007-02-21 2007-02-21 半導体装置とその製造方法
PCT/JP2007/053210 WO2008102443A1 (ja) 2007-02-21 2007-02-21 半導体装置とその製造方法
KR1020097017283A KR101100142B1 (ko) 2007-02-21 2007-02-21 반도체 장치와 그 제조 방법
CN2007800516013A CN101641781B (zh) 2007-02-21 2007-02-21 半导体装置及其制造方法
US12/542,243 US8004030B2 (en) 2007-02-21 2009-08-17 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053210 WO2008102443A1 (ja) 2007-02-21 2007-02-21 半導体装置とその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/542,243 Continuation US8004030B2 (en) 2007-02-21 2009-08-17 Semiconductor device and method for manufacturing the same

Publications (1)

Publication Number Publication Date
WO2008102443A1 true WO2008102443A1 (ja) 2008-08-28

Family

ID=39709729

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053210 Ceased WO2008102443A1 (ja) 2007-02-21 2007-02-21 半導体装置とその製造方法

Country Status (5)

Country Link
US (1) US8004030B2 (ja)
JP (1) JP5168273B2 (ja)
KR (1) KR101100142B1 (ja)
CN (1) CN101641781B (ja)
WO (1) WO2008102443A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011049537A (ja) * 2009-08-25 2011-03-10 Korea Electronics Telecommun 不揮発性メモリセル及びその製造方法
JP2019009339A (ja) * 2017-06-27 2019-01-17 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100959445B1 (ko) * 2007-12-17 2010-05-25 주식회사 동부하이텍 반도체 소자의 캐패시터 및 그 제조방법
JP2011061085A (ja) * 2009-09-11 2011-03-24 Toshiba Corp 強誘電体記憶装置
KR101989514B1 (ko) * 2012-07-11 2019-06-14 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20190157213A1 (en) * 2017-11-20 2019-05-23 Globalfoundries Inc. Semiconductor structure with substantially straight contact profile
CN116093068A (zh) * 2021-11-08 2023-05-09 联华电子股份有限公司 单次可编程存储器电容结构及其制作方法
US20230320227A1 (en) * 2022-03-29 2023-10-05 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure and semiconductor structure thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574921A (ja) * 1991-09-13 1993-03-26 Hitachi Ltd ケース
JP2001244426A (ja) * 1999-12-22 2001-09-07 Texas Instr Inc <Ti> 強誘電メモリ・セルの製造方法
JP2006049795A (ja) * 2004-06-28 2006-02-16 Fujitsu Ltd 半導体装置及びその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4408994B2 (ja) * 1999-07-13 2010-02-03 Ａｚエレクトロニックマテリアルズ株式会社 低誘電率多孔質シリカ質膜、半導体装置およびコーティング組成物
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
US6617690B1 (en) * 2002-08-14 2003-09-09 Ibm Corporation Interconnect structures containing stress adjustment cap layer
JP2007165350A (ja) * 2005-12-09 2007-06-28 Fujitsu Ltd 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574921A (ja) * 1991-09-13 1993-03-26 Hitachi Ltd ケース
JP2001244426A (ja) * 1999-12-22 2001-09-07 Texas Instr Inc <Ti> 強誘電メモリ・セルの製造方法
JP2006049795A (ja) * 2004-06-28 2006-02-16 Fujitsu Ltd 半導体装置及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011049537A (ja) * 2009-08-25 2011-03-10 Korea Electronics Telecommun 不揮発性メモリセル及びその製造方法
US8558295B2 (en) 2009-08-25 2013-10-15 Electronics And Telecommunications Research Institute Nonvolatile memory cell and method of manufacturing the same
US8716035B2 (en) 2009-08-25 2014-05-06 Electronics And Telecommunications Research Institute Nonvolatile memory cell and method of manufacturing the same
JP2019009339A (ja) * 2017-06-27 2019-01-17 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
US20090302363A1 (en) 2009-12-10
JPWO2008102443A1 (ja) 2010-05-27
CN101641781B (zh) 2012-04-04
KR20100004975A (ko) 2010-01-13
CN101641781A (zh) 2010-02-03
KR101100142B1 (ko) 2011-12-29
JP5168273B2 (ja) 2013-03-21
US8004030B2 (en) 2011-08-23

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