WO2008087516A1 - Procédé de fabrication d'un substrat hybride - Google Patents

Procédé de fabrication d'un substrat hybride Download PDF

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Publication number
WO2008087516A1
WO2008087516A1 PCT/IB2008/000050 IB2008000050W WO2008087516A1 WO 2008087516 A1 WO2008087516 A1 WO 2008087516A1 IB 2008000050 W IB2008000050 W IB 2008000050W WO 2008087516 A1 WO2008087516 A1 WO 2008087516A1
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substrate
layer
insulator
insulator layer
oxide
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PCT/IB2008/000050
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English (en)
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Xavier Hebras
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S.O.I.Tec Silicon On Insulator Technologies
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Publication of WO2008087516A1 publication Critical patent/WO2008087516A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the present invention relates to a process for fabricating a hybrid substrate that can be used m the field of optics, electronics or optoelectronics.
  • opticals in general include microelectronics, nano-electronics , micro-optoelectronics , nano-optoelectronics and components technology.
  • a hybrid substrate is a substrate comprising at least two layers of material of the same or different nature, the term "nature” covering both the chemical nature of the material and its physicochemical properties and/or its crystalline orientation.
  • Hybrid substrates are in particular those known by the acronym “SeOI”, which stands for “Semiconductor On Insulator” .
  • Such a substrate comprises an insulator layer, for example made of oxide, buried between a generally thin layer of semiconductor material, the "active" layer, and a bulk substrate or “receiver” substrate made of semiconductor material.
  • insulator denotes an electrically insulating material, possibly having a high dielectric permittivity .
  • SeOI substrates are fabricated, for example, by a process known by the trademark "SmartCutTM” , which comprises the following steps: formation or deposition of an insulator layer on a first substrate, called a “donor” substrate, so that an interface called a “bonding” interface exists between them; implantation of atomic species into said donor substrate so as to form a zone of weakness therein; bonding a second substrate, called a “receiver substrate” , onto the free surface of the insulator by molecular adhesion, ; and detachment of the rear part of said donor substrate along the zone of weakness .
  • SmartCutTM a process known by the trademark "SmartCutTM” , which comprises the following steps: formation or deposition of an insulator layer on a first substrate, called a “donor” substrate, so that an interface called a “bonding” interface exists between them; implantation of atomic species into said donor substrate so as to form a zone of weakness therein; bonding a second substrate, called
  • the surface quality of the active layer of semiconductor material is of very great importance. More precisely, the roughness and the absence of surface defects on this active layer are parameters that have to be optimized so that the future components that will be produced from these SeOI substrates will be of optimum quality.
  • NTZs non- transferred zones
  • blisters voids
  • COVs crystal -oriented voids
  • the defects present at the bonding interfaces will become sites for gas trapping during the various steps of the process and will thus swell and form voids or COVs.
  • the gaseous elements may have several origins.
  • LPCVD TEOS will denote a silicon oxide (SiO 2 ) obtained from a tetraethyl- orthosilicate (TEOS) precursor by a low-pressure chemical vapor deposition (LPCVD) technique.
  • the aforementioned gaseous elements may derive in particular : from the hydrogen and/or helium supplied during the atomic species implantation step for the purpose of forming the zone of weakness, the quantity of these gaseous elements depending on the type of implanter used and on the implantation conditions (dose and energy) ; from the desorption of water (H 2 O) molecules present at the bonding interface between the thermal oxide and the TEOS oxide; and from the TEOS oxide if the densification of the latter has not been sufficient, because of the diffusion of carbon compounds.
  • the thinner the thickness of the active layer the larger the number of defects. This is because when the active layer is thick enough, defects of the blister or void type are generally retained within its thickness and consequently appear less on its surface.
  • this hybrid substrate is the result of bonding between a silicon (Si) support substrate that has undergone a thermal oxidation and a germanium (Ge) donor substrate on which a layer of silicon oxide (SiO 2 ) has been deposited.
  • the bonding interface is therefore between two oxides, one belonging to the support substrate and the other belonging to the donor substrate.
  • the bonding interface between the two SiO 2 layers is located at -200 nm .
  • the support substrate has not been shown in figure 4 - only its linking interface with the SiO 2 layer is shown, and this interface is located at -400 nm .
  • Curve a shown as a solid line represents the results obtained m the germanium donor substrate covered with SiO 2 before the two substrates are bonded together and before the implantation of atomic species using the SmartCutTM process for the purpose of forming the zone of weakness within the germanium layer.
  • the H ⁇ ions lie mainly at the bonding interface between the SiO 2 first layer and the germanium layer.
  • Curve c shown as a bold line represents the results obtained in the same substrate after the implantation for forming the zone of weakness and before the bonding to the SiO 2 second layer. It should be noted that the vertical line at -200 nm corresponds to an artefact. The values start only at about -200 nm as this corresponds to the implantation carried out before the bonding of the SiO 2 second layer. In the particular case of germanium, detachment does not take place in the region of maximum implantation, but just a little after (about 550 nm) , which will explain the appearance of curve b below,
  • Curve b shown as a dotted line represents the results obtained after the bonding of the two SiO 2 layers and after detachment and transfer of the germanium active layer.
  • the distribution of the hydrogen species shows a build-up at the SiO 2 /Ge and Si0 2 /support substrate bonding interface. A small peak appears at -200 nm in the SiO 2 layer. This corresponds to the bonding interface between the two SiO 2 layers.
  • hybrid substrates are also those known by those skilled in the art as DSB ⁇ "Direct Silicon Bonding" substrates.
  • Such substrates comprise an active layer of semiconductor material directly bonded to a receiver substrate or bulk substrate, also made of semiconductor material, without the formation of an intermediate layer, especially without the formation of a buried oxide layer.
  • this process is to fabricate a hybrid substrate that comprises a germanium layer on silicon, while reducing the formation of bubbles at the bonding interface. More precisely, this substrate is obtained by implantation of hydrogen into a germanium donor substrate so as to form a zone of weakness therein, then by bonding it to a silicon receiver substrate, and finally by heat treatment to detach the rear part of the germanium substrate .
  • the author suggests placing what is called an "antibubble" layer of amorphous silicon on the germanium substrate before bonding, so as to make the bonding interface hydrophilic and thus to reduce the formation of hydrogen bubbles when the germanium substrate is bonded to the silicon substrate.
  • the object of the invention is to provide a process for fabricating a hybrid substrate that prevents the formation of defects on the surface of the semiconductor active layer transferred, and more precisely defects due to the build-up of gaseous elements at the various bonding interfaces of said substrate .
  • such a process must also be applicable to the fabrication of a hybrid substrate whose active layer has a small thickness, i.e. less than 400 nm, and whose insulator layer is less than 5 nm, or even nonexistent.
  • the object of the invention is also to dispense with the deposition of intermediate layers (amorphous layers or buffer layers) that are deposited or inserted between the insulator layer and the active layer, as is the case according to the processes known in the prior art.
  • intermediate layers amorphous layers or buffer layers
  • the reason for this is that such layers are liable to modify the electrical properties of the final structure .
  • the invention relates to a process for fabricating a hybrid substrate that can be used in the fields of optics, electronics or optoelectronics, wherein it comprises the following steps consisting in: a) forming or depositing a first insulator layer (2) on a first substrate chosen from two substrates referred to as "donor" substrate and “receiver” substrate respectively, which are made of semiconductor material; b) carrying out a treatment for increasing the roughness of the free surface of said first insulator layer; c) depositing a second insulator layer on the roughened first insulator layer so as to form, between them, a zone called a "trapping" zone; d) bonding the substrate that has not been used in step a) onto said second insulator layer by molecular adhesion (wafer bonding) ; and e) transferring a layer called an "active" layer by detaching it from said donor substrate along a zone of weakness formed within this substrate by the implantation of atomic species, said trapping
  • step b) is carried out so that the minimum RMS roughness of the free surface of said first insulator layer is at least 10 nm over a scan area measuring 40 ⁇ m x 40 ⁇ m and wherein the first insulator layer is formed or deposited so as to have a thickness at least equal to 10 times the value of this minimum roughness;
  • the roughening of the first insulator layer is carried out by chemical etching, for example using a standard cleaning solution 1 comprising a mixture of ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and deionized water or using a solution of hydrofluoric acid (HF) ;
  • the first insulator layer is roughened by subjecting it to a treatment m a gas plasma containing at least one of the following gases selected from C x F,, S x F , C x H 7 , carbon monoxide (CO) , hydrogen, argon, chlor
  • the insulator constituting the first and second insulator layers is an oxide of the semiconductor material constituting the active layer
  • said active layer has a predetermined thickness
  • the hybrid substrate is heated in an inert and/or reducing atmosphere at a predetermined temperature for a predetermined time, said predetermined thickness, predetermined temperature and predetermined time being chosen so as to make a quantity of oxygen of the oxide layer diffuse through the active layer rather than through said receiver substrate, so that the thickness of said oxide layer is reduced by a predetermined amount .
  • the thickness of the active layer is between about 25 nanometers and about 500 nanometers
  • the predetermined temperature is about 1200 0 C and the predetermined time is between 5 minutes and 5 hours
  • the total thickness of the first and second insulator layers is between 1 nm and 50 nm
  • the predetermined thickness of the active layer and the predetermined temperature are chosen so as to have an average rate of reduction of the oxide layers of about 0.05 nm per minute,- the heating is continued until the first and second oxide layers have been completely removed
  • the insulator is silicon oxide (SiO 2 ) and the donor substrate and receiver substrate are made of silicon (Si) .
  • figures IA to IG are diagrams showing the various successive steps of a first embodiment of the fabrication process according to the invention
  • - - figures 2A to 2F are diagrams showing the various successive steps of a second embodiment of the fabrication process according to the invention
  • - figures 3A to 3C are diagrams showing an alternative embodiment of the two aforementioned processes
  • - figure 4 is a graph showing the concentration C of H + ions per cm 2 as a function of the depth P into a composite substrate resulting from bonding a silicon support substrate that has undergone a thermal oxidation to a germanium donor substrate on which a silicon oxide layer has been deposited
  • figure 5 shows the concentration of O + ions per cm 3 as a function of their depth of implantation within a silicon dioxide (SiO 2 ) layer for various implantation energies.
  • Figure IA shows a substrate 1 called a "donor" substrate, as this is the one which provides the active layer in the hybrid substrate to be obtained.
  • the donor substrate 1 has two opposed faces 11 and 12, called “rear” and “front” faces respectively. It may be a monolayer or multilayer substrate. As an example of a multilayer donor substrate, it is possible to use a bulk substrate coated with an epitaxially grown layer, such as a bulk silicon substrate coated with an epitaxially grown germanium layer.
  • the donor substrate 1 consists at least partly of a semiconductor material, more precisely one of those commonly used in the electronics field, especially silicon .
  • the donor substrate 1 may also be, for example, made of germanium (Ge), gallium nitride (GaN), gallium arsenide (GaAs) or silicon-germanium (SiGe) .
  • a first insulator layer 2 is then formed or deposited on the front face 12 of the substrate 1.
  • the insulator layer 2 has a free surface 20.
  • the insulator constituting the layer 2 is preferably an oxide of a semiconductor material, for example a silicon dioxide (SiO 2 ) . It may also be a nitride or oxynitride of a semiconductor material, for example silicon nitride (Si 3 N 4 ) or germanium oxynitride (Ge x O 7 NJ .
  • the layer 2 dielectric materials having a high permittivity such as, for example, hafnium dioxide (HfO 2 ), alumina (Al 2 O 3 ) , zirconium oxide (ZrO 2 ) , tantalum pentoxide (Ta 2 O 5 ) , titanium dioxide (TiO 2 ) , their nitrides and their silicides.
  • high-k materials such as, for example, hafnium dioxide (HfO 2 ), alumina (Al 2 O 3 ) , zirconium oxide (ZrO 2 ) , tantalum pentoxide (Ta 2 O 5 ) , titanium dioxide (TiO 2 ) , their nitrides and their silicides.
  • the insulator layer 2 When the insulator layer 2 is formed, it is formed by thermal oxidation of the source substrate 1.
  • the insulator layer 2 is an oxide of the constituent semiconductor material of the front face 12 of the substrate 1. This technique is simple to employ, but makes the nature of the insulator 2 dependent on that of the substrate 1 or on part of the substrate 1 if this is a multilayer substrate.
  • a layer of silicon oxide may be obtained by a heat treatment m oxygen of a silicon substrate at a temperature of 900 0 C for a time of 30 minutes until the desired thickness, as will be described later, has been obtained.
  • the insulator layer 2 may also be deposited. This enables its chemical nature not to be dependent on the substrate 1. Thus, it will be possible, for example, to deposit a layer of SiO 2 on a substrate made of germanium or silicon carbide (SiC) .
  • deposition techniques mention may be made of chemical vapor deposition or CVD.
  • the insulator layer 2 is an SiO 2 layer, it is also possible to deposit it by the aforementioned LPCVD technique, but using a tetraethylorthosilicate (TEOS) precursor, this technique being known as LPCVD TEOS.
  • TEOS tetraethylorthosilicate
  • tetraethylorthosilicate Si(OC 2 H 5 )J is introduced in gaseous form into the chamber of the chemical deposition reactor. Under the action of temperature and pressure, the compound decomposes as f ol lows :
  • a step of roughening the free surface 20 of the layer 2 is then carried out, followed by deposition thereon of a second insulator layer 3 so as to form a zone 4 called a "trapping" zone between these two insulator layers 2 and 3.
  • the free surface of the second insulator layer 3 bears the numerical reference 30.
  • the list of materials constituting the second insulator layer 3 is the same as that mentioned above in the case of the insulator layer 2.
  • the insulating materials constituting the layers 2 and 3 may be of the same or different nature - the term "nature” is understood to mean both the chemical composition of the material and its physicochemical properties, for example the density.
  • the layers 2 and 3 may have the same chemical composition but the layer 3 has been obtained by deposition whereas the layer 2 has been obtained by thermal oxidation. Consequently, the layer 3 is less dense and trapping of the gaseous species also takes place therein, in addition to the trapping that occurs m the trapping zone 4.
  • Another example consists in using a layer 2 and a layer 3 that have different chemical compositions, the layer 3 having been deposited and therefore having a lower density than that of the layer 2.
  • a segregation phenomenon may be observed at the interfaces between the various layers, since the atoms that pass through the two insulator layers differ in behavior according to their limiting solubilities, which are different in these two layers. If certain gaseous species are blocked by one of the layers 2 or 3, they will for example be more strongly retained in the trapping zone 4.
  • the second insulator layer 3 can be obtained only by deposition, as if it were to be formed by a heat treatment this would run the risk of modifying the roughness obtained beforehand on the free surface 20 of the layer 2.
  • deposition allows a second insulator layer to be obtained with a lower density than the layer 2, therefore implying better trapping of the species, since a lower density leads to the formation of a larger number of dangling bonds within the insulator.
  • an insulator layer made of SiO 2 for example hydrogen atoms will form covalent bonds with oxygen and/or silicon.
  • the deposition techniques used to deposit the second insulator layer 3 may be chosen from the same as those mentioned above in the case of the insulator layer 2.
  • the purpose of the roughening treatment is to modify the surface state of the face 20 sufficiently to form a trapping zone 4 that can retain the gaseous species possibly present at the various interfaces of the hybrid substrate 6 to be obtained (see figure IG) and limit the formation of surface defects on its transferred active layer 14.
  • the roughness may be expressed by an RMS (Root Mean Square) value.
  • the roughness measurements may in particular be made using an atomic force microscope or AFM.
  • the insulator layer 2 prefferably has a minimum RMS surface roughness of at least 10 nm (10 nanometers) for a scan area of 40 ⁇ m x 40 ⁇ m under the AFM microscope beam.
  • This roughness is sufficiently large for the cavities formed in the surface 20 of the layer 2 not to be filled during deposition of the second insulator layer 3.
  • the roughening treatment may m certain cases have the effect of reducing the thickness of the insulator layer 2, this will preferably have a minimum thickness such that a sufficient insulator thickness remains even after the roughening treatment .
  • the insulator layer 2 it is necessary to have a minimum thickness of the first insulator layer 2 before etching equal to at least 10 times the value expressed in nanometers of the RMS roughness that it is desired to obtain on this layer.
  • the insulator layer 2 it is preferable for the insulator layer 2 to have a minimum thickness of 100 nanometers.
  • the roughening may for example be carried out by chemical etching or by a treatment in a particular plasma .
  • the chemical etching is carried out by immersing the substrate 1, covered with the insulator layer 2, in a bath of a solution known to those skilled in the art as SCl (Standard Clean 1) which comprises a mixture of ammonium hydroxide (NH 4 OH) , hydrogen peroxide (H 2 O 2 ) and deionized water.
  • SCl Standard Clean 1
  • NH 4 OH ammonium hydroxide
  • H 2 O 2 hydrogen peroxide
  • etching treatments they will be applied for 1 to 100 seconds within a temperature range from 2O 0 C to 7O 0 C in order to obtain etched thicknesses of 2 to 80 nm.
  • the plasma treatment consists in placing the substrate covered with the insulator layer 2 m a plasma furnace m which a plasma is formed from a gas or gas mixture under particular temperature and pressure conditions.
  • This plasma treatment is to create partial polymerization reactions on the surface of the first insulator layer 2. More precisely, when a first species in the plasma forms a weak bond at the surface 20 of the insulator, other species will subsequently be polymerized with the first, so that polymerized zones of micromasking of the free surface 20 are created locally. On the scale of one micron, this amounts to locally increasing the roughness of the insulator. This polymerization reaction takes place over a few minutes.
  • the gases that may be used to form the plasma are preferably chosen from: fluorocarbon gases C x F y , such as for example CF 4 , C 4 F 8 and CF 6 ; sulfur fluoride gases of the S x F type, such as SF S or SH 3 F; hydrocarbon gases of the C x H ⁇ type; and also carbon monoxide (CO), NF 3 , hydrogen, argon, chlorinated species of the BCl 3 type or mixtures thereof, and possibly in the presence of oxygen and/or nitrogen.
  • fluorocarbon gases C x F y such as for example CF 4 , C 4 F 8 and CF 6
  • sulfur fluoride gases of the S x F type such as SF S or SH 3 F
  • hydrocarbon gases of the C x H ⁇ type such as SF S or SH 3 F
  • CO carbon monoxide
  • NF 3 hydrogen, argon, chlorinated species of the BCl 3 type or mixtures thereof, and possibly in the presence of oxygen and/or nitrogen.
  • the gases will be chosen according to the chemical nature of the insulator layer 2, so as to be able to polymerize on the surface of this insulator.
  • the quantity of atomic species introduced, and therefore the implantation dose, will depend on the time during which the insulator 2 is exposed to the plasma. The longer this time, the greater the quantity of atoms introduced into the insulator 2.
  • the implantation energy also has an impact on the depth at which these atomic species will be introduced.
  • the type of reactor in which the plasma is formed, the choice of implanted species and the pressure within this reactor also have an influence on the density of the plasma formed.
  • a moderate or even high density of atoms that is to say a density between 10 7 at/cm 3 and 10 13 at/cm 3 , is preferably used.
  • the use of a plasma has the benefit of introducing chemical species at the surface that are highly reactive with hydrogen, for example gases providing oxygen.
  • the implantation energy will preferably be between 100 eV and 2000 eV for implantation doses ranging from IxIO 12 OVcm 2 to lxlO 15 0 + /cm 2 .
  • Trials carried out in an insulator layer of the silicon dioxide (SiO 2 ) type gave the results shown in figure 5.
  • This graph illustrates the concentration of O + ions per cm 2 as a function of the implantation depth within the SiO 2 , this depth being expressed in nanometers.
  • Curves d, e and f correspond to the results obtained for 0" ion implantations performed with energies of 500 eV, 300 eV and 200 eV respectively. In all cases, the implantation dose was lxlO 11 0 * /cm 2 .
  • a densification step on the second insulator layer 3 by subjecting the multilayer stack of figure ID to a heat treatment at about 800 0 C for 1 hour.
  • the purpose of the step of densifymg the insulator layer 3 is to limit the localization of the trapping at the trapping layer 4. However, if the layer 3 is not densified, it also plays a role of trapping the gaseous species.
  • implantation of atomic species is understood to mean any bombardment of atomic or ionic species that can introduce these species into the implanted substrate with a maximum concentration of implanted species at a predetermined depth of the substrate relative to the bombarded surface.
  • This implantation is to form a zone of weakness 13, which forms a boundary separating an active zone 14 from the rest 15 of the substrate.
  • the aforementioned implantation may be carried out m accordance with one of the steps of the process known by the trade name SmartCutTM.
  • zone of weakness 13 may optionally be formed before the formation or deposition of the first insulator layer 2.
  • the zone 13 is formed by implementation after formation or deposition of the layer 2, but before deposition of the insulator layer 3, it being possible for the insulator layer 2 to be roughened before or after the implantation.
  • the implantation for the purpose of forming the zone 13 is carried out, as shown in the figures, that is to say after the second insulator layer 3 has been deposited. This avoids limiting the thermal budget applied during deposition of this layer
  • the active layer 14 is then detached and transferred onto a receiver substrate 5 so as to obtain a hybrid substrate 6.
  • the receiver substrate 5 may be a monolayer or multilayer substrate.
  • an SOI-substra ⁇ e may be mentioned, so as to obtain a double SOI .
  • the receiver substrate is bonded by molecular adhesion onto the free surface 30 of the second insulator layer 3 and then the layer 14 is detached along the zone of weakness 13 by applying mechanical, thermal and/or chemical stresses, using techniques known to those skilled in the art.
  • the bonding interface bears the reference 7.
  • the successive insulator layers 2 and 3 are deposited on the front face of the receiver substrate 5 instead of the front face of the donor substrate 1.
  • the rear and front faces of the substrate 5 bear the references 51 and 52 respectively.
  • Figure 2E shows that the source substrate 1 has undergone the step of atomic species implantation, allowing the zone of weakness 13 to be formed, before being bonded by molecular adhesion onto the insulator layer 3.
  • the source substrate 1 may optionally be temporarily covered with an oxide layer making it easier to implement the aforementioned SmartCut Tt* process, this oxide layer being able to be removed before bonding onto the insulator layer 3.
  • a hybrid substrate 6' is obtained, as shown in figure 2F, which differs from the substrate 6 m that the active layer 14 is in contact with the second insulator layer 3 and not with the first insulator layer 2, as was the case in the first process described above.
  • the bonding interface bears the reference 7' .
  • the trapping layer 4 formed within the hybrid substrates 6 or 6 ' advantageously makes it possible to trap the gaseous species which result from the implantation of atomic species, for the purpose of forming the zone of weakness 13, or which appear at the bonding interface 7 or 7', or when detaching the active layer 14.
  • the hybrid substrate 6 also has the following advantages over the substrate 6' .
  • the gaseous species that do not participate in the formation of the zone of weakness 13 may be trapped directly in the trapping zone 4, something which is not the case with the substrate 6' .
  • the trapping of the gaseous species is slightly more effective with the hybrid substrate 6, as these do not have the bonding interface 7' to pass through as is the case with the substrate 6'.
  • This variant corresponds to additional steps applied after one or other of the two aforementioned processes that make it possible to obtain the hybrid substrates 6 or 6' .
  • UTBox is the acronym for the expression "Ultra Thin Buried Oxide” , which denotes substrates of the SOI type m which the buried oxide layer has a thickness of 50 nm (50 nanometers) or less, or even less than 25 nm .
  • DSB is the acronym for the expression "Direct Semiconductor Bonding” , which denotes a substrate comprising an active layer of semiconductor material directly in contact with the semiconductor receiver substrate.
  • the active layer 14 of the hybrid substrate 6 (see figure 3A) must have a thickness between 25 and 500 nanometers, preferably between 25 and 250 nanometers and even more preferably between 25 and 120 nanometers, and the sum of the thicknesses of the oxide layers 2 and 3 must be between 1 and 100 nanometers, preferably between 1 and 50 nanometers .
  • a heat treatment is carried out so that the thickness of the oxide layer 2, 3 decreases, by diffusion of oxygen through the active layer 14.
  • This heat treatment is carried out in an inert and/or reducing atmosphere, such as an atmosphere containing argon or hydrogen, or a mixture of the two.
  • figure 3A shows an axis x that extends perpendicular to the plane of the layers of the hybrid substrate 6, the origin 0 of which is at the center of the oxide layer and on which the positive values are directed toward the active layer 14 and the negative values toward the receiver substrate 5.
  • the substrate 6 has two diffusion regions, namely diffusion through the active layer 14 and through the bulk receiver substrate 5, these two regions being separated by the oxide layers 2, 3, the overall thickness of which is d oX .
  • the diffusion equation is then: in which C(x,t) is the oxygen concentration at a time t and at a point x, and D(T) is the oxygen diffusion coefficient (m units of cm 2 /s) in the semiconductor material .
  • the rate of dissolution of oxide corresponds to the difference between the oxygen flux passing through the active layer 14 and the oxygen flux passing through the receiver substrate 5 at the interfaces with the oxides 2 and 3.
  • the active layer 14 is thin enough, some of the oxygen of the oxide layers 2 and 3 diffuses through it and evaporates into the atmosphere on its surface .
  • the atmosphere in which the reaction takes place is inert, or more precisely non-oxidizmg .
  • the following reaction occurs at the surface of the active layer 14 if the inert atmosphere contains hydrogen and if the active layer 14 is silicon :
  • the oxygen present in the oxide layers 2 and 3 cannot reach the free surface of the substrate 5, namely the rear surface 51.
  • the Applicant has found that if the active layer 14 is thin enough and if the atmosphere m which the heat treatment takes place is inert and/or reducing, even if the thickness of the oxide layers 2 and 3 temporarily increases slightly owing to the supply of oxygen coming from the substrate 5, typically after a few seconds of treatment, the oxygen present in the oxide layers 2 and 3 starts to dissolve, so that the thickness of these layers decreases .
  • the oxide dissolution time, which allows the oxide layers 2, 3 of thickness d oy to be reduced by a predetermined value ⁇ d ox is:
  • the active layer 14 of semiconductor material is made of single-crystal silicon
  • N 4.22xlO 22
  • the time is 1.86xlO "12 xe l4 ° 4eV ⁇ > , k representing Boltzmann's constant and T the temperature in kelvin.
  • the Applicant has demonstrated that the main parameters affecting the dissolution time are the annealing temperature and the thickness of the active layer 14 and that moreover the result does not depend on the oxygen concentration in the receiver substrate 5.
  • the temperature and duration of the heat treatment, and also the thickness of the oxide layers 2 and 3 and the thickness of the active layer 14, will be chosen so as to incite oxygen present m the oxide layers 2 and 3 to diffuse through the active layer 14, rather than through the receiver substrate 5.
  • the minimum annealing conditions, in an atmosphere containing argon and/or hydrogen, allowing an SiO 2 layer 2 nanometers in thickness with a silicon active layer 14 100 nanometers in thickness to dissolve are the following:
  • the thickness of the active layer 14 and the heat treatment temperature determine the average rate of reduction of the oxide layers 2 and 3. The greater the thickness of the layer 14, the lower the rate of reduction of the thickness of the layers 2 and 3. The higher the temperature, the more rapid the dissolution of the layers 2 and 3.
  • the thickness of the active layer 14 and the temperature will be predetermined so as to have an average rate of reduction of the oxide layers 2 and 3 of at least about 0.05 nanometers/mm.
  • a temperature of 1200 0 C and a thickness of the single-crystal silicon active layer 14 of less than 250 nanometers will then be chosen.
  • Figure 3B illustrates the hybrid substrate 60 of the UTBox type obtained after diffusion of oxygen through the active layer 14. This layer is thicker and bears the reference 14' , while the oxide layers 2 and 3 are shown by a single thinner layer referenced 8.
  • the treatment may also be continued at temperatures and for durations such that the oxide layers 2 and 3 completely disappear so that the DSB substrate 600, with an even thicker active layer than the layer 14', and bearing the numerical reference 14", is obtained.

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Abstract

L'invention concerne un procédé de fabrication d'un substrat hybride (6) pouvant être utilisé dans les domaines de l'optique, de l'électronique ou de l'optoélectronique. Ce procédé est remarquable en ce qu'il comprend les étapes suivantes, consistant à : a) former ou déposer une première couche isolante (2) sur un premier substrat choisi parmi un substrat donneur et un substrat récepteur, tous deux constitués d'un matériau semi-conducteur ; b) réaliser un traitement destiné à accroître la rugosité de la surface libre de ladite première couche isolante (2) ; c) déposer sur cette première couche une seconde couche isolante (3) de manière à former une zone de piégeage (4) entre elles ; d) provoquer l'adhérence du substrat qui n'a pas été utilisé à l'étape a) sur ladite seconde couche isolante (3) par adhésion moléculaire (collage de plaquettes) ; et e) transférer une couche active (14) formée par l'implantation d'espèces atomiques dans ledit substrat donneur, ladite zone de piégeage (4) étant capable de retenir les espèces gazeuses éventuellement présentes dans les diverses interfaces du substrat hybride et de limiter la formation de défauts à la surface de la couche active.
PCT/IB2008/000050 2007-01-15 2008-01-07 Procédé de fabrication d'un substrat hybride WO2008087516A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0700265 2007-01-15
FR0700265A FR2911430B1 (fr) 2007-01-15 2007-01-15 "procede de fabrication d'un substrat hybride"

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WO2008087516A1 true WO2008087516A1 (fr) 2008-07-24

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US (1) US7632739B2 (fr)
FR (1) FR2911430B1 (fr)
WO (1) WO2008087516A1 (fr)

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US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
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US9111997B2 (en) 2007-03-26 2015-08-18 Semiconductor Energy Laboratory Co., Ltd. SOI substrate and method for manufacturing SOI substrate
US8034694B2 (en) 2007-04-03 2011-10-11 Semiconductor Energy Laboratory Co., Ltd. SOI substrate, method for manufacturing the same, and semiconductor device
US8823063B2 (en) 2007-04-03 2014-09-02 Semiconductor Energy Laboratory Co., Ltd. SOI substrate, method for manufacturing the same, and semiconductor device
US9536774B2 (en) 2007-04-03 2017-01-03 Semiconductor Energy Laboratory Co., Ltd. SOI substrate, method for manufacturing the same, and semiconductor device
US8048728B2 (en) 2007-04-13 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Display device, method for manufacturing display device, and SOI substrate
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
CN104900615A (zh) * 2015-05-08 2015-09-09 武汉新芯集成电路制造有限公司 一种提高键合力的方法及一种半导体键合结构

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US7632739B2 (en) 2009-12-15
FR2911430B1 (fr) 2009-04-17
FR2911430A1 (fr) 2008-07-18
US20080171443A1 (en) 2008-07-17

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