WO2008077659A1 - Composant électrique - Google Patents

Composant électrique Download PDF

Info

Publication number
WO2008077659A1
WO2008077659A1 PCT/EP2007/061347 EP2007061347W WO2008077659A1 WO 2008077659 A1 WO2008077659 A1 WO 2008077659A1 EP 2007061347 W EP2007061347 W EP 2007061347W WO 2008077659 A1 WO2008077659 A1 WO 2008077659A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
separation
electrical component
undercut
wafer
Prior art date
Application number
PCT/EP2007/061347
Other languages
German (de)
English (en)
Inventor
Lutz Rauscher
Frieder Haag
Anton Doering
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2008077659A1 publication Critical patent/WO2008077659A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention is based on an electrical component having at least one chip and a cladding, wherein a surface of the chip is part of a surface of the electrical component, wherein the cladding surrounds the chip at an edge of the surface of the chip L 5.
  • the envelope of such electrical components consists for example of an injection molded plastic housing.
  • the chips have substantially vertical edges. It could possibly come to a replacement of the wrapping from the chip. In the 10 episode moisture could penetrate into the device, which should be prevented.
  • the invention is based on an electrical component having at least one chip and a cladding, wherein a surface of the chip is part of a surface of the electrical component, wherein the cladding encloses the chip at an edge of the surface of the chip 30.
  • the essence of the invention is that the chip has an undercut. The undercut advantageously prevents the wrapping from detaching from the chip.
  • An advantageous embodiment of the electrical component according to the invention provides 35 that the envelope the chip at least in a region of the undercut embraces. It is also advantageous that the envelope rests against the chip at least in the region of the undercut.
  • a particularly advantageous embodiment of the electrical component according to the invention provides that the enclosure consists of a potting compound. It is advantageous if a sealant 5 is arranged on the undercut. It is also advantageous if the potting compound itself fills the undercut.
  • the invention is also directed to a method for producing an electrical component having at least one chip with an undercut with two main L 0 process steps, namely:
  • the first and second dividing distances are different.
  • the wafer is completely severed as a result of the process, so that isolated chips are created with an undercut in an edge region.
  • the chips both isolated as well as the same desired undercut can be created.
  • first separation step is performed from a first side and the second separation step from a second opposite side.
  • An advantageous embodiment of the method provides that the first separation step and / or the second separation step by means of sawing. Advantageously, this can be achieved by sawing
  • Another advantageous embodiment of the method provides that the first separation step and / or the second separation step takes place by means of etching.
  • Figure 1 shows a first embodiment of an electrical component according to the invention
  • FIG. 2 shows a second embodiment of an electrical component according to the invention.
  • FIG. 3 shows the essential steps of a method according to the invention for
  • Figures 4 a-d show the processing of a wafer with the method according to the invention in a development.
  • FIG. 1 shows a first embodiment of an electrical component according to the invention. Shown is an electrical device 10 having at least one chip 20 and a cladding 30.
  • the chip 20 is a microchip, i. a microelectronic
  • Enclosure 30 in this example is an injection-molded housing, which encloses the chip 20. In this case, an area 40 of the chip 20 remains free.
  • the envelope 30 surrounds the chip 20 circumferentially characterized at the edge of the surface.
  • the chip 20 has at this edge an undercut 50, which of the
  • injection-molded housing is filled.
  • the injection-molded housing engages around the chip 20 and this is secured against detachment from the injection-molded housing.
  • the lowest possible height of the electrical component 10 is ensured.
  • FIG. 2 shows a second embodiment of an electrical component according to the invention.
  • the injection molded case does not fill the undercut 50 here.
  • a sealant 60 such as a resin or a particularly adhesive or elastic adhesive is disposed in the undercut.
  • the chip 20 is secured against detachment from the injection-molded housing. 35 - A -
  • the injection-molded housing surrounds the chip 20 and this is secured against detachment from the injection-molded housing.
  • the undercut 50 is not completely filled by the injection-molded housing, but there remains a partial space on the chip 20, in which the sealing means 60 is arranged.
  • the electrical component 10 is additionally protected against penetration of substances from the environment, such as moisture, at the edge of the surface 40.
  • FIG. 3 shows the essential steps of a method according to the invention for
  • a wafer in particular a semiconductor wafer such as a silicon wafer is provided.
  • the wafer is separated in a separation region with a first separation distance to a first depth.
  • the second essential manufacturing step A
  • the wafer is separated in the separation region with a second separation distance to a second depth.
  • the first and the second separation distance are different from each other.
  • the wafer is completely severed and thus individual chips 20 with an undercut 50 in their edge regions created by the two-step separation with different separation widths
  • the separation can be done for example by sawing. It can to
  • step A and step B Production of the different separation distances in step A and step B different width saw blades are used.
  • the two separation steps may be performed from the same side of the wafer or from a first side and a second opposite side. It should be noted, however, that the separation steps, here
  • FIGS. 4 a-d show the processing of a wafer with the method according to the invention in a further development.
  • FIG. 4a shows the provision of a wafer 100.
  • FIG. 4b shows the first separation, here by sawing in the first essential production step A. The separation step A takes place from a first side, in one
  • FIG. 4c shows the second separation, here likewise by sawing in the second essential production step B. The wafer is rotated to this end.
  • the separation step B takes place from a second side, which is opposite to the first side.
  • the separation step B takes place in the separation area, substantially along the center line 110, with a second separation distance 140 to a second separation depth 150, such that the wafer 100 is completely severed along the center line 110.
  • FIG. 4 d shows an isolated chip 20, which has an undercut 50 as a result of the two-stage separation according to the invention with different separation widths 120 and 140.
  • the separation can be done instead of sawing by laser ablation or etching.
  • the various separation processes, here sawing and etching can also be combined by carrying out the first separation step A with a first separation process and the second separation step B with a second separation process.
  • sawing and etching can also be combined by carrying out the first separation step A with a first separation process and the second separation step B with a second separation process.
  • the separation step with the larger separation distances by means of sawing with a wide saw blade and the separation step with the smaller separation distances by means of a, in particular anisotropic, etching process can be performed.
  • the separation step with a larger separation distance by means of etching and the separation step with a smaller separation distance can be carried out by means of laser processing.
  • the undercut 50 is shown schematically in all figures, in a rectangular shape. However, according to the invention it can also have any other shape that can be predetermined by the selected separation method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne un composant électrique (10) comprenant au moins une puce (20) et une enveloppe (30), une surface (40) de la puce (20) formant une partie d'une surface du composant électrique (10), l'enveloppe (30) enfermant la puce (20) sur un bord de la surface de la puce (20). L'idée sous-jacente à l'invention réside en ce que la puce (20) présente une contre-dépouille (50). L'invention concerne également un procédé pour la fabrication d'un composant électrique (10) avec au moins une puce (20) dotée d'une contre-dépouille (50).
PCT/EP2007/061347 2006-12-21 2007-10-23 Composant électrique WO2008077659A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006060629.9 2006-12-21
DE200610060629 DE102006060629A1 (de) 2006-12-21 2006-12-21 Elektrisches Bauelement

Publications (1)

Publication Number Publication Date
WO2008077659A1 true WO2008077659A1 (fr) 2008-07-03

Family

ID=38969486

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2007/061347 WO2008077659A1 (fr) 2006-12-21 2007-10-23 Composant électrique

Country Status (2)

Country Link
DE (1) DE102006060629A1 (fr)
WO (1) WO2008077659A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10206661A1 (de) * 2001-02-20 2002-09-26 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip
US20040161910A1 (en) * 1999-03-11 2004-08-19 Akio Nakamura Semiconductor apparatus and semiconductor apparatus manufacturing method
WO2004082018A2 (fr) * 2003-03-11 2004-09-23 Infineon Technologies Ag Composant electronique comprenant une puce semi-conductrice et un boitier en plastique et son procede de production

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040161910A1 (en) * 1999-03-11 2004-08-19 Akio Nakamura Semiconductor apparatus and semiconductor apparatus manufacturing method
DE10206661A1 (de) * 2001-02-20 2002-09-26 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip
WO2004082018A2 (fr) * 2003-03-11 2004-09-23 Infineon Technologies Ag Composant electronique comprenant une puce semi-conductrice et un boitier en plastique et son procede de production

Also Published As

Publication number Publication date
DE102006060629A1 (de) 2008-06-26

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