Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/65—Lateral DMOS [LDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
  • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
  • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/351—Substrate regions of field-effect devices
  • H10D62/357—Substrate regions of field-effect devices of FETs
  • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
  • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Definitions

• the present invention generally relates to a semiconductor device and a method for forming a semiconductor device, and more particularly relates to a high power transistor.
• Power devices are integrated circuits (IC) that are specifically designed to tolerate the high currents and voltages that are present in power applications, such as motion control, air bag deployment, and automotive fuel injector drivers, hi particular applications, the power devices are required to block voltages in both a "positive” direction, where a voltage is applied to the drain side of a particular transistor with the source and the body shorted together and held at ground, and a "negative” direction, in which a negative voltage is applied to the drain side of the transistor with source and body held at ground.
• the ability to block both positive and negative voltages is known as "bi-directional" voltage blocking.
• FIG. 2 is a cross-sectional side view of the semiconductor substrate of FIG. 1 with a buried layer formed in an upper surface thereof;
• FIG. 3 is a cross-sectional side view of the semiconductor substrate of FIG.2 with an epitaxial layer formed thereon;
• FIG. 4 is a cross-sectional side view of the semiconductor substrate of FIG. 3 with a plurality of isolation regions formed thereon;
• FIG. 5 is a cross-sectional side view of the semiconductor substrate of FIG. 4 with a high voltage well formed in the epitaxial layer;
• FIG. 6 is a cross-sectional side view of the semiconductor substrate of FIG. 5 with a body region formed in the epitaxial layer;
• FIG. 7 is a cross-sectional side view of the semiconductor substrate of FIG. 6 with a well region formed in the epitaxial layer;
• FIG. 8 is a cross-sectional side view of the semiconductor substrate of FIG. 7 with a gate dielectric and gate electrode formed on the upper surface thereof;
• FIG. 9 is a cross-sectional side view of the semiconductor substrate of FIG. 8 with a lightly doped region formed in the well region;
• FIG. 10 is a cross-sectional side view of the semiconductor substrate of FIG. 9 with a suicide block layer formed partially over the gate electrode and the lightly doped region;
• FIG. 11 is a cross-sectional side view of the semiconductor substrate of FIG. 10 with a body contact region formed within the well region;
• FIG. 13 is a cross-sectional schematic view of the semiconductor substrate of FIG. 12 illustrating electrical connections being made to the various contact regions;
• FIG. 14 is a graph illustrating body current to drain current ratios for various gate voltages.
• FIGs. 1-14 are merely illustrative and may not be drawn to scale.
• the substrate 20 is a "P-type" semiconductor substrate and is doped with boron (B) to a concentration of approximately 2.0 x 10 1 atoms per cm 3 .
• B boron
• the substrate 20 may be a semiconductor wafer with a diameter of, for example, approximately 150, 200, or 300 millimeters. Additionally, although not specifically illustrated, the substrate 20 may be divided into multiplies dies, or "dice,” as commonly understood in the art.
• the following process steps may be shown as being performed on only a small portion of the substrate 20, it should be understood that each of the steps may be performed on substantially the entire substrate 20, or multiple dice, simultaneously.
• a buried layer 28 is first formed in the upper surface 22 of the substrate 20.
• the buried layer 28 is formed using ion implantation and has a thickness of, for example, between approximately 1 and 2 microns.
• the ion implantation process changes the semiconductor material of the substrate 20 within the buried layer 28 to have a second conductivity type (i.e., a second dopant type), as is commonly understood.
• the buried layer 28 includes "N-type" semiconductor material doped with a relatively high concentration of antimony (Sb) of approximately 1.0 x IO 19 atoms per cm 3 .
• an epitaxial layer 32 is then grown on the upper surface 22 of the substrate 20.
• the epitaxial layer 32 may have a thickness of approximately 2 and 5 microns, and the semiconductor material of the epitaxial layer 32 may have the first conductivity type (i.e., P-type).
• the epitaxial layer 32 is doped with boron to a concentration approximately 2.0 x 10 15 atoms per cm 3 .
• the epitaxial layer 32 may also have an upper surface 36.
• first, second, third, and fourth shallow trench isolation (STI) regions 38, 40, 42, and 44 are then formed on the upper surface 36 of the epitaxial layer 32.
• the STI regions 38, 40, 42, and 44 may be formed by etching trenches into the upper surface 36 of the epitaxial layer 32 and filling the trenches with an insulating material, such as a field oxide.
• the STI regions 38, 40, 42, and 44 may have thicknesses of, for example, between 0.3 and 1 micron. The widths of the STI regions may be appropriately adjusted depending on the voltage requirements on the semiconductor device and are typically between 0.5 and 5 microns.
• a body region 56 (e.g., P-body) is next formed in the upper surface 36 of the epitaxial layer 32.
• the body region 56 may also be formed using ion implantation and have the first conductivity type.
• the body region 56 may be a P-type region that is doped with boron to a concentration of approximately 2.0 x 10 17 atoms per cm 3 .
• the body region 56 may have a thickness 58 of approximately 1.6 microns, contact one end of the second STI region 40, and surround the third STI region 42.
• a gap 60 of approximately 0.2 microns may lie between the body region 56 and the N-type drift region 50 across the upper surface 36 of the epitaxial layer 32.
• a "sinker" region 62 is then formed within the epitaxial layer 32 using, for example, ion implantation, as shown in FIG. 7. As is shown, the sinker region 62 extends between the upper surface 36 of the epitaxial layer 32 and the buried layer 28, as well as contacts the first STI region 38 and an end of the second STI region 40.
• the sinker region 62 is doped to have N-type conductivity (i.e., the second conductivity type and/or dopant type) with phosphorous having a concentration of approximately 5.0 x 10 17 atoms per cm .
• a gate dielectric 64 and a gate electrode 66 are formed on the upper surface 36 of the epitaxial layer 32. As shown, the gate dielectric 64 and the gate electrode 66 may lie across the gap 60 between the body region 56 and the N-type drift region 50 to partially cover the body region 56, the N-type drift region 50, and the fourth STI region 44.
• the gate dielectric 64 is made of an insulating material, such as silicon oxide, and has a thickness of, for example, approximately 300 angstroms.
• the gate electrode 66 in one embodiment, is made of poly-silicon and has a thickness of approximately 0.2 microns.
• the gate electrode has a gate length 68 of, for example, approximately 2.5 microns.
• a suicide block layer 74 is then deposited over a portion of the gate electrode 66 and an adjacent portion of the lightly doped region 70 to a distance 76 away from the gate electrode 66, as illustrated in FIG. 10.
• the suicide block layer 74 may be made of a dielectric, such as silicon dioxide (SiO 2 ) or silicon nitride (SiN), and have a thickness of approximately 0.1 microns.
• a source contact region 80, a drain contact region 82, and an isolation (ISO) contact region 84 are formed in the upper surface 36 of the epitaxial layer 32.
• the source contact region 80 is formed between the third STI region 42 and the suicide block layer 74 to occupy the portion of the lightly doped region 70 that is not covered by the suicide block layer 74.
• the size of the lightly doped region 70 is reduced to only the portion of the original lightly doped region 70 that was covered by the suicide block layer 74 and now acts as a "source separation" region between the gate electrode 66 and the source contact region.
• the substrate 20 may be sawed into individual microelectronic dice, or semiconductor chips, packaged, and installed in various electronic or computing systems. As illustrated in FIG. 13, electrical connections 86 are made to the body contact region 17, the source contact region 80, the drain contact region 82, the ISO contact region 84 and the gate electrode 66. During operation, the lightly doped region 70 between the source contact region 80 and the gate electrode 66 increases the breakdown voltage of the device and prevents rapid increase in leakage current due to electric field enhancement.
• the high voltage well may extend across the epitaxial layer below the body region so that the body region is formed adjacent to, or within, the high voltage well.
• P-type being the first dopant and conductivity type
• N-type being the second dopant and conductivity type
• the dopant types of the various regions may be switched, as is commonly understood in the art.
• the dopant concentrations described above are merely examples and may be varied.
• the invention provides a semiconductor device.
• the semiconductor device may include a first semiconductor layer having a first dopant type, a second semiconductor layer having a second dopant type over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer.
• a first semiconductor region within the third semiconductor layer may have the second dopant type.
• a second semiconductor region within the third semiconductor layer between the first semiconductor region and the second semiconductor layer may have the first dopant type.
• a third semiconductor region within the third semiconductor layer above the second semiconductor region may have the first dopant type.
• a fourth semiconductor region within the third semiconductor layer adjacent to the third semiconductor region may have a first concentration of the second dopant type.
• a source contact region within the third semiconductor layer adjacent to the third semiconductor region and adjacent to the fourth semiconductor region may have a second concentration of the second dopant type.
• the second concentration may be higher than the first concentration.
• the semiconductor device may also include a gate electrode over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region. The gate electrode may be adjacent to and on a side of the fourth semiconductor region opposing the source contact region.
• the third semiconductor region may be next to the first semiconductor region and separated from the first semiconductor region by a distance.
• the third semiconductor region may be disposed inside the first semiconductor region.
• the second concentration may be at least 100 times greater than the first concentration.
• the second concentration may be approximately 1000 times greater than the first concentration.
• the third semiconductor layer may also include a body contact region having the second dopant type adjacent to the third semiconductor region and a drain contact region having the second dopant type adjacent to the first semiconductor region.
• the third semiconductor layer may also include a fifth semiconductor region having the second dopant type adjacent to the second semiconductor layer, and an isolation contact region having the second dopant type adjacent to the fifth semiconductor region.
• the third semiconductor layer may also include a plurality of trench isolation regions.
• the first dopant type may be P-type, and the second dopant type may be N-type.
• the third semiconductor region may be between the first and fifth semiconductor regions.
• the semiconductor device may also include a suicide block layer over at least a portion of the fourth semiconductor region and the gate electrode.
• the microelectronic assembly may also include a gate electrode over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region of the epitaxial layer.
• the gate electrode may be adjacent to and on a side of the fourth semiconductor region opposing the source contact region.
• the fourth semiconductor region and the source contact region may be doped with a dopant of the second conductivity type.
• the fourth semiconductor region may have a first concentration of the dopant, and the source contact region may have a second concentration of the dopant. The second concentration may be higher than the first concentration.
• the second concentration may be at least 100 times greater than the first concentration.
• the second concentration may be approximately 1000 times greater than the first concentration.
• the epitaxial layer may also include a fifth semiconductor region having the second conductivity type adjacent to the second layer of the semiconductor substrate and an isolation contact region having the second conductivity type adjacent to the fifth semiconductor region.
• the first dopant type may be P-type and the second dopant type may be N-type.
• the invention further provides a method for constructing a semiconductor device.
• the method may include forming a buried layer in a semiconductor substrate having a first dopant type, the buried layer having a second dopant type, forming an epitaxial semiconductor layer over the buried layer, the epitaxial semiconductor layer having the first dopant type, forming a first semiconductor region in the epitaxial semiconductor layer, the first semiconductor region having the second dopant type, a second semiconductor region being defined in the epitaxial semiconductor layer between the first semiconductor region and the buried layer, the second semiconductor region having the first dopant type, forming a third semiconductor region in the epitaxial semiconductor layer, the third semiconductor region having the first dopant type, forming a gate electrode over at least a portion of the first semiconductor region and over at least a portion of the third semiconductor region, forming a fourth semiconductor region in the epitaxial semiconductor layer adjacent t ⁇ the third semiconductor region and adjacent to the gate electrode, the fourth semiconductor region having a first concentration of the second dopant type, forming
• the method may also include forming a fifth semiconductor region in the epitaxial semiconductor layer adjacent to the second layer of the semiconductor substrate, the fifth semiconductor region having the second dopant type, and forming an isolation contact region in the epitaxial semiconductor layer adjacent to the fifth semiconductor region, the isolation contact region having the second dopant type.
• the method may also include forming a plurality of trench isolation regions in the epitaxial semiconductor layer, a first of the trench isolation regions being between the fifth semiconductor region and third semiconductor region, a second of the trench isolation regions being between the body contact region and the source contact region, and a third of the trench isolation regions being between the gate electrode and the drain contact region.
• the second concentration may be at least 100 times greater than the first concentration.
• the method may also include doping the second semiconductor region with the second dopant type.
• the first dopant type may be P-type and the second dopant type may be N-type.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Bipolar Transistors (AREA)

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• 2005
  • 2005-10-31 US US11/264,068 patent/US7276419B2/en active Active
• 2006
  • 2006-10-18 JP JP2008550308A patent/JP2009521131A/ja active Pending
  • 2006-10-18 EP EP06851955.2A patent/EP1966826A4/en not_active Withdrawn
  • 2006-10-18 WO PCT/US2006/040873 patent/WO2008076092A2/en not_active Ceased
  • 2006-10-18 KR KR1020087013091A patent/KR20080073313A/ko not_active Ceased
  • 2006-10-30 TW TW095139951A patent/TWI409946B/zh not_active IP Right Cessation

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