WO2008072510A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
WO2008072510A1
WO2008072510A1 PCT/JP2007/073454 JP2007073454W WO2008072510A1 WO 2008072510 A1 WO2008072510 A1 WO 2008072510A1 JP 2007073454 W JP2007073454 W JP 2007073454W WO 2008072510 A1 WO2008072510 A1 WO 2008072510A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
protruding electrode
bonding surface
semiconductor
semiconductor device
Prior art date
Application number
PCT/JP2007/073454
Other languages
French (fr)
Japanese (ja)
Inventor
Tatsuya Katoh
Satoru Kudose
Tomokatsu Nakagawa
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2008072510A1 publication Critical patent/WO2008072510A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor device, for example, an SOF (System equipped with an interposer substrate that is mounted on a film substrate and made of silicon, and a semiconductor element that is mounted on the interposer substrate to drive liquid crystal.
  • SOF System equipped with an interposer substrate that is mounted on a film substrate and made of silicon, and a semiconductor element that is mounted on the interposer substrate to drive liquid crystal.
  • the present invention relates to a semiconductor device suitable for On Film. Background art
  • FIG. 8 is a schematic cross-sectional view showing a configuration of a conventional semiconductor device 91.
  • the semiconductor device 91 includes a film substrate 98.
  • the film substrate 98 has a hole 82.
  • a wiring pattern 81 is formed on the surface of the film substrate 98.
  • the semiconductor device 91 is provided with an interposer substrate 92.
  • a plurality of protruding electrodes 90 made of gold are provided at positions facing the wiring pattern 81 on the surface of the interposer substrate 92 on the film substrate 98 side.
  • the interposer substrate 92 is mounted on the film substrate 98 having the wiring pattern 81 via the protruding electrodes 90! /.
  • a plurality of substrate protruding electrodes 94 made of gold are provided at positions facing the holes 82 on the surface of the interposer substrate 92 on the film substrate 98 side.
  • a semiconductor element 93 is provided in the hole 82 of the Finolem substrate 98.
  • a plurality of element protrusion electrodes 95 made of gold are provided at positions facing the substrate protrusion electrodes 94 on the surface of the semiconductor element 93 on the interposer substrate 92 side.
  • the semiconductor element 93 is mounted on the interposer substrate 92 via the element protruding electrode 95 and the substrate protruding electrode 94.
  • a sealing resin 99 is sealed between the semiconductor element 93 and the film substrate 98, and between the interposer substrate 92, the final substrate 98, and the semiconductor element 93.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-207566 (published July 22, 2004)
  • the present invention has been made in view of the above problems, and an object thereof is to realize a semiconductor device capable of stabilizing the bonding quality between a semiconductor element and an interposer substrate.
  • a semiconductor device includes an interposer substrate that is mounted on a mounting substrate and configured by a semiconductor, and a semiconductor element that is mounted on the interposer substrate.
  • the substrate has a substrate protruding electrode formed on the semiconductor element side, and the semiconductor element has an element protruding electrode to be bonded to the substrate protruding electrode.
  • the area of the element bonding surface of the element protruding electrode is The area of the substrate bonding surface of the substrate protruding electrode is larger.
  • another semiconductor device includes an interposer substrate that is mounted on a mounting substrate and configured of a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate includes the semiconductor
  • a semiconductor device having a substrate protruding electrode formed on an element side, wherein the semiconductor element has an element protruding electrode bonded to the substrate protruding electrode; The area of the element protruding electrode is larger than the area of the substrate protruding electrode when seen through from the interposer substrate side or the semiconductor element side.
  • another semiconductor device includes an interposer substrate that is mounted on a mounting substrate and is configured of a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate includes: In a semiconductor device having a substrate protruding electrode formed on a semiconductor element side, and the semiconductor element having an element protruding electrode bonded to the substrate protruding electrode, the element bonding surface of the element protruding electrode in a side view Is longer than the length of the substrate bonding surface of the substrate projection electrode.
  • the element protruding electrode is in contact with a surface having a large area among the substrate bonding surfaces of the substrate protruding electrode. It is possible to suppress the variation of the bonding load and stabilize the bonding quality.
  • the protruding electrode is generally called “bump” and is formed on the surface of the electrode portion and bonded to an object to be electrically connected.
  • the element bonding surface and the substrate bonding surface have a rectangular shape, and the major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other.
  • the width of the element bonding surface in the minor axis direction is wider than the width of the substrate bonding surface in the minor axis direction! /.
  • the length in the major axis direction of the element bonding surface and the length in the major axis direction of the substrate bonding surface are equal to each other! /.
  • the side wall along the major axis direction of the substrate protruding electrode bites into the element bonding surface of the element protruding electrode to increase the bonding strength
  • the side wall of the substrate protruding electrode bites into the element bonding surface. Since the joints are long and tightly joined, the joint strength is increased and the joint quality is improved.
  • the length of the substrate bonding surface in the long axis direction is longer than the length of the element bonding surface in the long axis direction.
  • the element bonding surface is arranged so as to surround the substrate bonding surface when viewed from a direction perpendicular to the interposer substrate, and the element bonding surface and the substrate
  • the bonding surface has a rectangular shape, and the major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other, and the element bonding surface is viewed from a direction perpendicular to the interposer substrate.
  • the one side is arranged 5 to 10 ⁇ m away from the corresponding one side of the substrate bonding surface! /,
  • the force S is preferable.
  • the height of the element protruding electrode and the height and force of the substrate protruding electrode are different from each other.
  • the element protruding electrode or the substrate protruding electrode can be lowered, the height variation can be reduced, and the bonding quality can be stabilized.
  • the substrate protruding electrode has a low level when the interposer substrate is connected to the tape carrier. , And the gap between the tape carrier wiring and the end of the interposer board may not be sufficient, and the wiring force of the tape carrier may contact the end of the interposer board, causing a short circuit between the wiring conductors of the tape carrier.
  • the substrate protruding electrode is made at 15 m and the substrate protruding electrode and the tape carrier wiring are connected, the distance between the tape carrier wiring and the end of the interposer substrate can be secured about 9 m.
  • the height is 10 to 15 m, a sufficient distance between the tape carrier spring and the end of the interposer substrate can be secured, and a short circuit between the wirings can be avoided. Further, since the element protruding electrode does not have such a concern, it can be made lower than the height of the substrate protruding electrode. Therefore, in the semiconductor device according to the present invention, it is preferable that the height of the element protruding electrode is lower than the height of the substrate protruding electrode! /.
  • the element protruding electrode can be made lower than the substrate protruding electrode, the variation in the height of the element protruding electrode can be reduced, the amount of Au used can be reduced, and the bonding quality can be stabilized. That's the power S.
  • the height of the element protruding electrode is 5 to 8111.
  • the element protrusion electrode can be lowered, the height variation of the element protrusion electrode can be reduced, the amount of Au used can be reduced, the cost can be reduced, and the bonding quality can be stabilized.
  • a height of the substrate protruding electrode is 10 to 15111.
  • the substrate protruding electrode has higher hardness than the element protruding electrode.
  • another semiconductor device includes an interposer substrate formed of a semiconductor mounted on a mounting substrate, and a semiconductor element mounted on the interposer substrate,
  • the interposer substrate has a substrate protruding electrode formed on the semiconductor element side, and the semiconductor element has a terminal bonded to the substrate protruding electrode.
  • the terminal is made of aluminum and the substrate protruding electrode is made of gold.
  • the bonding quality is improved by general A1-Au bonding such as wire bonding. Stabilization can be achieved.
  • Still another semiconductor device includes an interposer substrate that is mounted on a mounting substrate and configured by a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate includes the semiconductor element.
  • the element protrusion electrode can be configured to be lower than the substrate protrusion electrode, the variation in the height of the element protrusion electrode can be reduced, the amount of Au used can be reduced, and the bonding quality can be stabilized.
  • Still another semiconductor device includes an interposer substrate that is mounted on a mounting substrate and configured of a semiconductor, and a semiconductor element that is mounted on the interposer substrate.
  • the interposer substrate includes the semiconductor element.
  • the semiconductor element has a substrate protruding electrode formed on a side, and the semiconductor element has a device protruding electrode bonded to the substrate protruding electrode.
  • the substrate bonding surface of the protruding electrode has a rectangular shape, the major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other, and the width of the element bonding surface in the minor axis direction is The major axis direction length of the substrate bonding surface, which is wider than the minor axis width of the substrate bonding surface, is longer than the major axis length of the element bonding surface.
  • the side wall along the long axis direction of the substrate protruding electrode does not only bite into the element bonding surface of the element protruding electrode, but the side wall along the short axis direction of the element protruding electrode causes the substrate protruding electrode to Bite in the opposite direction to the substrate bonding surface. For this reason, the substrate protruding electrode and the element protruding electrode are bonded so as to be held together, the bonding strength is further increased, and the bonding quality is further improved.
  • the semiconductor device according to the present invention is configured such that, even when a displacement occurs in the contact position between the substrate protruding electrode and the element protruding electrode, the element protruding electrode is out of the substrate bonding surface of the substrate protruding electrode. It is possible to contact a surface with a large area, and fluctuations in the bonding load can be suppressed to stabilize the bonding quality.
  • FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment.
  • FIG. 2 is a schematic cross-sectional view showing the dimensional relationship between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a dimensional relationship between a substrate protruding electrode and an element protruding electrode according to the embodiment.
  • FIG. 4 is a schematic cross-sectional view showing another dimensional relationship between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment.
  • FIG. 5 is a schematic cross-sectional view showing still another dimensional relationship between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment.
  • FIG. 6 is a schematic cross-sectional view showing another dimensional relationship between the substrate protruding electrode and the element protruding electrode according to the embodiment.
  • FIG. 7 is a schematic cross-sectional view showing still another dimensional relationship between the substrate protruding electrode and the element protruding electrode according to the embodiment.
  • FIG. 8 is a schematic cross-sectional view showing a configuration of a conventional semiconductor device.
  • FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device 1 according to the embodiment.
  • the semiconductor device 1 includes a film substrate 8.
  • the film substrate 8 has holes 12.
  • a wiring pattern 11 is formed on the surface of the film substrate 8! /.
  • the semiconductor device 1 is provided with an interposer substrate 2! /.
  • a plurality of protruding electrodes (bumps) 10 made of gold are provided at positions facing the wiring pattern 11 on the surface of the interposer substrate 2 on the film substrate 8 side.
  • the interposer substrate 2 is mounted on the film substrate 8 having the wiring pattern 11 via the protruding electrodes 10! /.
  • a plurality of substrate protruding electrodes (bumps) 4 made of gold are provided.
  • a semiconductor element 3 for driving the liquid crystal is provided in the hole 12 of the film substrate 8.
  • a plurality of element protrusion electrodes (bumps) 5 made of gold are provided at positions facing the substrate protrusion electrodes 4 on the surface of the semiconductor element 3 on the interposer substrate 2 side.
  • the semiconductor element 3 is mounted on the interposer substrate 2 via the element protruding electrode 5 and the substrate protruding electrode 4.
  • a sealing resin 9 is sealed between the semiconductor element 3 and the film substrate 8 and between the interposer substrate 2, the film substrate 8, and the semiconductor element 3.
  • FIG. 2 is a schematic cross-sectional view showing a dimensional relationship between the substrate bonding surface 6 of the substrate protruding electrode 4 and the element bonding surface 7 of the element protruding electrode 5 according to the embodiment.
  • the substrate bonding surface 6 has a rectangular shape.
  • the element bonding surface 7 has a rectangular shape larger than the substrate bonding surface 6 and is disposed so as to surround the substrate bonding surface 6.
  • the major axes of the element bonding surface 7 and the substrate bonding surface 6 coincide with each other.
  • the width W2 in the minor axis direction of the element bonding surface 7 is wider than the width W1 in the minor axis direction of the substrate bonding surface 6.
  • the length L2 in the major axis direction of the element bonding surface 7 is longer than the length L1 in the major axis direction of the substrate bonding surface 6.
  • the edge of the substrate bonding surface 6 along the long axis direction is separated from the edge of the element bonding surface 7 along the long axis direction by a distance D1.
  • the edge of the substrate bonding surface 6 along the minor axis direction is separated from the edge of the element bonding surface 7 along the minor axis direction by a distance D2.
  • the length L2 of the element bonding surface 7 is, for example, 75 m, and the width W2 is, for example, 45 ⁇ m.
  • the length L1 of the substrate bonding surface 6 is 60 ⁇ m, for example.
  • the width Wl is, for example, 30 m. Therefore, the distance D1 and the distance D2 are 7. ⁇ ⁇ .
  • the substrate protruding electrode 4 has a higher hardness than the element protruding electrode 5.
  • the hardness of the protruding electrode can be adjusted by the presence or absence of annealing. Bonding quality can be improved by the hard and thin substrate protruding electrode 4 biting into the soft and low element protruding electrode 5.
  • the surface roughness of the element protrusion electrode 5 and the surface roughness of the substrate protrusion electrode 4 may be different from each other by 0.5 am or more. It is possible to increase the contact area by increasing the unevenness of the contact surface and increase the bonding quality by increasing the bonding strength.
  • the surface roughness of the protruding electrode can be adjusted by changing the measuring conditions such as the time of immersion in the etching solution.
  • bumps for confirming the collapsed state of the bumps may be provided at the corners of the chip. It can be determined from the image taken by the infrared microscope that the bumps spread out, and the bumps collide with each other and are compressed together! /. Based on this judgment, the fine adjustment can be made! Since it becomes possible, the joining quality can be improved.
  • the shape of the substrate protruding electrode 4 and the element protruding electrode 5 viewed from the direction perpendicular to the interposer substrate 3 may be a square.
  • the force required to make the bumps a vertically long rectangle to secure the bonding area with the lead.
  • the bump must be connected to the lead if it is connected to the metal wiring. Therefore, it can be made square to make the joining state uniform and to improve the joining quality.
  • the bump size of the substrate protrusion electrode 4 and the bump size of the element protrusion electrode 5 are different from each other, and the bump size of the element protrusion electrode 5 is larger than the bump size of the substrate protrusion electrode 4. . For this reason, it is possible to suppress the variation in the bonding load caused by the bonding position deviation caused by the bump formation position deviation, the startup position deviation, and the equipment capability.
  • FIG. 3 is a schematic cross-sectional view showing a dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment.
  • the bump height HI of the substrate protruding electrode 4 is, for example, 15 111
  • the element protruding electrode 5 bump height H2 is, for example, 8 m.
  • the bump height of the element protrusion electrode 5 and the bump height of the substrate protrusion electrode 4 are different from each other, and the bump height of the element protrusion electrode 5 is lower than the bump height of the substrate protrusion electrode 4. ing.
  • Element protruding electrode 5 The bump height H2 may be as low as 5 m, for example.
  • the amount of Au used can be reduced and the cost can be reduced. Further, when the bump height of the element protruding electrode 5 is lowered, the height variation of the element protruding electrode 5 is reduced, so that the bonding quality is stabilized.
  • the bump height HI of the substrate protruding electrode 4 may be as low as 10 inches, for example. Lowering the substrate protrusion electrode 4 can reduce the amount of Au used and can reduce costs. Further, since the height variation is reduced, the bonding quality is stabilized.
  • the bonding quality between the element protrusion electrode 5 and the substrate protrusion electrode 4 is stable. To do.
  • the element projecting electrode 5 and the substrate projecting electrode 4 having different sizes are converted to approximately 80% in terms of the bonding area in all the bumps.
  • the remaining 20% of bumps are the same size. It should be noted that all bumps may be configured so that the bump sizes are different!
  • redundant bumps may be provided.
  • the quality of the device can be improved by stabilizing the device characteristics.
  • the substrate protruding electrode 4 may be bonded to a terminal formed of aluminum on the semiconductor element 3 without providing the element protruding electrode 5. Bonding quality can be stabilized by general Al-Au bonding such as wire bonding.
  • FIG. 4 is a schematic cross-sectional view showing another dimensional relationship between the substrate bonding surface 6 of the substrate protruding electrode 4 and the element bonding surface 7 of the element protruding electrode 5 according to the embodiment.
  • the length in the major axis direction of the element bonding surface 7 and the length in the major axis direction of the substrate bonding surface 6 may be equal to each other.
  • Side wall force along the major axis direction of the substrate projection electrode 4 The strength of the junction protrudes from the element bonding surface 7 of the element projection electrode 5 and increases the bonding strength, but when configured as shown in FIG.
  • the side wall of the electrode 4 is longer than the configuration shown in FIG. 2 and is joined so as to fit together, so that the joining strength is increased and the joining quality is improved.
  • FIG. 5 shows the substrate bonding surface 6 of the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment.
  • 7 is a schematic cross-sectional view showing still another dimensional relationship with the child bonding surface 7.
  • the length of the substrate bonding surface 6 in the long axis direction may be longer than the length of the element bonding surface 7 in the long axis direction.
  • FIG. 6 is a schematic cross-sectional view showing another dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. While the shape and size of the substrate bonding surface 6 and the element bonding surface 7 are the same, the height of the substrate protruding electrode 4 and the height of the element protruding electrode 5 may be different. The height of the substrate protruding electrode 4 that is lower than the substrate protruding electrode 4 is 15 m, for example, and the height of the element protruding electrode 5 is 8 m, for example. The height of the element protruding electrode 5 may be as low as 5 m, for example.
  • the element protruding electrode 5 is configured to be low, and therefore it is possible to reduce the amount of Au used and reduce the cost. Further, since the element protruding electrode 5 is lowered, the height variation is reduced, and the bonding quality can be stabilized.
  • FIG. 7 is a schematic cross-sectional view showing still another dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. If the substrate bonding surface 6 and the element bonding surface 7 have the same shape and size, when bonding displacement occurs, one end of the substrate protruding electrode 4 protrudes from one end of the element protruding electrode 5, With the end protruding from the other end of the substrate protruding electrode 4, pressure bonding is performed.
  • One end of the substrate protruding electrode 4 protruding from one end of the element protruding electrode 5 and the other end of the element protruding electrode 5 protruding from the other end of the substrate protruding electrode 4 are not crimped, but the element protruding electrode 5
  • One end of the substrate protruding electrode 4 protruding from one end of the substrate does not contact the surface of the semiconductor element 3 on the interposer substrate 2 side, and the other end of the element protruding electrode 5 protruding from the other end of the substrate protruding electrode 4 is
  • the interposer substrate 2 is configured not to contact the surface of the semiconductor element 3 side. For this reason, it is possible to avoid quality degradation caused by bumps contacting the surface of the chip.
  • the interposer substrate 2 When viewed from the side or the semiconductor element 3 side, the area of the element protruding electrode 4 is larger than the area of the substrate protruding electrode 5. Further, for example, in a side view of the semiconductor device shown in FIG. 1 in which the lateral force is also viewed, the length (LI, L2) is longer than the length (Wl, W2) of the substrate bonding surface of the substrate protruding electrode 4. Similarly, in side view, the length of the element bonding surface of the element protruding electrode 5 is longer than the length of the substrate bonding surface of the substrate protruding electrode 4 in the lateral direction of FIGS. .
  • the planar shape of the protruding electrode is a square shape, but may be an elliptical shape or a round shape.
  • the present invention can be applied to a semiconductor device including an interposer substrate that is mounted on a film substrate and made of silicon, and a semiconductor element that is mounted on the interposer substrate to drive a liquid crystal. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device (1) in which the quality of the joint between a semiconductor element and the interposer substrate is stabilized comprises the interposer substrate (2) mounted on a film substrate (8) and made of silicon, and a semiconductor element (3) mounted in the interposer substrate (2) so as to drive a liquid crystal. The interposer substrate (2) has a substrate projecting electrode (4) formed on the semiconductor element (3) side. The semiconductor element (3) has an element projecting electrode (5) jointed to the substrate projecting electrode (4). The element-joined area of the element projecting electrode (5) is larger than the substrate-joined area of the substrate projecting electrode (4).

Description

明 細 書  Specification
半導体装置  Semiconductor device
技術分野  Technical field
[0001] 本発明は、半導体装置に関し、例えば、フィルム基板に実装されてシリコンにより構 成されたインタポーザ基板と、液晶を駆動するためにインタポーザ基板に実装された 半導体素子とを備えた SOF (System On Film)に好適な半導体装置に関する。 背景技術  TECHNICAL FIELD [0001] The present invention relates to a semiconductor device, for example, an SOF (System equipped with an interposer substrate that is mounted on a film substrate and made of silicon, and a semiconductor element that is mounted on the interposer substrate to drive liquid crystal. The present invention relates to a semiconductor device suitable for On Film. Background art
[0002] 集積回路 (IC)に組み込まれるトランジスタの数は年々多くなつており、内部に構成 される回路数も多くなつている。液晶パネルは近年高精細化が進み、表示画素が増 加する分、駆動回路も増加する。増加した駆動回路を補うためには、液晶パネルに 実装される液晶ドライバの数を増加させる力、、 1つの液晶ドライバに搭載される駆動 回路を増加させる必要がある。近年では液晶パネルに実装される液晶ドライバの数 が増加しないように後者の液晶ドライバの駆動回路を増加で対応することが多い。  [0002] The number of transistors incorporated in integrated circuits (ICs) is increasing year by year, and the number of circuits configured inside is also increasing. In recent years, liquid crystal panels have become higher in definition, and the number of drive circuits increases as the number of display pixels increases. To compensate for the increased drive circuit, it is necessary to increase the number of liquid crystal drivers mounted on the liquid crystal panel and the drive circuit mounted on one liquid crystal driver. In recent years, in order to prevent the number of liquid crystal drivers mounted on the liquid crystal panel from increasing, the drive circuit for the latter liquid crystal driver is often increased.
[0003] 集積回路チップは、チップサイズが小さいほど量産効率がよぐチップの原価は安く なる。そのため、多出力のドライバでは、チップサイズ縮小のためにパッドをファインピ ツチ化することが必要となる。また、集積回路チップのパッドのファインピッチ化に伴 い、ドライバのパッケージであるフィルムのインナーリード（液晶ドライバとフィルムをつ なぐ配線）のピッチもファインピッチ化する必要がある。ファインピッチ化を実現可能に する構造として、 SOF (System On Film: COF (Chip On Film)とも呼ばれる） が知られている。  [0003] The smaller the chip size of an integrated circuit chip, the lower the cost of the chip with higher mass production efficiency. For this reason, in a multi-output driver, it is necessary to make the pads fine pitch in order to reduce the chip size. In addition, as the pitch of integrated circuit chip pads becomes finer, the pitch of the inner leads (wiring that connects the liquid crystal driver and film) of the film that is the driver package also needs to be made finer. SOF (System On Film: also called COF (Chip On Film)) is known as a structure that enables fine pitch.
[0004] 図 8は、従来の半導体装置 91の構成を示す模式断面図である。半導体装置 91は 、フィルム基板 98を備えている。フィルム基板 98は、孔 82を有している。フィルム基 板 98の表面には、配線パターン 81が形成されている。  FIG. 8 is a schematic cross-sectional view showing a configuration of a conventional semiconductor device 91. The semiconductor device 91 includes a film substrate 98. The film substrate 98 has a hole 82. A wiring pattern 81 is formed on the surface of the film substrate 98.
[0005] 半導体装置 91には、インタポーザ基板 92が設けられている。インタポーザ基板 92 のフィルム基板 98側の表面の配線パターン 81に対向する位置には、金によって構 成された複数個の突起電極 90が設けられている。インタポーザ基板 92は、突起電極 90を介して配線パターン 81を有するフィルム基板 98に実装されて!/、る。 [0006] インタポーザ基板 92のフィルム基板 98側の表面の孔 82に対向する位置には、金 によって構成された複数個の基板突起電極 94が設けられている。 The semiconductor device 91 is provided with an interposer substrate 92. A plurality of protruding electrodes 90 made of gold are provided at positions facing the wiring pattern 81 on the surface of the interposer substrate 92 on the film substrate 98 side. The interposer substrate 92 is mounted on the film substrate 98 having the wiring pattern 81 via the protruding electrodes 90! /. A plurality of substrate protruding electrodes 94 made of gold are provided at positions facing the holes 82 on the surface of the interposer substrate 92 on the film substrate 98 side.
[0007] フイノレム基板 98の孔 82の中には、半導体素子 93が設けられている。半導体素子 9 3のインタポーザ基板 92側の表面の各基板突起電極 94に対向する位置には、金に よって構成された複数個の素子突起電極 95が設けられて!/、る。半導体素子 93は、 素子突起電極 95及び基板突起電極 94を介してインタポーザ基板 92に実装されて いる。半導体素子 93とフィルム基板 98との間、並びに、インタポーザ基板 92とフィノレ ム基板 98及び半導体素子 93との間には、封止樹脂 99が封止されている。  A semiconductor element 93 is provided in the hole 82 of the Finolem substrate 98. A plurality of element protrusion electrodes 95 made of gold are provided at positions facing the substrate protrusion electrodes 94 on the surface of the semiconductor element 93 on the interposer substrate 92 side. The semiconductor element 93 is mounted on the interposer substrate 92 via the element protruding electrode 95 and the substrate protruding electrode 94. A sealing resin 99 is sealed between the semiconductor element 93 and the film substrate 98, and between the interposer substrate 92, the final substrate 98, and the semiconductor element 93.
特許文献 1 :特開 2004— 207566号公報（平成 16年 7月 22日公開）  Patent Document 1: Japanese Patent Application Laid-Open No. 2004-207566 (published July 22, 2004)
発明の開示  Disclosure of the invention
[0008] しかしながら、上記従来の構成では、半導体素子 93をインタポーザ基板 92に実装 する際に、素子突起電極 95と基板突起電極 94との接合位置ズレが生じ、素子突起 電極 95の接合面が、基板突起電極 94の接合面からはみ出して、接合荷重が変動 する結果、半導体素子 93とインタポーザ基板 92との接合品質が不安定になるとレ、う 問題がある。  [0008] However, in the conventional configuration described above, when the semiconductor element 93 is mounted on the interposer substrate 92, the bonding position deviation between the element protruding electrode 95 and the substrate protruding electrode 94 occurs, and the bonding surface of the element protruding electrode 95 is If the bonding quality of the semiconductor element 93 and the interposer substrate 92 becomes unstable as a result of fluctuations in the bonding load that protrude from the bonding surface of the substrate protruding electrode 94, there is a problem.
[0009] 本発明は、上記の問題点に鑑みてなされたものであり、その目的は、半導体素子と インタポーザ基板との接合品質を安定化させることができる半導体装置を実現するこ とにある。  [0009] The present invention has been made in view of the above problems, and an object thereof is to realize a semiconductor device capable of stabilizing the bonding quality between a semiconductor element and an interposer substrate.
[0010] 本発明に係る半導体装置は、上記課題を解決するために、実装基板に実装されて 半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半 導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板 突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極 を有する半導体装置において、前記素子突起電極の素子接合面の面積が、前記基 板突起電極の基板接合面の面積よりも大きいことを特徴とする。  In order to solve the above-described problem, a semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and configured by a semiconductor, and a semiconductor element that is mounted on the interposer substrate. The substrate has a substrate protruding electrode formed on the semiconductor element side, and the semiconductor element has an element protruding electrode to be bonded to the substrate protruding electrode. In the semiconductor device, the area of the element bonding surface of the element protruding electrode is The area of the substrate bonding surface of the substrate protruding electrode is larger.
[0011] また、本発明に係る他の半導体装置は、実装基板に実装されて半導体により構成 されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え 、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、 前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装 置にお!/、て、前記インタポーザ基板側又は前記半導体素子側から透視した場合に、 前記素子突起電極の面積が前記基板突起電極の面積よりも大きいことを特徴とする [0011] In addition, another semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and configured of a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate includes the semiconductor A semiconductor device having a substrate protruding electrode formed on an element side, wherein the semiconductor element has an element protruding electrode bonded to the substrate protruding electrode; The area of the element protruding electrode is larger than the area of the substrate protruding electrode when seen through from the interposer substrate side or the semiconductor element side.
[0012] また、本発明に係るさらに他の半導体装置は、実装基板に実装されて半導体により 構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを 備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有 し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導 体装置において、一側面視で、前記素子突起電極の素子接合面の長さが、前記基 板突起電極の基板接合面の長さよりも長いことを特徴とする。 [0012] Further, another semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and is configured of a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate includes: In a semiconductor device having a substrate protruding electrode formed on a semiconductor element side, and the semiconductor element having an element protruding electrode bonded to the substrate protruding electrode, the element bonding surface of the element protruding electrode in a side view Is longer than the length of the substrate bonding surface of the substrate projection electrode.
[0013] 上記の特徴によれば、基板突起電極と素子突起電極との接合位置にズレが生じて も、素子突起電極は、基板突起電極の基板接合面のうちの広い面積の面と接触する ことができ、接合荷重の変動が抑制されて、接合品質を安定化することができる。  [0013] According to the above feature, even if the bonding position between the substrate protruding electrode and the element protruding electrode is displaced, the element protruding electrode is in contact with a surface having a large area among the substrate bonding surfaces of the substrate protruding electrode. It is possible to suppress the variation of the bonding load and stabilize the bonding quality.
[0014] なお、突起電極とは、通常「バンプ」と呼ばれているもので、電極部の表面に形成さ れ、電気的に接続する対象物と接合されるものである。  Note that the protruding electrode is generally called “bump” and is formed on the surface of the electrode portion and bonded to an object to be electrically connected.
[0015] 本発明に係る半導体装置では、前記素子接合面及び前記基板接合面は、長方形 状をしており、前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに 平行に配置されており、前記素子接合面の短軸方向の幅が、前記基板接合面の短 軸方向の幅よりも広レ、ことが好まし!/、。  In the semiconductor device according to the present invention, the element bonding surface and the substrate bonding surface have a rectangular shape, and the major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other. Preferably, the width of the element bonding surface in the minor axis direction is wider than the width of the substrate bonding surface in the minor axis direction! /.
[0016] 上記構成によれば、基板接合面の短軸方向に沿った接合位置のズレに対して、好 適に接合荷重の変動を抑制し、接合品質を安定化することができる。  [0016] According to the above configuration, it is possible to favorably suppress the variation in the bonding load and stabilize the bonding quality with respect to the displacement of the bonding position along the minor axis direction of the substrate bonding surface.
[0017] 本発明に係る半導体装置では、前記素子接合面の長軸方向の長さと前記基板接 合面の長軸方向の長さとが、互いに等し!/、ことが好まし!/、。  In the semiconductor device according to the present invention, it is preferable that the length in the major axis direction of the element bonding surface and the length in the major axis direction of the substrate bonding surface are equal to each other! /.
[0018] 基板突起電極の長軸方向に沿った側壁が、素子突起電極の素子接合面に食い込 んで接合強度が増大するが、上記構成によれば、素子接合面に食い込む基板突起 電極の側壁が長くなり、嚙み合うように接合するので、接合強度が増大し、接合品質 が向上する。  [0018] Although the side wall along the major axis direction of the substrate protruding electrode bites into the element bonding surface of the element protruding electrode to increase the bonding strength, according to the above configuration, the side wall of the substrate protruding electrode bites into the element bonding surface. Since the joints are long and tightly joined, the joint strength is increased and the joint quality is improved.
[0019] 本発明に係る半導体装置では、前記基板接合面の長軸方向の長さは、前記素子 接合面の長軸方向の長さよりも長レ、ことが好ましレ、。 [0020] 上記構成によれば、基板突起電極の長軸方向に沿った側壁が、素子突起電極の 素子接合面に食い込むのみならず、素子突起電極の短軸方向に沿った側壁が、基 板突起電極の基板接合面に逆方向に食い込む。このため、基板突起電極と素子突 起電極とが、互いに嚙み合うように接合して、接合強度がより一層増大し、接合品質 がより一層向上する。 In the semiconductor device according to the present invention, it is preferable that the length of the substrate bonding surface in the long axis direction is longer than the length of the element bonding surface in the long axis direction. [0020] According to the above configuration, the side wall along the long axis direction of the substrate protruding electrode not only bites into the element bonding surface of the element protruding electrode, but also the side wall along the short axis direction of the element protruding electrode is It bites into the substrate bonding surface of the protruding electrode in the opposite direction. For this reason, the substrate protruding electrode and the element protruding electrode are bonded to each other so that the bonding strength is further increased and the bonding quality is further improved.
[0021] 本発明に係る半導体装置では、前記インタポーザ基板に垂直な方向から見て、前 記素子接合面は、前記基板接合面を囲むように配置されており、前記素子接合面及 び前記基板接合面は、長方形状をしており、前記素子接合面及び前記基板接合面 のそれぞれの長軸は、互いに平行に配置されており、前記インタポーザ基板に垂直 な方向から見て、前記素子接合面の一辺は、前記基板接合面の対応する一辺から 5 〜10 μ m離れて配置されて!/、ること力 S好ましレ、。  In the semiconductor device according to the present invention, the element bonding surface is arranged so as to surround the substrate bonding surface when viewed from a direction perpendicular to the interposer substrate, and the element bonding surface and the substrate The bonding surface has a rectangular shape, and the major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other, and the element bonding surface is viewed from a direction perpendicular to the interposer substrate. The one side is arranged 5 to 10 μm away from the corresponding one side of the substrate bonding surface! /, The force S is preferable.
[0022] 上記構成によれば、接合位置のズレがどの方向に 5〜； 10 a m生じても、接合荷重 の変動を抑制し、接合品質を安定化することができる。  [0022] According to the above configuration, even if the displacement of the joining position is 5 to 10 am in any direction, the fluctuation of the joining load can be suppressed and the joining quality can be stabilized.
[0023] 本発明に係る半導体装置では、前記素子突起電極の高さと前記基板突起電極の 高さと力 互いに異なっていることが好ましい。  In the semiconductor device according to the present invention, it is preferable that the height of the element protruding electrode and the height and force of the substrate protruding electrode are different from each other.
[0024] 上記構成によれば、素子突起電極または基板突起電極を低くすることができ、高さ のバラツキを低減して、接合品質を安定化することができる。  [0024] According to the above configuration, the element protruding electrode or the substrate protruding electrode can be lowered, the height variation can be reduced, and the bonding quality can be stabilized.
[0025] 例えばテープキャリアのように曲げ加工し易いように薄くて可撓性が高い素材をパッ ケージ基材として構成した場合、テープキャリアにインターポーザ基板を接続する際 、前記基板突起電極が低レ、とテープキャリアの配線とインターポーザ基板の端部の 間隔が充分に確保できず、テープキャリアの配線力インターポーザ基板の端部に接 触して、テープキャリアの配線導体間の短絡が生じることがある。例えば基板突起電 極を 15 mで作製し、基板突起電極とテープキャリアの配線を接続した場合にテー プキャリアの配線とインターポーザ基板の端部との間隔は 9 m程度確保できるため 、基板突起電極高さが、 10〜； 15 mであればテープキャリアの配泉とインターポー ザ基板の端部との間隔が充分に確保でき、配線同士の短絡を避けることができる。ま た、素子突起電極はそのような心配が無い為、前記基板突起電極の高さよりも低くで きる。 [0026] そのため本発明に係る半導体装置では、前記素子突起電極の高さが、前記基板 突起電極の高さよりも低!/、ことが好まし!/、。 [0025] For example, when a thin and highly flexible material such as a tape carrier that can be easily bent is configured as a package base material, the substrate protruding electrode has a low level when the interposer substrate is connected to the tape carrier. , And the gap between the tape carrier wiring and the end of the interposer board may not be sufficient, and the wiring force of the tape carrier may contact the end of the interposer board, causing a short circuit between the wiring conductors of the tape carrier. . For example, when the substrate protruding electrode is made at 15 m and the substrate protruding electrode and the tape carrier wiring are connected, the distance between the tape carrier wiring and the end of the interposer substrate can be secured about 9 m. If the height is 10 to 15 m, a sufficient distance between the tape carrier spring and the end of the interposer substrate can be secured, and a short circuit between the wirings can be avoided. Further, since the element protruding electrode does not have such a concern, it can be made lower than the height of the substrate protruding electrode. Therefore, in the semiconductor device according to the present invention, it is preferable that the height of the element protruding electrode is lower than the height of the substrate protruding electrode! /.
[0027] 上記構成によれば、素子突起電極を基板突起電極よりも低くすることができ、素子 突起電極の高さのバラツキを低減して、 Au使用量を削減し、接合品質を安定化する こと力 Sでさる。 [0027] According to the above configuration, the element protruding electrode can be made lower than the substrate protruding electrode, the variation in the height of the element protruding electrode can be reduced, the amount of Au used can be reduced, and the bonding quality can be stabilized. That's the power S.
[0028] 本発明に係る半導体装置では、前記素子突起電極の高さが、 5〜8 111であること が好ましい。  In the semiconductor device according to the present invention, it is preferable that the height of the element protruding electrode is 5 to 8111.
[0029] 上記構成によれば、素子突起電極を低くすることができ、素子突起電極の高さのバ ラツキを低減して、 Au使用量を削減してコストを低減するとともに、接合品質を安定 ィ匕すること力 Sでさる。  [0029] According to the above configuration, the element protrusion electrode can be lowered, the height variation of the element protrusion electrode can be reduced, the amount of Au used can be reduced, the cost can be reduced, and the bonding quality can be stabilized.力
[0030] 本発明に係る半導体装置では、前記基板突起電極の高さが、 10〜； 15 111である ことが好ましい。  [0030] In the semiconductor device according to the present invention, it is preferable that a height of the substrate protruding electrode is 10 to 15111.
[0031] 上記構成によれば、基板突起電極を低くして、 Au使用量削減によるコストダウンを 実現し、バンプ高さのバラツキを低減して、接合品質を安定化することができる。  [0031] According to the above configuration, it is possible to lower the substrate protruding electrode, to realize cost reduction by reducing the amount of Au used, to reduce bump height variation, and to stabilize the bonding quality.
[0032] 本発明に係る半導体装置では、前記基板突起電極は、前記素子突起電極よりも硬 度が高いことが好ましい。 In the semiconductor device according to the present invention, it is preferable that the substrate protruding electrode has higher hardness than the element protruding electrode.
[0033] 上記構成によれば、硬度が高!/、基板突起電極が、柔らか!/、素子突起電極に食!/、 込むので、接合強度が向上する。 [0033] According to the above configuration, since the hardness is high !, the substrate protruding electrode is soft! /, And the device protruding electrode bites into / out, the bonding strength is improved.
[0034] 本発明に係る他の半導体装置は、上記課題を解決するために、実装基板に実装さ れて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装され た半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された 基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する端子を有 することを特徴とする。 [0034] In order to solve the above problems, another semiconductor device according to the present invention includes an interposer substrate formed of a semiconductor mounted on a mounting substrate, and a semiconductor element mounted on the interposer substrate, The interposer substrate has a substrate protruding electrode formed on the semiconductor element side, and the semiconductor element has a terminal bonded to the substrate protruding electrode.
[0035] 上記特徴により、半導体素子側に突起電極を設けないので、 Au使用量低減による コストダウンを実現することができる。  [0035] Due to the above feature, since no protruding electrode is provided on the semiconductor element side, it is possible to realize cost reduction by reducing the amount of Au used.
[0036] 本発明に係る半導体装置では、前記端子は、アルミニウムによって構成され、前記 基板突起電極は、金によって構成されることが好ましレ、。 [0036] In the semiconductor device according to the present invention, it is preferable that the terminal is made of aluminum and the substrate protruding electrode is made of gold.
[0037] 上記構成によれば、ワイヤーボンド等の一般的な A1— Au接合により、接合品質の 安定化を図ることができる。 [0037] According to the above configuration, the bonding quality is improved by general A1-Au bonding such as wire bonding. Stabilization can be achieved.
[0038] 本発明に係るさらに他の半導体装置は、実装基板に実装されて半導体により構成 されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え 、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、 前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装 置において、前記素子突起電極の高さと前記基板突起電極の高さとが、互いに異な つていることを特徴とする。 [0038] Still another semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and configured by a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate includes the semiconductor element. A semiconductor device having an element protruding electrode bonded to the substrate protruding electrode, wherein the height of the element protruding electrode and the height of the substrate protruding electrode are: It is characterized by being different from each other.
[0039] 上記特徴により、素子突起電極を、基板突起電極よりも低く構成することができ、素 子突起電極の高さのバラツキを低減して、 Au使用量を削減し、接合品質を安定化す ること力 Sでさる。 [0039] Due to the above features, the element protrusion electrode can be configured to be lower than the substrate protrusion electrode, the variation in the height of the element protrusion electrode can be reduced, the amount of Au used can be reduced, and the bonding quality can be stabilized. The power S
[0040] 本発明に係るさらに他の半導体装置は、実装基板に実装されて半導体により構成 されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え 、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、 前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装 置にお!/、て、前記素子突起電極の素子接合面及び前記基板突起電極の基板接合 面は、長方形状をしており、前記素子接合面及び前記基板接合面のそれぞれの長 軸は、互いに平行に配置されており、前記素子接合面の短軸方向の幅が、前記基板 接合面の短軸方向の幅よりも広ぐ前記基板接合面の長軸方向の長さは、前記素子 接合面の長軸方向の長さよりも長いことを特徴とする。  [0040] Still another semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and configured of a semiconductor, and a semiconductor element that is mounted on the interposer substrate. The interposer substrate includes the semiconductor element. The semiconductor element has a substrate protruding electrode formed on a side, and the semiconductor element has a device protruding electrode bonded to the substrate protruding electrode. The substrate bonding surface of the protruding electrode has a rectangular shape, the major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other, and the width of the element bonding surface in the minor axis direction is The major axis direction length of the substrate bonding surface, which is wider than the minor axis width of the substrate bonding surface, is longer than the major axis length of the element bonding surface.
[0041] 上記特徴により、基板突起電極の長軸方向に沿った側壁が、素子突起電極の素子 接合面に食い込むのみならず、素子突起電極の短軸方向に沿った側壁が、基板突 起電極の基板接合面に逆方向に食い込む。このため、基板突起電極と素子突起電 極とが、互いに嚙み合うように接合して、接合強度がより一層増大し、接合品質がより 一層向上する。 [0041] Due to the above feature, the side wall along the long axis direction of the substrate protruding electrode does not only bite into the element bonding surface of the element protruding electrode, but the side wall along the short axis direction of the element protruding electrode causes the substrate protruding electrode to Bite in the opposite direction to the substrate bonding surface. For this reason, the substrate protruding electrode and the element protruding electrode are bonded so as to be held together, the bonding strength is further increased, and the bonding quality is further improved.
[0042] 本発明に係る半導体装置は、以上のように、基板突起電極と素子突起電極との接 合位置にズレが生じても、素子突起電極は、基板突起電極の基板接合面のうちの広 い面積の面と接触することができ、接合荷重の変動が抑制されて、接合品質を安定 化すること力 Sできると!/、う効果を奏する。 図面の簡単な説明 [0042] As described above, the semiconductor device according to the present invention is configured such that, even when a displacement occurs in the contact position between the substrate protruding electrode and the element protruding electrode, the element protruding electrode is out of the substrate bonding surface of the substrate protruding electrode. It is possible to contact a surface with a large area, and fluctuations in the bonding load can be suppressed to stabilize the bonding quality. Brief Description of Drawings
[図 1]実施の形態に係る半導体装置の構成を示す模式断面図である。 FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment.
[図 2]実施の形態に係る基板突起電極の基板接合面と素子突起電極の素子接合面 との寸法関係を示す模式断面図である。  FIG. 2 is a schematic cross-sectional view showing the dimensional relationship between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment.
[図 3]実施の形態に係る基板突起電極と素子突起電極との寸法関係を示す模式断 面図である。  FIG. 3 is a schematic cross-sectional view showing a dimensional relationship between a substrate protruding electrode and an element protruding electrode according to the embodiment.
[図 4]実施の形態に係る基板突起電極の基板接合面と素子突起電極の素子接合面 との他の寸法関係を示す模式断面図である。  FIG. 4 is a schematic cross-sectional view showing another dimensional relationship between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment.
[図 5]実施の形態に係る基板突起電極の基板接合面と素子突起電極の素子接合面 とのさらに他の寸法関係を示す模式断面図である。  FIG. 5 is a schematic cross-sectional view showing still another dimensional relationship between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment.
[図 6]実施の形態に係る基板突起電極と素子突起電極との他の寸法関係を示す模 式断面図である。  FIG. 6 is a schematic cross-sectional view showing another dimensional relationship between the substrate protruding electrode and the element protruding electrode according to the embodiment.
[図 7]実施の形態に係る基板突起電極と素子突起電極とのさらに他の寸法関係を示 す模式断面図である。  FIG. 7 is a schematic cross-sectional view showing still another dimensional relationship between the substrate protruding electrode and the element protruding electrode according to the embodiment.
[図 8]従来の半導体装置の構成を示す模式断面図である。  FIG. 8 is a schematic cross-sectional view showing a configuration of a conventional semiconductor device.
符号の説明 Explanation of symbols
1 半導体装置  1 Semiconductor devices
2 インターポーザ基板  2 Interposer board
3 半導体素子  3 Semiconductor elements
4 基板突起電極  4 Substrate protruding electrode
5 素子突起電極  5 Element protruding electrode
6 基板接合面  6 Board interface
7 素子接合面  7 Element interface
8 フィルム基板  8 Film substrate
9 封止樹脂  9 Sealing resin
10 突起電極  10 Projection electrode
11 配線パターン  11 Wiring pattern
12 孔 発明を実施するための最良の形態 12 holes BEST MODE FOR CARRYING OUT THE INVENTION
[0045] 本発明の一実施形態について図 1ないし図 7に基づいて説明すると以下の通りで ある。図 1は、実施の形態に係る半導体装置 1の構成を示す模式断面図である。半 導体装置 1は、フィルム基板 8を備えている。フィルム基板 8は、孔 12を有している。フ イルム基板 8の表面には、配線パターン 11が形成されて!/、る。  One embodiment of the present invention is described below with reference to FIGS. 1 to 7. FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device 1 according to the embodiment. The semiconductor device 1 includes a film substrate 8. The film substrate 8 has holes 12. A wiring pattern 11 is formed on the surface of the film substrate 8! /.
[0046] 半導体装置 1には、インタポーザ基板 2が設けられて!/、る。インタポーザ基板 2のフ イルム基板 8側の表面の配線パターン 11に対向する位置には、金によって構成され た複数個の突起電極 (バンプ） 10が設けられている。インタポーザ基板 2は、突起電 極 10を介して配線パターン 11を有するフィルム基板 8に実装されて!/、る。  The semiconductor device 1 is provided with an interposer substrate 2! /. A plurality of protruding electrodes (bumps) 10 made of gold are provided at positions facing the wiring pattern 11 on the surface of the interposer substrate 2 on the film substrate 8 side. The interposer substrate 2 is mounted on the film substrate 8 having the wiring pattern 11 via the protruding electrodes 10! /.
[0047] インタポーザ基板 2のフィルム基板 8側の表面の孔 2に対向する位置には、金によつ て構成された複数個の基板突起電極 (バンプ) 4が設けられて!/、る。  [0047] At a position facing the hole 2 on the surface of the interposer substrate 2 on the film substrate 8 side, a plurality of substrate protruding electrodes (bumps) 4 made of gold are provided.
[0048] フィルム基板 8の孔 12の中には、液晶を駆動するための半導体素子 3が設けられて いる。半導体素子 3のインタポーザ基板 2側の表面の各基板突起電極 4に対向する 位置には、金によって構成された複数個の素子突起電極 (バンプ） 5が設けられてい る。半導体素子 3は、素子突起電極 5及び基板突起電極 4を介してインタポーザ基板 2に実装されている。半導体素子 3とフィルム基板 8との間、並びに、インタポーザ基 板 2とフィルム基板 8及び半導体素子 3との間には、封止樹脂 9が封止されている。  [0048] In the hole 12 of the film substrate 8, a semiconductor element 3 for driving the liquid crystal is provided. A plurality of element protrusion electrodes (bumps) 5 made of gold are provided at positions facing the substrate protrusion electrodes 4 on the surface of the semiconductor element 3 on the interposer substrate 2 side. The semiconductor element 3 is mounted on the interposer substrate 2 via the element protruding electrode 5 and the substrate protruding electrode 4. A sealing resin 9 is sealed between the semiconductor element 3 and the film substrate 8 and between the interposer substrate 2, the film substrate 8, and the semiconductor element 3.
[0049] 図 2は、実施の形態に係る基板突起電極 4の基板接合面 6と素子突起電極 5の素 子接合面 7との寸法関係を示す模式断面図であり、図 1に示す断面 AAに沿った模 式断面図である。基板接合面 6は、長方形状をしている。素子接合面 7は、基板接合 面 6よりも大きな長方形状をしており、基板接合面 6を囲むように配置されている。素 子接合面 7及び基板接合面 6のそれぞれの長軸は、一致している。素子接合面 7の 短軸方向の幅 W2は、基板接合面 6の短軸方向の幅 W1よりも広い。素子接合面 7の 長軸方向の長さ L2は、基板接合面 6の長軸方向の長さ L1よりも長い。基板接合面 6 の長軸方向に沿った縁辺は、素子接合面 7の長軸方向に沿った縁辺から距離 D1だ け離れている。基板接合面 6の短軸方向に沿った縁辺は、素子接合面 7の短軸方向 に沿った縁辺から距離 D2だけ離れている。素子接合面 7の長さ L2は、例えば 75 mであり、幅 W2は、例えば 45 μ mである。基板接合面 6の長さ L1は、例えば 60 μ m であり、幅 Wlは、例えば 30 mである。従って、距離 D 1及び距離 D2は、 7. δ μ ΐη である。 FIG. 2 is a schematic cross-sectional view showing a dimensional relationship between the substrate bonding surface 6 of the substrate protruding electrode 4 and the element bonding surface 7 of the element protruding electrode 5 according to the embodiment. FIG. The substrate bonding surface 6 has a rectangular shape. The element bonding surface 7 has a rectangular shape larger than the substrate bonding surface 6 and is disposed so as to surround the substrate bonding surface 6. The major axes of the element bonding surface 7 and the substrate bonding surface 6 coincide with each other. The width W2 in the minor axis direction of the element bonding surface 7 is wider than the width W1 in the minor axis direction of the substrate bonding surface 6. The length L2 in the major axis direction of the element bonding surface 7 is longer than the length L1 in the major axis direction of the substrate bonding surface 6. The edge of the substrate bonding surface 6 along the long axis direction is separated from the edge of the element bonding surface 7 along the long axis direction by a distance D1. The edge of the substrate bonding surface 6 along the minor axis direction is separated from the edge of the element bonding surface 7 along the minor axis direction by a distance D2. The length L2 of the element bonding surface 7 is, for example, 75 m, and the width W2 is, for example, 45 μm. The length L1 of the substrate bonding surface 6 is 60 μm, for example. The width Wl is, for example, 30 m. Therefore, the distance D1 and the distance D2 are 7.δμ μη.
[0050] 基板突起電極 4は、素子突起電極 5よりも硬度が高くなつている。突起電極の硬度 は、ァニールの有無によって調整することができる。硬くて細い基板突起電極 4が、 柔らかくて低い素子突起電極 5に食い込むことにより、接合品質を向上させることが できる。  The substrate protruding electrode 4 has a higher hardness than the element protruding electrode 5. The hardness of the protruding electrode can be adjusted by the presence or absence of annealing. Bonding quality can be improved by the hard and thin substrate protruding electrode 4 biting into the soft and low element protruding electrode 5.
[0051] また、素子突起電極 5の表面粗度と、基板突起電極 4の表面粗度とを 0. 5 a m以上 異ならせてもよい。接触面の凹凸を大きくして接触面積を増大させ、接合強度を大き くして接合品質を増大させること力 Sできる。突起電極の表面粗度は、エッチング液に 浸す時間等のメツキ条件を変更することによって調整することができる。  [0051] Further, the surface roughness of the element protrusion electrode 5 and the surface roughness of the substrate protrusion electrode 4 may be different from each other by 0.5 am or more. It is possible to increase the contact area by increasing the unevenness of the contact surface and increase the bonding quality by increasing the bonding strength. The surface roughness of the protruding electrode can be adjusted by changing the measuring conditions such as the time of immersion in the etching solution.
[0052] また、バンプ潰れ状態を確認するためのバンプを、チップのコーナ部に設けてもよ い。赤外線顕微鏡による画像により、バンプが広がっているほど、バンプ同士がぶつ 力、り合って圧縮されて!/、ると判断することができ、この判断に基づ!/、て微調整すること が可能になるので、接合品質を向上させることができる。  [0052] Further, bumps for confirming the collapsed state of the bumps may be provided at the corners of the chip. It can be determined from the image taken by the infrared microscope that the bumps spread out, and the bumps collide with each other and are compressed together! /. Based on this judgment, the fine adjustment can be made! Since it becomes possible, the joining quality can be improved.
[0053] また、基板突起電極 4及び素子突起電極 5のインタポーザ基板 3に垂直な方向から 見た形状は、正方形であってもよい。従来の SOFでは、リードとの接合面積を確保す るためにバンプを縦長の長方形にする必要があった力 本実施の形態では、バンプ はメタル配線と接続すればよぐリードと接合する必要がなくなるため、正方形にして 、接合状態を均一にし、接合品質を高めることができる。  [0053] The shape of the substrate protruding electrode 4 and the element protruding electrode 5 viewed from the direction perpendicular to the interposer substrate 3 may be a square. In conventional SOF, the force required to make the bumps a vertically long rectangle to secure the bonding area with the lead. In this embodiment, the bump must be connected to the lead if it is connected to the metal wiring. Therefore, it can be made square to make the joining state uniform and to improve the joining quality.
[0054] このように、基板突起電極 4のバンプサイズと、素子突起電極 5のバンプサイズとは 、互いに異なっており、素子突起電極 5のバンプサイズは、基板突起電極 4のバンプ サイズよりも大きい。このため、バンプ形成位置ズレ、立ち上げ位置ズレ、及び設備能 力に起因する接合位置ズレによって生じる接合荷重の変動を抑制することができる。  As described above, the bump size of the substrate protrusion electrode 4 and the bump size of the element protrusion electrode 5 are different from each other, and the bump size of the element protrusion electrode 5 is larger than the bump size of the substrate protrusion electrode 4. . For this reason, it is possible to suppress the variation in the bonding load caused by the bonding position deviation caused by the bump formation position deviation, the startup position deviation, and the equipment capability.
[0055] 図 3は、実施の形態に係る基板突起電極 4と素子突起電極 5との寸法関係を示す 模式断面図である。基板突起電極 4のバンプ高さ HIは、例えば 15 111であり、素子 突起電極 5バンプ高さ H2は、例えば 8 mである。このように、素子突起電極 5のバ ンプ高さと、基板突起電極 4のバンプ高さとは、互いに異なっており、素子突起電極 5 のバンプ高さは、基板突起電極 4のバンプ高さよりも低くなつている。素子突起電極 5 のバンプ高さ H2は、例えば 5 mに低くしてもよい。 FIG. 3 is a schematic cross-sectional view showing a dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. The bump height HI of the substrate protruding electrode 4 is, for example, 15 111, and the element protruding electrode 5 bump height H2 is, for example, 8 m. Thus, the bump height of the element protrusion electrode 5 and the bump height of the substrate protrusion electrode 4 are different from each other, and the bump height of the element protrusion electrode 5 is lower than the bump height of the substrate protrusion electrode 4. ing. Element protruding electrode 5 The bump height H2 may be as low as 5 m, for example.
[0056] このように、素子突起電極 5のバンプ高さを低くすると、 Auの使用量を削減すること ができ、コストを低減すること力 Sできる。また、素子突起電極 5のバンプ高さを低くする と、素子突起電極 5の高さバラツキが低減するので、接合品質が安定する。 As described above, when the bump height of the element protruding electrode 5 is lowered, the amount of Au used can be reduced and the cost can be reduced. Further, when the bump height of the element protruding electrode 5 is lowered, the height variation of the element protruding electrode 5 is reduced, so that the bonding quality is stabilized.
[0057] 基板突起電極 4のバンプ高さ HIは、例えば 10 inに低くしてもよい。基板突起電 極 4を低くすると、 Auの使用量を削減することができ、コストを低減すること力 Sできる。 また、高さバラツキが低減するので、接合品質が安定する。 [0057] The bump height HI of the substrate protruding electrode 4 may be as low as 10 inches, for example. Lowering the substrate protrusion electrode 4 can reduce the amount of Au used and can reduce costs. Further, since the height variation is reduced, the bonding quality is stabilized.
[0058] 以上のように、大きくて低いバンプである素子突起電極 5を、細くて高いバンプであ る基板突起電極 4に接合すると、素子突起電極 5と基板突起電極 4との接合品質が 安定する。 As described above, when the element protrusion electrode 5 which is a large and low bump is bonded to the substrate protrusion electrode 4 which is a thin and high bump, the bonding quality between the element protrusion electrode 5 and the substrate protrusion electrode 4 is stable. To do.
[0059] サイズの異なる素子突起電極 5と基板突起電極 4とは、全バンプ中、接合面積で換 算して、 80%程度にする。残りの 20%のバンプは、サイズを等しくしている。なお、全 てのバンプにお!/、て、上下バンプサイズが異なるように構成してもよ!/、。  [0059] The element projecting electrode 5 and the substrate projecting electrode 4 having different sizes are converted to approximately 80% in terms of the bonding area in all the bumps. The remaining 20% of bumps are the same size. It should be noted that all bumps may be configured so that the bump sizes are different!
[0060] また、半導体素子 3の入力端子に接続して設けられる入力バンプ、及び出力端子 に接続して設けられる出力バンプ以外に、冗長バンプを設けてもよい。また、入カバ ンプにおいて、電源系及び GND系のバンプを冗長的に複数個設けると、デバイス特 性の安定化により高品質化を図ることができる。  In addition to the input bumps connected to the input terminals of the semiconductor element 3 and the output bumps connected to the output terminals, redundant bumps may be provided. In addition, if the power supply system and GND system bumps are redundantly provided in the input bump, the quality of the device can be improved by stabilizing the device characteristics.
[0061] また、素子突起電極 5を設けず、半導体素子 3にアルミニウムによって形成された端 子に基板突起電極 4を接合するように構成してもよい。ワイヤーボンド等の一般的な Al—Au接合により、接合品質を安定化することができる。  [0061] Alternatively, the substrate protruding electrode 4 may be bonded to a terminal formed of aluminum on the semiconductor element 3 without providing the element protruding electrode 5. Bonding quality can be stabilized by general Al-Au bonding such as wire bonding.
[0062] 図 4は、実施の形態に係る基板突起電極 4の基板接合面 6と素子突起電極 5の素 子接合面 7との他の寸法関係を示す模式断面図である。素子接合面 7の長軸方向の 長さと基板接合面 6の長軸方向の長さとは、互いに等しくてもよい。基板突起電極 4 の長軸方向に沿った側壁力 素子突起電極 5の素子接合面 7に食い込んで接合強 度が増大するが、図 4に示すように構成すると、素子接合面 7に食い込む基板突起電 極 4の側壁が、図 2に示す構成よりも長くなり、嚙み合うように接合するので、接合強 度が増大し、接合品質が向上する。  FIG. 4 is a schematic cross-sectional view showing another dimensional relationship between the substrate bonding surface 6 of the substrate protruding electrode 4 and the element bonding surface 7 of the element protruding electrode 5 according to the embodiment. The length in the major axis direction of the element bonding surface 7 and the length in the major axis direction of the substrate bonding surface 6 may be equal to each other. Side wall force along the major axis direction of the substrate projection electrode 4 The strength of the junction protrudes from the element bonding surface 7 of the element projection electrode 5 and increases the bonding strength, but when configured as shown in FIG. The side wall of the electrode 4 is longer than the configuration shown in FIG. 2 and is joined so as to fit together, so that the joining strength is increased and the joining quality is improved.
[0063] 図 5は、実施の形態に係る基板突起電極 4の基板接合面 6と素子突起電極 5の素 子接合面 7とのさらに他の寸法関係を示す模式断面図である。基板接合面 6の長軸 方向の長さは、素子接合面 7の長軸方向の長さよりも長く構成してもよい。このように 構成すると、基板突起電極 4の長軸方向に沿った側壁が、素子突起電極 5の素子接 合面 7に食い込むのみならず、素子突起電極 5の短軸方向に沿った側壁が、基板突 起電極 4の基板接合面 6に逆方向に食い込む。このため、基板突起電極 4と素子突 起電極 5とが、互いに嚙み合うように接合して、接合強度がより一層増大し、接合品 質がより一層向上する。 FIG. 5 shows the substrate bonding surface 6 of the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. 7 is a schematic cross-sectional view showing still another dimensional relationship with the child bonding surface 7. FIG. The length of the substrate bonding surface 6 in the long axis direction may be longer than the length of the element bonding surface 7 in the long axis direction. With this configuration, the side wall along the long axis direction of the substrate protruding electrode 4 not only bites into the element contact surface 7 of the element protruding electrode 5, but also the side wall along the short axis direction of the element protruding electrode 5 It bites into the substrate bonding surface 6 of the substrate protruding electrode 4 in the opposite direction. For this reason, the substrate protruding electrode 4 and the element protruding electrode 5 are bonded together so as to sandwich each other, the bonding strength is further increased, and the bonding quality is further improved.
[0064] 図 6は、実施の形態に係る基板突起電極 4と素子突起電極 5との他の寸法関係を 示す模式断面図である。基板接合面 6と素子接合面 7との形状及びサイズとは、同一 にしながら、基板突起電極 4の高さと、素子突起電極 5の高さとを異ならせてもよい。 素子突起電極 5は基板突起電極 4よりも低ぐ基板突起電極 4の高さは、例えば 15 mであり、素子突起電極 5の高さは、例えば 8 mである。素子突起電極 5の高さは、 例えば 5 mに低くしてもよい。  FIG. 6 is a schematic cross-sectional view showing another dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. While the shape and size of the substrate bonding surface 6 and the element bonding surface 7 are the same, the height of the substrate protruding electrode 4 and the height of the element protruding electrode 5 may be different. The height of the substrate protruding electrode 4 that is lower than the substrate protruding electrode 4 is 15 m, for example, and the height of the element protruding electrode 5 is 8 m, for example. The height of the element protruding electrode 5 may be as low as 5 m, for example.
[0065] このように構成すると、素子突起電極 5を低く構成するので、 Auの使用量を削減し てコストを低減すること力 Sできる。また、素子突起電極 5が低くなるので、高さバラツキ が低減し、接合品質を安定化することができる。  [0065] With this configuration, the element protruding electrode 5 is configured to be low, and therefore it is possible to reduce the amount of Au used and reduce the cost. Further, since the element protruding electrode 5 is lowered, the height variation is reduced, and the bonding quality can be stabilized.
[0066] 図 7は、実施の形態に係る基板突起電極 4と素子突起電極 5とのさらに他の寸法関 係を示す模式断面図である。基板接合面 6と素子接合面 7とを同一の形状及びサイ ズにすると、接合ズレが発生した場合、基板突起電極 4の一端が、素子突起電極 5の 一端からはみ出し、素子突起電極 5の他端が、基板突起電極 4の他端からはみ出し た状態で、圧着接合される。素子突起電極 5の一端からはみ出した基板突起電極 4 の一端と、基板突起電極 4の他端からはみ出した素子突起電極 5の他端とは、圧着さ れないことになるが、素子突起電極 5の一端からはみ出した基板突起電極 4の一端 は、半導体素子 3のインターポーザ基板 2側の表面に接触せず、また、基板突起電 極 4の他端からはみ出した素子突起電極 5の他端は、インターポーザ基板 2の半導 体素子 3側の表面に接触しないように構成されている。このため、バンプがチップの 表面に接触することによる品質低下を回避することができる。  FIG. 7 is a schematic cross-sectional view showing still another dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. If the substrate bonding surface 6 and the element bonding surface 7 have the same shape and size, when bonding displacement occurs, one end of the substrate protruding electrode 4 protrudes from one end of the element protruding electrode 5, With the end protruding from the other end of the substrate protruding electrode 4, pressure bonding is performed. One end of the substrate protruding electrode 4 protruding from one end of the element protruding electrode 5 and the other end of the element protruding electrode 5 protruding from the other end of the substrate protruding electrode 4 are not crimped, but the element protruding electrode 5 One end of the substrate protruding electrode 4 protruding from one end of the substrate does not contact the surface of the semiconductor element 3 on the interposer substrate 2 side, and the other end of the element protruding electrode 5 protruding from the other end of the substrate protruding electrode 4 is The interposer substrate 2 is configured not to contact the surface of the semiconductor element 3 side. For this reason, it is possible to avoid quality degradation caused by bumps contacting the surface of the chip.
[0067] なお、上述した実施形態では、図 2, 4, 5からも明らかなように、インタポーザ基板 2 側又は半導体素子 3側から透視した場合に、素子突起電極 4の面積が基板突起電 極 5の面積よりも大きくなつている。また、例えば図 1に示すような半導体装置を側面 力も見た側面視において、図 2の図面上下方向と図面左右方向とのいずれでも、素 子突起電極 5の素子接合面の長さ（LI , L2)が、基板突起電極 4の基板接合面の長 さ（Wl , W2)よりも長くなつている。そして、同様に側面視において、図 4, 5の図面 左右方向では、素子突起電極 5の素子接合面の長さが、基板突起電極 4の基板接 合面の長さよりも長くなつてレ、る。 In the embodiment described above, as is clear from FIGS. 2, 4, and 5, the interposer substrate 2 When viewed from the side or the semiconductor element 3 side, the area of the element protruding electrode 4 is larger than the area of the substrate protruding electrode 5. Further, for example, in a side view of the semiconductor device shown in FIG. 1 in which the lateral force is also viewed, the length (LI, L2) is longer than the length (Wl, W2) of the substrate bonding surface of the substrate protruding electrode 4. Similarly, in side view, the length of the element bonding surface of the element protruding electrode 5 is longer than the length of the substrate bonding surface of the substrate protruding electrode 4 in the lateral direction of FIGS. .
[0068] 本発明は上述した実施形態に限定されるものではなぐ請求項に示した範囲で種 々の変更が可能である。すなわち、請求項に示した範囲で適宜変更した技術的手段 を組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。例え ば、上記実施形態では、いずれも突起電極の平面形状が四角形のものを示したが、 楕円形状や丸形状のものでも良い。  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention. For example, in the above-described embodiments, the planar shape of the protruding electrode is a square shape, but may be an elliptical shape or a round shape.
産業上の利用可能性  Industrial applicability
[0069] 本発明は、フィルム基板に実装されてシリコンにより構成されたインタポーザ基板と 、液晶を駆動するためにインタポーザ基板に実装された半導体素子とを備えた半導 体装置に適用することができる。  The present invention can be applied to a semiconductor device including an interposer substrate that is mounted on a film substrate and made of silicon, and a semiconductor element that is mounted on the interposer substrate to drive a liquid crystal. .

Claims

請求の範囲 The scope of the claims
[1] 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポ 一ザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体 素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極 と接合する素子突起電極を有する半導体装置にぉレ、て、  [1] An interposer substrate configured by a semiconductor mounted on a mounting substrate, and a semiconductor element mounted on the interposer substrate. The interposer substrate includes a substrate protruding electrode formed on the semiconductor element side. And the semiconductor element is connected to a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
前記素子突起電極の素子接合面の面積が、前記基板突起電極の基板接合面の 面積よりも大きレ、ことを特徴とする半導体装置。  An area of the element bonding surface of the element protruding electrode is larger than an area of the substrate bonding surface of the substrate protruding electrode.
[2] 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポ 一ザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体 素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極 と接合する素子突起電極を有する半導体装置にぉレ、て、  [2] An interposer substrate that is mounted on a mounting substrate and is made of a semiconductor, and a semiconductor element that is mounted on the interposer substrate. The interposer substrate includes a substrate protruding electrode formed on the semiconductor element side. And the semiconductor element is connected to a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
前記インタポーザ基板側又は前記半導体素子側から透視した場合に、前記素子突 起電極の面積が前記基板突起電極の面積よりも大きいことを特徴とする半導体装置 A semiconductor device characterized in that an area of the element protruding electrode is larger than an area of the substrate protruding electrode when seen through from the interposer substrate side or the semiconductor element side
〇 Yes
[3] 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポ 一ザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体 素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極 と接合する素子突起電極を有する半導体装置にぉレ、て、  [3] An interposer substrate mounted on a mounting substrate and made of a semiconductor, and a semiconductor element mounted on the interposer substrate. The interposer substrate includes a substrate protruding electrode formed on the semiconductor element side. And the semiconductor element is connected to a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
一側面視で、前記素子突起電極の素子接合面の長さが、前記基板突起電極の基 板接合面の長さよりも長レ、ことを特徴とする半導体装置。  In one side view, the length of the element bonding surface of the element protruding electrode is longer than the length of the substrate bonding surface of the substrate protruding electrode.
[4] 前記素子接合面及び前記基板接合面は、長方形状をしており、 [4] The element bonding surface and the substrate bonding surface have a rectangular shape,
前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置さ れており、  The major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other,
前記素子接合面の短軸方向の幅が、前記基板接合面の短軸方向の幅よりも広い 請求項 1記載の半導体装置。  The semiconductor device according to claim 1, wherein a width of the element bonding surface in the minor axis direction is wider than a width of the substrate bonding surface in the minor axis direction.
[5] 前記素子接合面の長軸方向の長さと前記基板接合面の長軸方向の長さとが、互い に等し!/、請求項 4記載の半導体装置。 5. The semiconductor device according to claim 4, wherein a length in the major axis direction of the element bonding surface and a length in the major axis direction of the substrate bonding surface are equal to each other!
[6] 前記基板接合面の長軸方向の長さは、前記素子接合面の長軸方向の長さよりも長 V、請求項 4記載の半導体装置。 [6] The length of the substrate bonding surface in the long axis direction is longer than the length of the element bonding surface in the long axis direction. V. The semiconductor device according to claim 4.
[7] 前記インタポーザ基板に垂直な方向から見て、前記素子接合面は、前記基板接合 面を囲むように配置されており、 [7] The element bonding surface is disposed so as to surround the substrate bonding surface when viewed from a direction perpendicular to the interposer substrate.
前記素子接合面及び前記基板接合面は、長方形状をしており、  The element bonding surface and the substrate bonding surface have a rectangular shape,
前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置さ れており、  The major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other,
前記インタポーザ基板に垂直な方向から見て、前記素子接合面の一辺は、前記基 板接合面の対応する一辺から 5〜； 10 m離れて配置されている請求項 1に記載の 半導体装置。  2. The semiconductor device according to claim 1, wherein when viewed from a direction perpendicular to the interposer substrate, one side of the element bonding surface is arranged 5 to 10 m away from a corresponding side of the substrate bonding surface.
[8] 前記素子突起電極の高さと前記基板突起電極の高さとが、互いに異なっている請 求項 1に記載の半導体装置。  [8] The semiconductor device according to [1], wherein a height of the element protruding electrode and a height of the substrate protruding electrode are different from each other.
[9] 前記素子突起電極の高さが、前記基板突起電極の高さよりも低!/、請求項 1に記載 の半導体装置。 9. The semiconductor device according to claim 1, wherein the height of the element protruding electrode is lower than the height of the substrate protruding electrode.
[10] 前記素子突起電極の高さが、 5〜8 11 mである請求項 1に記載の半導体装置。  10. The semiconductor device according to claim 1, wherein the height of the element protruding electrode is 5 to 8 11 m.
[11] 前記基板突起電極の高さが、 10〜； 15 πιである請求項 1に記載の半導体装置。 [11] The semiconductor device according to [1], wherein the height of the substrate protruding electrode is 10 to 15πι.
[12] 前記基板突起電極は、前記素子突起電極よりも硬度が高い請求項 1記載の半導体 装置。 12. The semiconductor device according to claim 1, wherein the substrate protruding electrode has higher hardness than the element protruding electrode.
[13] 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポ 一ザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体 素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極 と接合する端子を有することを特徴とする半導体装置。  [13] An interposer substrate configured by a semiconductor mounted on a mounting substrate, and a semiconductor element mounted on the interposer substrate, the interposer substrate having a substrate protruding electrode formed on the semiconductor element side And the semiconductor element has a terminal bonded to the substrate protruding electrode.
[14] 前記端子は、アルミニウムによって構成され、  [14] The terminal is made of aluminum,
前記基板突起電極は、金によって構成される請求項 13記載の半導体装置。  14. The semiconductor device according to claim 13, wherein the substrate protruding electrode is made of gold.
[15] 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポ 一ザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体 素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極 と接合する素子突起電極を有する半導体装置にぉレ、て、  [15] An interposer substrate configured by a semiconductor mounted on a mounting substrate, and a semiconductor element mounted on the interposer substrate, wherein the interposer substrate includes a substrate protruding electrode formed on the semiconductor element side. And the semiconductor element is connected to a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
前記素子突起電極の高さと前記基板突起電極の高さとが、互いに異なっていること を特徴とする半導体装置。 The height of the element protruding electrode and the height of the substrate protruding electrode are different from each other. A semiconductor device characterized by the above.
実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポ 一ザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体 素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極 と接合する素子突起電極を有する半導体装置にぉレ、て、  An interposer substrate mounted on a mounting substrate and made of a semiconductor; and a semiconductor element mounted on the interposer substrate, the interposer substrate having a substrate protruding electrode formed on the semiconductor element side, The semiconductor element is connected to a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode, and
前記素子突起電極の素子接合面及び前記基板突起電極の基板接合面は、長方 形状をしており、  The element bonding surface of the element protruding electrode and the substrate bonding surface of the substrate protruding electrode have a rectangular shape,
前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置さ れており、  The major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other,
前記素子接合面の短軸方向の幅が、前記基板接合面の短軸方向の幅よりも広ぐ 前記基板接合面の長軸方向の長さは、前記素子接合面の長軸方向の長さよりも長 Vヽことを特徴とする半導体装置。  The width of the element bonding surface in the minor axis direction is wider than the width of the substrate bonding surface in the minor axis direction. The length of the substrate bonding surface in the major axis direction is larger than the length of the element bonding surface in the major axis direction. A semiconductor device characterized by a long V ヽ.
PCT/JP2007/073454 2006-12-15 2007-12-05 Semiconductor device WO2008072510A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006339048A JP4376893B2 (en) 2006-12-15 2006-12-15 Semiconductor device
JP2006-339048 2006-12-15

Publications (1)

Publication Number Publication Date
WO2008072510A1 true WO2008072510A1 (en) 2008-06-19

Family

ID=39511531

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/073454 WO2008072510A1 (en) 2006-12-15 2007-12-05 Semiconductor device

Country Status (3)

Country Link
JP (1) JP4376893B2 (en)
TW (1) TW200843080A (en)
WO (1) WO2008072510A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5304536B2 (en) 2009-08-24 2013-10-02 ソニー株式会社 Semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0385642U (en) * 1989-12-22 1991-08-29
JPH05343473A (en) * 1992-06-11 1993-12-24 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH11251363A (en) * 1998-03-03 1999-09-17 Olympus Optical Co Ltd Flip-chip mounting method and structure thereof
JP2002208613A (en) * 2001-01-12 2002-07-26 Nec Kansai Ltd Semiconductor device
JP2004207566A (en) * 2002-12-26 2004-07-22 Seiko Instruments Inc Semiconductor device, display apparatus, and manufacturing method thereof
JP2005236123A (en) * 2004-02-20 2005-09-02 Advanced Display Inc Ic connection structure and liquid crystal display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0385642U (en) * 1989-12-22 1991-08-29
JPH05343473A (en) * 1992-06-11 1993-12-24 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH11251363A (en) * 1998-03-03 1999-09-17 Olympus Optical Co Ltd Flip-chip mounting method and structure thereof
JP2002208613A (en) * 2001-01-12 2002-07-26 Nec Kansai Ltd Semiconductor device
JP2004207566A (en) * 2002-12-26 2004-07-22 Seiko Instruments Inc Semiconductor device, display apparatus, and manufacturing method thereof
JP2005236123A (en) * 2004-02-20 2005-09-02 Advanced Display Inc Ic connection structure and liquid crystal display device

Also Published As

Publication number Publication date
JP4376893B2 (en) 2009-12-02
TW200843080A (en) 2008-11-01
JP2008153394A (en) 2008-07-03

Similar Documents

Publication Publication Date Title
US7649246B2 (en) Tab package connecting host device element
US6552419B2 (en) Semiconductor device and liquid crystal module using the same
US20120080789A1 (en) SEMICONDUCTOR CHIP AND MOUNTING STRUCTURE OF THE SAME (as amended)
US20110204497A1 (en) Semiconductor integrated circuit and method for manufacturing the same
JP4740708B2 (en) Wiring board and semiconductor device
JP2004235353A (en) Semiconductor device and display unit using same
JP2012164846A (en) Semiconductor device, semiconductor device manufacturing method and display device
US7906374B2 (en) COF packaging structure, method of manufacturing the COF packaging structure, and method for assembling a driver IC and the COF packaging structure thereof
JP2730536B2 (en) Liquid crystal display
WO2008072510A1 (en) Semiconductor device
JP4750149B2 (en) Semiconductor device
US20040178501A1 (en) Tape circuit substrate having wavy beam leads and semiconductor chip package using the same
US7385289B2 (en) Semiconductor device using inorganic film between wiring layer and bonding pad
JP5154275B2 (en) Magnetic sensor package
JP2004134653A (en) Substrate connecting structure and fabricating process of electronic parts therewith
JP3769979B2 (en) Display panel and display device including the same
JP5217013B2 (en) Power conversion device and manufacturing method thereof
JP5742623B2 (en) Semiconductor device
US20080020605A1 (en) Circuit board module
JP2012028636A (en) Tape carrier substrate and semiconductor device equipped with tape carrier substrate
WO2008041507A1 (en) Semiconductor package, and display
JP2001100238A (en) Electrode connection structure for liquid crystal display panel
JP2003234371A (en) Mounting structure for semiconductor device
JP2001202029A (en) Driver module for large-sized display panel
JP2006135247A (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07850096

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07850096

Country of ref document: EP

Kind code of ref document: A1