JP2008153394A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008153394A
JP2008153394A JP2006339048A JP2006339048A JP2008153394A JP 2008153394 A JP2008153394 A JP 2008153394A JP 2006339048 A JP2006339048 A JP 2006339048A JP 2006339048 A JP2006339048 A JP 2006339048A JP 2008153394 A JP2008153394 A JP 2008153394A
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substrate
protruding electrode
bonding surface
semiconductor
semiconductor device
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JP4376893B2 (en
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Tatsuya Kato
達也 加藤
Satoshi Kudose
智 久戸瀬
Tomokatsu Nakagawa
智克 中川
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Sharp Corp
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Sharp Corp
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Priority to JP2006339048A priority Critical patent/JP4376893B2/en
Priority to PCT/JP2007/073454 priority patent/WO2008072510A1/en
Priority to TW096147450A priority patent/TW200843080A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which stabilizes the quality of connection between a semiconductor element and an interposer substrate. <P>SOLUTION: The semiconductor device 1 includes the interposer substrate 2 which is made of a silicon and is mounted on a film substrate 8, and the semiconductor element 3 which is mounted on the interposer substrate 2 to drive a liquid crystal. The interposer substrate 2 has a substrate bump 4 formed toward the semiconductor element 3, and the semiconductor element 3 has an element bump 5 joined to the substrate bump 4. The area of an element junction face of the element bump 5 is greater than the area of a substrate junction face of the substrate bump 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置に関し、例えば、フィルム基板に実装されてシリコンにより構成されたインタポーザ基板と、液晶を駆動するためにインタポーザ基板に実装された半導体素子とを備えたＳＯＦ（Ｓｙｓｔｅｍ Ｏｎ Ｆｉｌｍ）に好適な半導体装置に関する。   The present invention relates to a semiconductor device, for example, in an SOF (System On Film) including an interposer substrate formed of silicon mounted on a film substrate and a semiconductor element mounted on the interposer substrate for driving liquid crystal. The present invention relates to a suitable semiconductor device.

集積回路（ＩＣ）に組み込まれるトランジスタの数は年々多くなっており、内部に構成される回路数も多くなっている。液晶パネルは近年高精細化が進み、表示画素が増加する分、駆動回路も増加する。増加した駆動回路を補うためには、液晶パネルに実装される液晶ドラバの数を増加させるか、１つの液晶ドライバに搭載される駆動回路を増加させる必要がある。近年では液晶パネルに実装される液晶ドライバの数が増加しないように後者の液晶ドライバの駆動回路を増加で対応することが多い。   The number of transistors incorporated in an integrated circuit (IC) is increasing year by year, and the number of circuits configured therein is also increasing. In recent years, liquid crystal panels have become higher in definition, and the number of display circuits increases, so that drive circuits also increase. In order to compensate for the increased drive circuit, it is necessary to increase the number of liquid crystal drivers mounted on the liquid crystal panel or increase the drive circuit mounted on one liquid crystal driver. In recent years, in order to prevent an increase in the number of liquid crystal drivers mounted on a liquid crystal panel, the latter liquid crystal driver drive circuit is often increased.

集積回路チップは、チップサイズが小さいほど量産効率がよく、チップの原価は安くなる。そのため、多出力のドライバでは、チップサイズ縮小のためにパッドをファインピッチ化することが必要となる。また、集積回路チップのパッドのファインピッチ化に伴い、ドライバのパッケージであるフィルムのインナーリード（液晶ドライバとフィルムをつなぐ配線）のピッチもファインピッチ化する必要がある。ファインピッチ化を実現可能にする構造として、ＳＯＦ（Ｓｙｓｔｅｍ Ｏｎ Ｆｉｌｍ：ＣＯＦ（Ｃｈｉｐ Ｏｎ Ｆｉｌｍ）とも呼ばれる）が知られている。   An integrated circuit chip has a higher mass production efficiency as the chip size is smaller, and the cost of the chip is lower. Therefore, in a multi-output driver, it is necessary to make the pads finer in order to reduce the chip size. In addition, with the fine pitch of the pads of the integrated circuit chip, the pitch of the film inner leads (wiring connecting the liquid crystal driver and the film) as the driver package needs to be fine. SOF (System On Film: also called COF (Chip On Film)) is known as a structure that enables fine pitch.

図８は、従来の半導体装置９１の構成を示す模式断面図である。半導体装置９１は、フィルム基板９８を備えている。フィルム基板９８は、孔８２を有している。フィルム基板９８の表面には、配線パターン８１が形成されている。   FIG. 8 is a schematic cross-sectional view showing a configuration of a conventional semiconductor device 91. The semiconductor device 91 includes a film substrate 98. The film substrate 98 has a hole 82. A wiring pattern 81 is formed on the surface of the film substrate 98.

半導体装置９１には、インタポーザ基板９２が設けられている。インタポーザ基板９２のフィルム基板９８側の表面の配線パターン８１に対向する位置には、金によって構成された複数個の突起電極９０が設けられている。インタポーザ基板９２は、突起電極９０及び配線パターン８１を介してフィルム基板９８に実装されている。   The semiconductor device 91 is provided with an interposer substrate 92. A plurality of protruding electrodes 90 made of gold are provided at positions facing the wiring pattern 81 on the surface of the interposer substrate 92 on the film substrate 98 side. The interposer substrate 92 is mounted on the film substrate 98 via the protruding electrodes 90 and the wiring patterns 81.

インタポーザ基板９２のフィルム基板９８側の表面の孔８２に対向する位置には、金によって構成された複数個の基板突起電極９４が設けられている。   A plurality of substrate protruding electrodes 94 made of gold are provided at positions facing the holes 82 on the surface of the interposer substrate 92 on the film substrate 98 side.

フィルム基板９８の孔８２の中には、半導体素子９３が設けられている。半導体素子９３のインタポーザ基板９２側の表面の各基板突起電極９４に対向する位置には、金によって構成された複数個の素子突起電極９５が設けられている。半導体素子９３は、素子突起電極９５及び基板突起電極９４を介してインタポーザ基板９２に実装されている。半導体素子９３とフィルム基板９８との間、並びに、インタポーザ基板９２とフィルム基板９８及び半導体素子９３との間には、封止樹脂９９が封止されている。
特開２００４−２０７５６６号公報（平成１６年７月２２日公開） A semiconductor element 93 is provided in the hole 82 of the film substrate 98. A plurality of element protrusion electrodes 95 made of gold are provided at positions facing the substrate protrusion electrodes 94 on the surface of the semiconductor element 93 on the interposer substrate 92 side. The semiconductor element 93 is mounted on the interposer substrate 92 via the element protruding electrode 95 and the substrate protruding electrode 94. Sealing resin 99 is sealed between the semiconductor element 93 and the film substrate 98 and between the interposer substrate 92, the film substrate 98 and the semiconductor element 93.
Japanese Patent Application Laid-Open No. 2004-207566 (released on July 22, 2004)

しかしながら、上記従来の構成では、半導体素子９３をインタポーザ基板９２に実装する際に、素子突起電極９５と基板突起電極９４との接合位置ズレが生じ、素子突起電極９５の接合面が、基板突起電極９４の接合面からはみ出して、接合荷重が変動する結果、半導体素子９３とインタポーザ基板９２との接合品質が不安定になるという問題がある。   However, in the above-described conventional configuration, when the semiconductor element 93 is mounted on the interposer substrate 92, a displacement of the bonding position between the element protruding electrode 95 and the substrate protruding electrode 94 occurs, and the bonding surface of the element protruding electrode 95 is the substrate protruding electrode. There is a problem that the bonding quality of the semiconductor element 93 and the interposer substrate 92 becomes unstable as a result of fluctuation of the bonding load that protrudes from the bonding surface 94.

本発明は、上記の問題点に鑑みてなされたものであり、その目的は、半導体素子とインタポーザ基板との接合品質を安定化させることができる半導体装置を実現することにある。   The present invention has been made in view of the above-described problems, and an object thereof is to realize a semiconductor device capable of stabilizing the bonding quality between a semiconductor element and an interposer substrate.

本発明に係る半導体装置は、上記課題を解決するために、実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、前記素子突起電極の素子接合面の面積が、前記基板突起電極の基板接合面の面積よりも大きいことを特徴とする。   In order to solve the above-described problems, a semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and configured of a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate includes In a semiconductor device having a substrate protruding electrode formed on a semiconductor element side, the semiconductor element having an element protruding electrode bonded to the substrate protruding electrode, the area of the element bonding surface of the element protruding electrode is the substrate protruding It is characterized by being larger than the area of the substrate bonding surface of the electrode.

また、本発明に係る他の半導体装置は、実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、前記インタポーザ基板側又は前記半導体素子側から透視した場合に、前記素子突起電極の面積が前記基板突起電極の面積よりも大きいことを特徴とする。   In addition, another semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and configured by a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate is disposed on the semiconductor element side. In a semiconductor device having a formed substrate protruding electrode, and the semiconductor element has an element protruding electrode bonded to the substrate protruding electrode, the element protruding electrode is seen through from the interposer substrate side or the semiconductor element side. The area is larger than the area of the substrate protruding electrode.

また、本発明に係るさらに他の半導体装置は、実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、一側面視で、前記素子突起電極の素子接合面の長さが、前記基板突起電極の基板接合面の長さよりも長いことを特徴とする。   Further, another semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and configured by a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate is on the semiconductor element side. In the semiconductor device having the substrate projection electrode formed on the semiconductor projection device, the semiconductor element has an element projection electrode to be bonded to the substrate projection electrode. It is longer than the length of the substrate bonding surface of the substrate protruding electrode.

上記の特徴によれば、基板突起電極と素子突起電極との接合位置にズレが生じても、素子突起電極は、基板突起電極の基板接合面のうちの広い面積の面と接触することができ、接合荷重の変動が抑制されて、接合品質を安定化することができる。   According to the above feature, even if the bonding position between the substrate protruding electrode and the element protruding electrode is displaced, the element protruding electrode can be in contact with a large area of the substrate bonding surfaces of the substrate protruding electrode. The fluctuation of the bonding load is suppressed, and the bonding quality can be stabilized.

なお、突起電極とは、通常「バンプ」と呼ばれているもので、電極部の表面に形成され、電気的に接続する対象物と接合されるものである。   Note that the protruding electrode is generally called a “bump” and is formed on the surface of the electrode portion and bonded to an object to be electrically connected.

本発明に係る半導体装置では、前記素子接合面及び前記基板接合面は、長方形状をしており、前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置されており、前記素子接合面の短軸方向の幅が、前記基板接合面の短軸方向の幅よりも広いことが好ましい。   In the semiconductor device according to the present invention, the element bonding surface and the substrate bonding surface have a rectangular shape, and the major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other, The width in the minor axis direction of the element bonding surface is preferably wider than the width in the minor axis direction of the substrate bonding surface.

上記構成によれば、基板接合面の短軸方向に沿った接合位置のズレに対して、好適に接合荷重の変動を抑制し、接合品質を安定化することができる。   According to the said structure, the fluctuation | variation of a joining load can be suppressed suitably with respect to the shift | offset | difference of the joining position along the short-axis direction of a board | substrate joining surface, and joining quality can be stabilized.

本発明に係る半導体装置では、前記素子接合面の長軸方向の長さと前記基板接合面の長軸方向の長さとが、互いに等しいことが好ましい。   In the semiconductor device according to the present invention, it is preferable that a length in the major axis direction of the element bonding surface and a length in the major axis direction of the substrate bonding surface are equal to each other.

基板突起電極の長軸方向に沿った側壁が、素子突起電極の素子接合面に食い込んで接合強度が増大するが、上記構成によれば、素子接合面に食い込む基板突起電極の側壁が長くなり、噛み合うように接合するので、接合強度が増大し、接合品質が向上する。   Although the side wall along the major axis direction of the substrate protruding electrode bites into the element bonding surface of the element protruding electrode and the bonding strength increases, according to the above configuration, the side wall of the substrate protruding electrode bites into the element bonding surface becomes long, Since it joins so that it may mesh | engage, joining strength increases and joining quality improves.

本発明に係る半導体装置では、前記基板接合面の長軸方向の長さは、前記素子接合面の長軸方向の長さよりも長いことが好ましい。   In the semiconductor device according to the present invention, it is preferable that the length of the substrate bonding surface in the long axis direction is longer than the length of the element bonding surface in the long axis direction.

上記構成によれば、基板突起電極の長軸方向に沿った側壁が、素子突起電極の素子接合面に食い込むのみならず、素子突起電極の短軸方向に沿った側壁が、基板突起電極の基板接合面に逆方向に食い込む。このため、基板突起電極と素子突起電極とが、互いに噛み合うように接合して、接合強度がより一層増大し、接合品質がより一層向上する。   According to the above configuration, the side wall along the long axis direction of the substrate protruding electrode does not only bite into the element bonding surface of the element protruding electrode, but the side wall along the short axis direction of the element protruding electrode serves as the substrate of the substrate protruding electrode. Cut into the joint surface in the opposite direction. For this reason, a board | substrate protruding electrode and an element protruding electrode are joined so that it may mutually mesh | engage, joining strength increases further, and joining quality improves further.

本発明に係る半導体装置では、前記インタポーザ基板に垂直な方向から見て、前記素子接合面は、前記基板接合面を囲むように配置されており、前記素子接合面及び前記基板接合面は、長方形状をしており、前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置されており、前記インタポーザ基板に垂直な方向から見て、前記素子接合面の一辺は、前記基板接合面の対応する一辺から５〜１０μｍ離れて配置されていることが好ましい。   In the semiconductor device according to the present invention, when viewed from a direction perpendicular to the interposer substrate, the element bonding surface is disposed so as to surround the substrate bonding surface, and the element bonding surface and the substrate bonding surface are rectangular. The major surfaces of the element bonding surface and the substrate bonding surface are arranged in parallel to each other, and when viewed from a direction perpendicular to the interposer substrate, one side of the element bonding surface is It is preferable that the substrate is disposed 5 to 10 μm away from the corresponding side of the substrate bonding surface.

上記構成によれば、接合位置のズレがどの方向に５〜１０μｍ生じても、接合荷重の変動を抑制し、接合品質を安定化することができる。   According to the said structure, even if the shift | offset | difference of a joining position arises 5-10 micrometers in which direction, the fluctuation | variation of joining load can be suppressed and joining quality can be stabilized.

本発明に係る半導体装置では、前記素子突起電極の高さと前記基板突起電極の高さとが、互いに異なっていることが好ましい。   In the semiconductor device according to the present invention, it is preferable that a height of the element protruding electrode and a height of the substrate protruding electrode are different from each other.

上記構成によれば、素子突起電極または基板突起電極を低くすることができ、高さのバラツキを低減して、接合品質を安定化することができる。   According to the above configuration, the element protruding electrode or the substrate protruding electrode can be lowered, the variation in height can be reduced, and the bonding quality can be stabilized.

例えばテープキャリアのように曲げ加工し易いように薄くて可撓性が高い素材をパッケージ基材として構成した場合、テープキャリアにインターポーザ基板を接続する際、前記基板突起電極が低いとテープキャリアの配線とインターポーザ基板の端部の間隔が充分に確保できず、テープキャリアの配線がインターポーザ基板の端部に接触して、テープキャリアの配線導体間の短絡が生じることがある。例えば基板突起電極を１５μｍで作製し、基板突起電極とテープキャリアの配線を接続した場合にテープキャリアの配線とインターポーザ基板の端部との間隔は９μｍ程度確保できるため、基板突起電極高さが、１０〜１５μｍであればテープキャリアの配線とインターポーザ基板の端部との間隔が充分に確保でき、配線同士の短絡を避けることができる。また、素子突起電極はそのような心配が無い為、前記基板突起電極の高さよりも低くできる。   For example, when a thin and highly flexible material such as a tape carrier is easy to bend as the package base material, when connecting the interposer substrate to the tape carrier, if the substrate protruding electrode is low, the wiring of the tape carrier In some cases, the gap between the end portions of the interposer substrate cannot be secured sufficiently, and the wiring of the tape carrier comes into contact with the end portion of the interposer substrate, causing a short circuit between the wiring conductors of the tape carrier. For example, when the substrate protruding electrode is made at 15 μm and the substrate protruding electrode and the tape carrier wiring are connected, the distance between the tape carrier wiring and the end of the interposer substrate can be secured about 9 μm. If it is 10-15 micrometers, the space | interval of the wiring of a tape carrier and the edge part of an interposer board | substrate can fully be ensured, and the short circuit of wiring can be avoided. Further, since the element protruding electrode does not have such a concern, it can be made lower than the height of the substrate protruding electrode.

そのため本発明に係る半導体装置では、前記素子突起電極の高さが、前記基板突起電極の高さよりも低いことが好ましい。   Therefore, in the semiconductor device according to the present invention, it is preferable that the height of the element protruding electrode is lower than the height of the substrate protruding electrode.

上記構成によれば、素子突起電極を基板突起電極よりも低くすることができ、素子突起電極の高さのバラツキを低減して、Ａｕ使用量を削減し、接合品質を安定化することができる。   According to the above configuration, the element protruding electrode can be made lower than the substrate protruding electrode, the variation in the height of the element protruding electrode can be reduced, the amount of Au used can be reduced, and the bonding quality can be stabilized. .

本発明に係る半導体装置では、前記素子突起電極の高さが、５〜８μｍであることが好ましい。   In the semiconductor device according to the present invention, it is preferable that a height of the element protruding electrode is 5 to 8 μm.

上記構成によれば、素子突起電極を低くすることができ、素子突起電極の高さのバラツキを低減して、Ａｕ使用量を削減してコストを低減するとともに、接合品質を安定化することができる。   According to the above configuration, the element protruding electrode can be lowered, the variation in the height of the element protruding electrode can be reduced, the amount of Au used can be reduced, the cost can be reduced, and the bonding quality can be stabilized. it can.

本発明に係る半導体装置では、前記基板突起電極の高さが、１０〜１５μｍであることが好ましい。   In the semiconductor device according to the present invention, it is preferable that a height of the substrate protruding electrode is 10 to 15 μm.

上記構成によれば、基板突起電極を低くして、Ａｕ使用量削減によるコストダウンを実現し、バンプ高さのバラツキを低減して、接合品質を安定化することができる。   According to the above configuration, it is possible to lower the substrate protruding electrode, to realize cost reduction by reducing the amount of Au used, to reduce the bump height variation, and to stabilize the bonding quality.

本発明に係る半導体装置では、前記基板突起電極は、前記素子突起電極よりも硬度が高いことが好ましい。   In the semiconductor device according to the present invention, it is preferable that the substrate protruding electrode has a hardness higher than that of the element protruding electrode.

上記構成によれば、硬度が高い基板突起電極が、柔らかい素子突起電極に食い込むので、接合強度が向上する。   According to the above configuration, since the substrate protruding electrode having high hardness bites into the soft element protruding electrode, the bonding strength is improved.

本発明に係る他の半導体装置は、上記課題を解決するために、実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する端子を有することを特徴とする。   In order to solve the above problems, another semiconductor device according to the present invention includes an interposer substrate that is mounted on a mounting substrate and configured by a semiconductor, and a semiconductor element that is mounted on the interposer substrate, and the interposer substrate includes: The semiconductor element has a substrate protruding electrode formed on the semiconductor element side, and the semiconductor element has a terminal bonded to the substrate protruding electrode.

上記特徴により、半導体素子側に突起電極を設けないので、Ａｕ使用量低減によるコストダウンを実現することができる。   Due to the above feature, since no protruding electrode is provided on the semiconductor element side, it is possible to realize cost reduction by reducing the amount of Au used.

本発明に係る半導体装置では、前記端子は、アルミニウムによって構成され、前記基板突起電極は、金によって構成されることが好ましい。   In the semiconductor device according to the present invention, it is preferable that the terminal is made of aluminum, and the substrate protruding electrode is made of gold.

上記構成によれば、ワイヤーボンド等の一般的なＡｌ−Ａｕ接合により、接合品質の安定化を図ることができる。   According to the said structure, stabilization of joining quality can be aimed at by common Al-Au joining, such as a wire bond.

本発明に係るさらに他の半導体装置は、実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、前記素子突起電極の高さと前記基板突起電極の高さとが、互いに異なっていることを特徴とする。   Still another semiconductor device according to the present invention includes an interposer substrate configured by a semiconductor mounted on a mounting substrate, and a semiconductor element mounted on the interposer substrate, and the interposer substrate is formed on the semiconductor element side. In the semiconductor device having the element protruding electrode bonded to the substrate protruding electrode, the height of the element protruding electrode and the height of the substrate protruding electrode are different from each other. It is characterized by that.

上記特徴により、素子突起電極を、基板突起電極よりも低く構成することができ、素子突起電極の高さのバラツキを低減して、Ａｕ使用量を削減し、接合品質を安定化することができる。   With the above features, the element protruding electrode can be configured lower than the substrate protruding electrode, the variation in the height of the element protruding electrode can be reduced, the amount of Au used can be reduced, and the bonding quality can be stabilized. .

本発明に係るさらに他の半導体装置は、実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、前記素子突起電極の素子接合面及び前記基板突起電極の基板接合面は、長方形状をしており、前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置されており、前記素子接合面の短軸方向の幅が、前記基板接合面の短軸方向の幅よりも広く、前記基板接合面の長軸方向の長さは、前記素子接合面の長軸方向の長さよりも長いことを特徴とする。   Still another semiconductor device according to the present invention includes an interposer substrate configured by a semiconductor mounted on a mounting substrate, and a semiconductor element mounted on the interposer substrate, and the interposer substrate is formed on the semiconductor element side. In the semiconductor device having the element protruding electrode bonded to the substrate protruding electrode, the element bonding surface of the element protruding electrode and the substrate bonding surface of the substrate protruding electrode are rectangular. The major axis of each of the element bonding surface and the substrate bonding surface is arranged in parallel to each other, and the width of the element bonding surface in the minor axis direction is the minor axis direction of the substrate bonding surface. And the length of the substrate bonding surface in the major axis direction is longer than the length of the element bonding surface in the major axis direction.

上記特徴により、基板突起電極の長軸方向に沿った側壁が、素子突起電極の素子接合面に食い込むのみならず、素子突起電極の短軸方向に沿った側壁が、基板突起電極の基板接合面に逆方向に食い込む。このため、基板突起電極と素子突起電極とが、互いに噛み合うように接合して、接合強度がより一層増大し、接合品質がより一層向上する。   With the above feature, the side wall along the long axis direction of the substrate protruding electrode does not only bite into the element bonding surface of the element protruding electrode, but the side wall along the short axis direction of the element protruding electrode is not limited to the substrate bonding surface of the substrate protruding electrode. Cut in the opposite direction. For this reason, a board | substrate protruding electrode and an element protruding electrode are joined so that it may mutually mesh | engage, joining strength increases further, and joining quality improves further.

本発明に係る半導体装置は、以上のように、基板突起電極と素子突起電極との接合位置にズレが生じても、素子突起電極は、基板突起電極の基板接合面のうちの広い面積の面と接触することができ、接合荷重の変動が抑制されて、接合品質を安定化することができるという効果を奏する。   In the semiconductor device according to the present invention, as described above, even if the bonding position between the substrate protruding electrode and the element protruding electrode is shifted, the element protruding electrode is a surface having a large area among the substrate bonding surfaces of the substrate protruding electrode. It is possible to make contact with each other, the fluctuation of the bonding load is suppressed, and the bonding quality can be stabilized.

本発明の一実施形態について図１ないし図７に基づいて説明すると以下の通りである。図１は、実施の形態に係る半導体装置１の構成を示す模式断面図である。半導体装置１は、フィルム基板８を備えている。フィルム基板８は、孔１２を有している。フィルム基板８の表面には、配線パターン１１が形成されている。   An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device 1 according to an embodiment. The semiconductor device 1 includes a film substrate 8. The film substrate 8 has a hole 12. A wiring pattern 11 is formed on the surface of the film substrate 8.

半導体装置１には、インタポーザ基板２が設けられている。インタポーザ基板２のフィルム基板８側の表面の配線パターン１１に対向する位置には、金によって構成された複数個の突起電極（バンプ）１０が設けられている。インタポーザ基板２は、突起電極１０及び配線パターン１１を介してフィルム基板８に実装されている。   The semiconductor device 1 is provided with an interposer substrate 2. A plurality of protruding electrodes (bumps) 10 made of gold are provided at a position facing the wiring pattern 11 on the surface of the interposer substrate 2 on the film substrate 8 side. The interposer substrate 2 is mounted on the film substrate 8 via the protruding electrodes 10 and the wiring patterns 11.

インタポーザ基板２のフィルム基板８側の表面の孔２に対向する位置には、金によって構成された複数個の基板突起電極（バンプ）４が設けられている。   A plurality of substrate protruding electrodes (bumps) 4 made of gold are provided at positions facing the holes 2 on the surface of the interposer substrate 2 on the film substrate 8 side.

フィルム基板８の孔１２の中には、液晶を駆動するための半導体素子３が設けられている。半導体素子３のインタポーザ基板２側の表面の各基板突起電極４に対向する位置には、金によって構成された複数個の素子突起電極（バンプ）５が設けられている。半導体素子３は、素子突起電極５及び基板突起電極４を介してインタポーザ基板２に実装されている。半導体素子３とフィルム基板８との間、並びに、インタポーザ基板２とフィルム基板８及び半導体素子３との間には、封止樹脂９が封止されている。   A semiconductor element 3 for driving the liquid crystal is provided in the hole 12 of the film substrate 8. A plurality of element protrusion electrodes (bumps) 5 made of gold are provided at positions facing the substrate protrusion electrodes 4 on the surface of the semiconductor element 3 on the interposer substrate 2 side. The semiconductor element 3 is mounted on the interposer substrate 2 via the element protruding electrode 5 and the substrate protruding electrode 4. A sealing resin 9 is sealed between the semiconductor element 3 and the film substrate 8 and between the interposer substrate 2, the film substrate 8, and the semiconductor element 3.

図２は、実施の形態に係る基板突起電極４の基板接合面６と素子突起電極５の素子接合面７との寸法関係を示す模式断面図であり、図１に示す断面ＡＡに沿った模式断面図である。基板接合面６は、長方形状をしている。素子接合面７は、基板接合面６よりも大きな長方形状をしており、基板接合面６を囲むように配置されている。素子接合面７及び基板接合面６のそれぞれの長軸は、一致している。素子接合面７の短軸方向の幅Ｗ２は、基板接合面６の短軸方向の幅Ｗ１よりも広い。素子接合面７の長軸方向の長さＬ２は、基板接合面６の長軸方向の長さＬ１よりも長い。基板接合面６の長軸方向に沿った縁辺は、素子接合面７の長軸方向に沿った縁辺から距離Ｄ１だけ離れている。基板接合面６の短軸方向に沿った縁辺は、素子接合面７の短軸方向に沿った縁辺から距離Ｄ２だけ離れている。素子接合面７の長さＬ２は、例えば７５μｍであり、幅Ｗ２は、例えば４５μｍである。基板接合面６の長さＬ１は、例えば６０μｍであり、幅Ｗ１は、例えば３０μｍである。従って、距離Ｄ１及び距離Ｄ２は、７．５μｍである。   FIG. 2 is a schematic cross-sectional view showing a dimensional relationship between the substrate bonding surface 6 of the substrate protruding electrode 4 and the element bonding surface 7 of the element protruding electrode 5 according to the embodiment, and is a schematic cross section along the section AA shown in FIG. It is sectional drawing. The substrate bonding surface 6 has a rectangular shape. The element bonding surface 7 has a rectangular shape larger than the substrate bonding surface 6 and is disposed so as to surround the substrate bonding surface 6. The major axes of the element bonding surface 7 and the substrate bonding surface 6 coincide with each other. The width W2 in the minor axis direction of the element bonding surface 7 is wider than the width W1 in the minor axis direction of the substrate bonding surface 6. The length L2 in the major axis direction of the element bonding surface 7 is longer than the length L1 in the major axis direction of the substrate bonding surface 6. The edge along the major axis direction of the substrate bonding surface 6 is separated from the edge along the major axis direction of the element bonding surface 7 by a distance D1. The edge along the minor axis direction of the substrate bonding surface 6 is separated from the edge along the minor axis direction of the element bonding surface 7 by a distance D2. The length L2 of the element bonding surface 7 is, for example, 75 μm, and the width W2 is, for example, 45 μm. The length L1 of the substrate bonding surface 6 is, for example, 60 μm, and the width W1 is, for example, 30 μm. Therefore, the distance D1 and the distance D2 are 7.5 μm.

基板突起電極４は、素子突起電極５よりも硬度が高くなっている。突起電極の硬度は、アニールの有無によって調整することができる。硬くて細い基板突起電極４が、柔らかくて低い素子突起電極５に食い込むことにより、接合品質を向上させることができる。   The substrate protruding electrode 4 has a higher hardness than the element protruding electrode 5. The hardness of the protruding electrode can be adjusted by the presence or absence of annealing. The hard and thin substrate protruding electrode 4 bites into the soft and low element protruding electrode 5, whereby the bonding quality can be improved.

また、素子突起電極５の表面粗度と、基板突起電極４の表面粗度とを０．５μｍ以上異ならせてもよい。接触面の凹凸を大きくして接触面積を増大させ、接合強度を大きくして接合品質を増大させることができる。突起電極の表面粗度は、エッチング液に浸す時間等のメッキ条件を変更することによって調整することができる。   Further, the surface roughness of the element protrusion electrode 5 and the surface roughness of the substrate protrusion electrode 4 may be different by 0.5 μm or more. By increasing the unevenness of the contact surface, the contact area can be increased, and the bonding strength can be increased by increasing the bonding strength. The surface roughness of the protruding electrode can be adjusted by changing the plating conditions such as the time of immersion in the etching solution.

また、バンプ潰れ状態を確認するためのバンプを、チップのコーナ部に設けてもよい。赤外線顕微鏡による画像により、バンプが広がっているほど、バンプ同士がぶつかり合って圧縮されていると判断することができ、この判断に基づいて微調整することが可能になるので、接合品質を向上させることができる。   Further, bumps for confirming the collapsed state of the bumps may be provided at the corners of the chip. It can be judged from the image taken with an infrared microscope that bumps collide with each other as the bumps spread, and it can be judged that the bumps are compressed and fine adjustment can be made based on this judgment, thus improving the bonding quality. be able to.

また、基板突起電極４及び素子突起電極５のインタポーザ基板３に垂直な方向から見た形状は、正方形であってもよい。従来のＳＯＦでは、リードとの接合面積を確保するためにバンプを縦長の長方形にする必要があったが、本実施の形態では、バンプはメタル配線と接続すればよく、リードと接合する必要がなくなるため、正方形にして、接合状態を均一にし、接合品質を高めることができる。   The shape of the substrate protruding electrode 4 and the element protruding electrode 5 viewed from the direction perpendicular to the interposer substrate 3 may be a square. In the conventional SOF, the bumps have to be formed in a vertically long rectangle in order to secure a bonding area with the leads. In this embodiment, the bumps need only be connected to the metal wiring, and need to be bonded to the leads. Therefore, it can be made square to make the joining state uniform and to improve the joining quality.

このように、基板突起電極４のバンプサイズと、素子突起電極５のバンプサイズとは、互いに異なっており、素子突起電極５のバンプサイズは、基板突起電極４のバンプサイズよりも大きい。このため、バンプ形成位置ズレ、立ち上げ位置ズレ、及び設備能力に起因する接合位置ズレによって生じる接合荷重の変動を抑制することができる。   Thus, the bump size of the substrate protrusion electrode 4 and the bump size of the element protrusion electrode 5 are different from each other, and the bump size of the element protrusion electrode 5 is larger than the bump size of the substrate protrusion electrode 4. For this reason, the fluctuation | variation of the bonding load which arises by the bonding position shift resulting from a bump formation position shift, a starting position shift, and equipment capability can be suppressed.

図３は、実施の形態に係る基板突起電極４と素子突起電極５との寸法関係を示す模式断面図である。基板突起電極４のバンプ高さＨ１は、例えば１５μｍであり、素子突起電極５バンプ高さＨ２は、例えば８μｍである。このように、素子突起電極５のバンプ高さと、基板突起電極４のバンプ高さとは、互いに異なっており、素子突起電極５のバンプ高さは、基板突起電極４のバンプ高さよりも低くなっている。素子突起電極５のバンプ高さＨ２は、例えば５μｍに低くしてもよい。   FIG. 3 is a schematic cross-sectional view showing a dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. The bump height H1 of the substrate protruding electrode 4 is, for example, 15 μm, and the bump height H2 of the element protruding electrode 5 is, for example, 8 μm. As described above, the bump height of the element protrusion electrode 5 and the bump height of the substrate protrusion electrode 4 are different from each other, and the bump height of the element protrusion electrode 5 is lower than the bump height of the substrate protrusion electrode 4. Yes. The bump height H2 of the element protruding electrode 5 may be as low as 5 μm, for example.

このように、素子突起電極５のバンプ高さを低くすると、Ａｕの使用量を削減することができ、コストを低減することができる。また、素子突起電極５のバンプ高さを低くすると、素子突起電極５の高さバラツキが低減するので、接合品質が安定する。   Thus, if the bump height of the element protruding electrode 5 is lowered, the amount of Au used can be reduced, and the cost can be reduced. Further, when the bump height of the element protrusion electrode 5 is lowered, the height variation of the element protrusion electrode 5 is reduced, so that the bonding quality is stabilized.

基板突起電極４のバンプ高さＨ１は、例えば１０μｍに低くしてもよい。基板突起電極４を低くすると、Ａｕの使用量を削減することができ、コストを低減することができる。また、高さバラツキが低減するので、接合品質が安定する。   The bump height H1 of the substrate protruding electrode 4 may be as low as 10 μm, for example. When the substrate protruding electrode 4 is lowered, the amount of Au used can be reduced, and the cost can be reduced. Further, since the height variation is reduced, the bonding quality is stabilized.

以上のように、大きくて低いバンプである素子突起電極５を、細くて高いバンプである基板突起電極４に接合すると、素子突起電極５と基板突起電極４との接合品質が安定する。   As described above, when the element protruding electrode 5 that is a large and low bump is bonded to the substrate protruding electrode 4 that is a thin and high bump, the bonding quality between the element protruding electrode 5 and the substrate protruding electrode 4 is stabilized.

サイズの異なる素子突起電極５と基板突起電極４とは、全バンプ中、接合面積で換算して、８０％程度にする。残りの２０％のバンプは、サイズを等しくしている。なお、全てのバンプにおいて、上下バンプサイズが異なるように構成してもよい。   The element projecting electrode 5 and the substrate projecting electrode 4 having different sizes are converted to a bonding area of about 80% in all the bumps. The remaining 20% of the bumps are the same size. In addition, you may comprise so that the upper and lower bump size may differ in all the bumps.

また、半導体素子３の入力端子に接続して設けられる入力バンプ、及び出力端子に接続して設けられる出力バンプ以外に、冗長バンプを設けてもよい。また、入力バンプにおいて、電源系及びＧＮＤ系のバンプを冗長的に複数個設けると、デバイス特性の安定化により高品質化を図ることができる。   In addition to the input bumps connected to the input terminals of the semiconductor element 3 and the output bumps connected to the output terminals, redundant bumps may be provided. In addition, when the input bumps are provided with a plurality of redundant power supply and GND bumps, high quality can be achieved by stabilizing the device characteristics.

また、素子突起電極５を設けず、半導体素子３にアルミニウムによって形成された端子に基板突起電極４を接合するように構成してもよい。ワイヤーボンド等の一般的なＡｌ−Ａｕ接合により、接合品質を安定化することができる。   Alternatively, the substrate protruding electrode 4 may be bonded to a terminal formed of aluminum on the semiconductor element 3 without providing the element protruding electrode 5. Bonding quality can be stabilized by general Al—Au bonding such as wire bonding.

図４は、実施の形態に係る基板突起電極４の基板接合面６と素子突起電極５の素子接合面７との他の寸法関係を示す模式断面図である。素子接合面７の長軸方向の長さと基板接合面６の長軸方向の長さとは、互いに等しくてもよい。基板突起電極４の長軸方向に沿った側壁が、素子突起電極５の素子接合面７に食い込んで接合強度が増大するが、図４に示すように構成すると、素子接合面７に食い込む基板突起電極４の側壁が、図２に示す構成よりも長くなり、噛み合うように接合するので、接合強度が増大し、接合品質が向上する。   FIG. 4 is a schematic cross-sectional view showing another dimensional relationship between the substrate bonding surface 6 of the substrate protruding electrode 4 and the element bonding surface 7 of the element protruding electrode 5 according to the embodiment. The length in the major axis direction of the element bonding surface 7 and the length in the major axis direction of the substrate bonding surface 6 may be equal to each other. The side wall along the major axis direction of the substrate protruding electrode 4 bites into the element bonding surface 7 of the element protruding electrode 5 to increase the bonding strength. However, if configured as shown in FIG. Since the side walls of the electrode 4 are longer than the configuration shown in FIG. 2 and are joined so as to mesh with each other, the joining strength is increased and the joining quality is improved.

図５は、実施の形態に係る基板突起電極４の基板接合面６と素子突起電極５の素子接合面７とのさらに他の寸法関係を示す模式断面図である。基板接合面６の長軸方向の長さは、素子接合面７の長軸方向の長さよりも長く構成してもよい。このように構成すると、基板突起電極４の長軸方向に沿った側壁が、素子突起電極５の素子接合面７に食い込むのみならず、素子突起電極５の短軸方向に沿った側壁が、基板突起電極４の基板接合面６に逆方向に食い込む。このため、基板突起電極４と素子突起電極５とが、互いに噛み合うように接合して、接合強度がより一層増大し、接合品質がより一層向上する。   FIG. 5 is a schematic cross-sectional view showing still another dimensional relationship between the substrate bonding surface 6 of the substrate protruding electrode 4 and the element bonding surface 7 of the element protruding electrode 5 according to the embodiment. The length of the substrate bonding surface 6 in the long axis direction may be longer than the length of the element bonding surface 7 in the long axis direction. With this configuration, not only the side wall along the major axis direction of the substrate projection electrode 4 bites into the element bonding surface 7 of the element projection electrode 5, but also the side wall along the minor axis direction of the element projection electrode 5 It bites into the substrate bonding surface 6 of the protruding electrode 4 in the opposite direction. For this reason, the board | substrate protruding electrode 4 and the element protruding electrode 5 are joined so that it may mutually mesh | engage, joining strength increases further, and joining quality improves further.

図６は、実施の形態に係る基板突起電極４と素子突起電極５との他の寸法関係を示す模式断面図である。基板接合面６と素子接合面７との形状及びサイズとは、同一にしながら、基板突起電極４の高さと、素子突起電極５の高さとを異ならせてもよい。素子突起電極５は基板突起電極４よりも低く、基板突起電極４の高さは、例えば１５μｍであり、素子突起電極５の高さは、例えば８μｍである。素子突起電極５の高さは、例えば５μｍに低くしてもよい。   FIG. 6 is a schematic cross-sectional view showing another dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. While the shape and size of the substrate bonding surface 6 and the element bonding surface 7 are the same, the height of the substrate protruding electrode 4 and the height of the element protruding electrode 5 may be different. The element protruding electrode 5 is lower than the substrate protruding electrode 4, the height of the substrate protruding electrode 4 is, for example, 15 μm, and the height of the element protruding electrode 5 is, for example, 8 μm. The height of the element protruding electrode 5 may be as low as 5 μm, for example.

このように構成すると、素子突起電極５を低く構成するので、Ａｕの使用量を削減してコストを低減することができる。また、素子突起電極５が低くなるので、高さバラツキが低減し、接合品質を安定化することができる。   If comprised in this way, since the element protrusion electrode 5 is comprised low, the usage-amount of Au can be reduced and cost can be reduced. Further, since the element protruding electrode 5 is lowered, the height variation can be reduced and the bonding quality can be stabilized.

図７は、実施の形態に係る基板突起電極４と素子突起電極５とのさらに他の寸法関係を示す模式断面図である。基板接合面６と素子接合面７とを同一の形状及びサイズにすると、接合ズレが発生した場合、基板突起電極４の一端が、素子突起電極５の一端からはみ出し、素子突起電極５の他端が、基板突起電極４の他端からはみ出した状態で、圧着接合される。素子突起電極５の一端からはみ出した基板突起電極４の一端と、基板突起電極４の他端からはみ出した素子突起電極５の他端とは、圧着されないことになるが、素子突起電極５の一端からはみ出した基板突起電極４の一端は、半導体素子３のインターポーザ基板２側の表面に接触せず、また、基板突起電極４の他端からはみ出した素子突起電極５の他端は、インターポーザ基板２の半導体素子３側の表面に接触しないように構成されている。このため、バンプがチップの表面に接触することによる品質低下を回避することができる。   FIG. 7 is a schematic cross-sectional view showing still another dimensional relationship between the substrate protruding electrode 4 and the element protruding electrode 5 according to the embodiment. If the substrate bonding surface 6 and the element bonding surface 7 have the same shape and size, when bonding deviation occurs, one end of the substrate protruding electrode 4 protrudes from one end of the element protruding electrode 5 and the other end of the element protruding electrode 5. However, in a state of protruding from the other end of the substrate protruding electrode 4, pressure bonding is performed. The one end of the substrate projection electrode 4 protruding from one end of the element projection electrode 5 and the other end of the element projection electrode 5 protruding from the other end of the substrate projection electrode 4 are not crimped. One end of the substrate protruding electrode 4 protruding from the interposer substrate 2 side of the semiconductor element 3 does not contact the surface of the semiconductor element 3, and the other end of the element protruding electrode 5 protruding from the other end of the substrate protruding electrode 4 is connected to the interposer substrate 2. It is comprised so that it may not contact the surface of the semiconductor element 3 side. For this reason, it is possible to avoid quality degradation due to bumps coming into contact with the surface of the chip.

なお、上述した実施形態では、図２，４，５からも明らかなように、インタポーザ基板２側又は半導体素子３側から透視した場合に、素子突起電極４の面積が基板突起電極５の面積よりも大きくなっている。また、例えば図１に示すような半導体装置を側面から見た側面視において、図２の図面上下方向と図面左右方向とのいずれでも、素子突起電極５の素子接合面の長さ（Ｌ１，Ｌ２）が、基板突起電極４の基板接合面の長さ（Ｗ１，Ｗ２）よりも長くなっている。そして、同様に側面視において、図４，５の図面左右方向では、素子突起電極５の素子接合面の長さが、基板突起電極４の基板接合面の長さよりも長くなっている。   In the above-described embodiment, as is apparent from FIGS. 2, 4, and 5, the area of the element protruding electrode 4 is larger than the area of the substrate protruding electrode 5 when viewed from the interposer substrate 2 side or the semiconductor element 3 side. Is also getting bigger. Further, for example, when the semiconductor device as shown in FIG. 1 is viewed from the side, the length (L1, L2) of the element bonding surface of the element protruding electrode 5 in either the vertical direction or the horizontal direction in FIG. ) Is longer than the length (W1, W2) of the substrate bonding surface of the substrate protruding electrode 4. Similarly, in side view, the length of the element bonding surface of the element protruding electrode 5 is longer than the length of the substrate bonding surface of the substrate protruding electrode 4 in the lateral direction of FIGS.

本発明は上述した実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能である。すなわち、請求項に示した範囲で適宜変更した技術的手段を組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。例えば、上記実施形態では、いずれも突起電極の平面形状が四角形のものを示したが、楕円形状や丸形状のものでも良い。   The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention. For example, in the above-described embodiments, the planar shape of the protruding electrode is square, but an elliptical shape or a round shape may be used.

本発明は、フィルム基板に実装されてシリコンにより構成されたインタポーザ基板と、液晶を駆動するためにインタポーザ基板に実装された半導体素子とを備えたハイブリッドＳＯＦに適用することができる。   The present invention can be applied to a hybrid SOF including an interposer substrate that is mounted on a film substrate and made of silicon, and a semiconductor element that is mounted on the interposer substrate to drive a liquid crystal.

実施の形態に係る半導体装置の構成を示す模式断面図である。1 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. 実施の形態に係る基板突起電極の基板接合面と素子突起電極の素子接合面との寸法関係を示す模式断面図である。It is a schematic cross section showing the dimensional relationship between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment. 実施の形態に係る基板突起電極と素子突起電極との寸法関係を示す模式断面図である。It is a schematic cross section which shows the dimensional relationship of the board | substrate protruding electrode and element protruding electrode which concern on embodiment. 実施の形態に係る基板突起電極の基板接合面と素子突起電極の素子接合面との他の寸法関係を示す模式断面図である。It is a schematic cross section showing other dimensional relationships between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment. 実施の形態に係る基板突起電極の基板接合面と素子突起電極の素子接合面とのさらに他の寸法関係を示す模式断面図である。FIG. 10 is a schematic cross-sectional view showing still another dimensional relationship between the substrate bonding surface of the substrate protruding electrode and the element bonding surface of the element protruding electrode according to the embodiment. 実施の形態に係る基板突起電極と素子突起電極との他の寸法関係を示す模式断面図である。It is a schematic cross section which shows the other dimensional relationship of the board | substrate protruding electrode which concerns on embodiment, and an element protruding electrode. 実施の形態に係る基板突起電極と素子突起電極とのさらに他の寸法関係を示す模式断面図である。FIG. 10 is a schematic cross-sectional view showing still another dimensional relationship between the substrate protruding electrode and the element protruding electrode according to the embodiment. 従来の半導体装置の構成を示す模式断面図である。It is a schematic cross section which shows the structure of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置
２ インターポーザ基板
３ 半導体素子
４ 基板突起電極
５ 素子突起電極
６ 基板接合面
７ 素子接合面
８ フィルム基板
９ 封止樹脂
１０ 突起電極
１１ 配線パターン
１２ 孔 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Interposer substrate 3 Semiconductor element 4 Substrate protrusion electrode 5 Element protrusion electrode 6 Substrate joint surface 7 Element joint surface 8 Film substrate 9 Sealing resin 10 Protrusion electrode 11 Wiring pattern 12 Hole

Claims (16)

実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、
前記素子突起電極の素子接合面の面積が、前記基板突起電極の基板接合面の面積よりも大きいことを特徴とする半導体装置。 An interposer substrate mounted on a mounting substrate and made of a semiconductor; and a semiconductor element mounted on the interposer substrate, the interposer substrate having a substrate protruding electrode formed on the semiconductor element side, and the semiconductor In a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
The area of the element bonding surface of the element protruding electrode is larger than the area of the substrate bonding surface of the substrate protruding electrode. 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、
前記インタポーザ基板側又は前記半導体素子側から透視した場合に、前記素子突起電極の面積が前記基板突起電極の面積よりも大きいことを特徴とする半導体装置。 An interposer substrate mounted on a mounting substrate and made of a semiconductor; and a semiconductor element mounted on the interposer substrate, the interposer substrate having a substrate protruding electrode formed on the semiconductor element side, and the semiconductor In a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
A semiconductor device, wherein an area of the element protruding electrode is larger than an area of the substrate protruding electrode when seen through from the interposer substrate side or the semiconductor element side. 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、
一側面視で、前記素子突起電極の素子接合面の長さが、前記基板突起電極の基板接合面の長さよりも長いことを特徴とする半導体装置。 An interposer substrate mounted on a mounting substrate and made of a semiconductor; and a semiconductor element mounted on the interposer substrate, the interposer substrate having a substrate protruding electrode formed on the semiconductor element side, and the semiconductor In a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
In one aspect, the length of the element bonding surface of the element protruding electrode is longer than the length of the substrate bonding surface of the substrate protruding electrode. 前記素子接合面及び前記基板接合面は、長方形状をしており、
前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置されており、
前記素子接合面の短軸方向の幅が、前記基板接合面の短軸方向の幅よりも広い請求項１記載の半導体装置。 The element bonding surface and the substrate bonding surface have a rectangular shape,
The major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other,
The semiconductor device according to claim 1, wherein a width of the element bonding surface in the minor axis direction is wider than a width of the substrate bonding surface in the minor axis direction. 前記素子接合面の長軸方向の長さと前記基板接合面の長軸方向の長さとが、互いに等しい請求項４記載の半導体装置。   The semiconductor device according to claim 4, wherein a length in the major axis direction of the element bonding surface and a length in the major axis direction of the substrate bonding surface are equal to each other. 前記基板接合面の長軸方向の長さは、前記素子接合面の長軸方向の長さよりも長い請求項４記載の半導体装置。   The semiconductor device according to claim 4, wherein a length of the substrate bonding surface in a major axis direction is longer than a length of the element bonding surface in a major axis direction. 前記インタポーザ基板に垂直な方向から見て、前記素子接合面は、前記基板接合面を囲むように配置されており、
前記素子接合面及び前記基板接合面は、長方形状をしており、
前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置されており、
前記インタポーザ基板に垂直な方向から見て、前記素子接合面の一辺は、前記基板接合面の対応する一辺から５〜１０μｍ離れて配置されている請求項１または４に記載の半導体装置。 When viewed from a direction perpendicular to the interposer substrate, the element bonding surface is disposed so as to surround the substrate bonding surface,
The element bonding surface and the substrate bonding surface have a rectangular shape,
The major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other,
5. The semiconductor device according to claim 1, wherein one side of the element bonding surface is disposed at a distance of 5 to 10 μm from a corresponding side of the substrate bonding surface when viewed from a direction perpendicular to the interposer substrate. 前記素子突起電極の高さと前記基板突起電極の高さとが、互いに異なっている請求項１から７の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a height of the element protruding electrode and a height of the substrate protruding electrode are different from each other. 前記素子突起電極の高さが、前記基板突起電極の高さよりも低い請求項１から８の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a height of the element protruding electrode is lower than a height of the substrate protruding electrode. 前記素子突起電極の高さが、５〜８μｍである請求項１から９の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a height of the element protruding electrode is 5 to 8 μm. 前記基板突起電極の高さが、１０〜１５μｍである請求項１から１０の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a height of the substrate protruding electrode is 10 to 15 μm. 前記基板突起電極は、前記素子突起電極よりも硬度が高い請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the substrate protruding electrode has a hardness higher than that of the element protruding electrode. 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する端子を有することを特徴とする半導体装置。   An interposer substrate mounted on a mounting substrate and made of a semiconductor; and a semiconductor element mounted on the interposer substrate, the interposer substrate having a substrate protruding electrode formed on the semiconductor element side, and the semiconductor The element has a terminal to be joined to the substrate protruding electrode. 前記端子は、アルミニウムによって構成され、
前記基板突起電極は、金によって構成される請求項１３記載の半導体装置。 The terminal is made of aluminum,
The semiconductor device according to claim 13, wherein the substrate protruding electrode is made of gold. 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、
前記素子突起電極の高さと前記基板突起電極の高さとが、互いに異なっていることを特徴とする半導体装置。 An interposer substrate mounted on a mounting substrate and made of a semiconductor; and a semiconductor element mounted on the interposer substrate, the interposer substrate having a substrate protruding electrode formed on the semiconductor element side, and the semiconductor In a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
The semiconductor device according to claim 1, wherein the height of the element protruding electrode and the height of the substrate protruding electrode are different from each other. 実装基板に実装されて半導体により構成されたインタポーザ基板と、前記インタポーザ基板に実装された半導体素子とを備え、前記インタポーザ基板は、前記半導体素子側に形成された基板突起電極を有し、前記半導体素子は、前記基板突起電極と接合する素子突起電極を有する半導体装置において、
前記素子突起電極の素子接合面及び前記基板突起電極の基板接合面は、長方形状をしており、
前記素子接合面及び前記基板接合面のそれぞれの長軸は、互いに平行に配置されており、
前記素子接合面の短軸方向の幅が、前記基板接合面の短軸方向の幅よりも広く、
前記基板接合面の長軸方向の長さは、前記素子接合面の長軸方向の長さよりも長いことを特徴とする半導体装置。 An interposer substrate mounted on a mounting substrate and made of a semiconductor; and a semiconductor element mounted on the interposer substrate, the interposer substrate having a substrate protruding electrode formed on the semiconductor element side, and the semiconductor In a semiconductor device having an element protruding electrode bonded to the substrate protruding electrode,
The element bonding surface of the element protruding electrode and the substrate bonding surface of the substrate protruding electrode have a rectangular shape,
The major axes of the element bonding surface and the substrate bonding surface are arranged in parallel to each other,
The width in the minor axis direction of the element bonding surface is wider than the width in the minor axis direction of the substrate bonding surface,
A length of the substrate bonding surface in the major axis direction is longer than a length of the element bonding surface in the major axis direction.
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