WO2008018870A1 - Embase de stockage de charges intégrée et structure de découplage large bande incorporée pour circuits intégrés - Google Patents

Embase de stockage de charges intégrée et structure de découplage large bande incorporée pour circuits intégrés Download PDF

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Publication number
WO2008018870A1
WO2008018870A1 PCT/US2006/030986 US2006030986W WO2008018870A1 WO 2008018870 A1 WO2008018870 A1 WO 2008018870A1 US 2006030986 W US2006030986 W US 2006030986W WO 2008018870 A1 WO2008018870 A1 WO 2008018870A1
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Prior art keywords
signal absorption
capacitor
conductive
conductive layers
absorption ring
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PCT/US2006/030986
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English (en)
Inventor
Ronald Barnett
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Geomat Insights, Llc
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Priority to PCT/US2006/030986 priority Critical patent/WO2008018870A1/fr
Publication of WO2008018870A1 publication Critical patent/WO2008018870A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/35—Feed-through capacitors or anti-noise capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/255—Means for correcting the capacitance value
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0233—Filters, inductors or a magnetic substance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0234—Resistors or by disposing resistive or lossy substances in or near power planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/20—Arrangements for preventing discharge from edges of electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/22—Electrostatic or magnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0263—Details about a collection of particles
    • H05K2201/0269—Non-uniform distribution or concentration of particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08—Magnetic details
    • H05K2201/083—Magnetic materials
    • H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09254—Branched layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts

Definitions

  • capacitors are not capable of bypassing both low and high frequencies.
  • the upper frequency is limited by internal resonances in the capacitors themselves. This upper frequency limit can be increased by reducing the capacitance. However as the capacitance decreases so does its admittance, and hence its ability to shunt low frequencies.
  • the most common decoupling network solution consists of a number of strategically placed capacitors of different values connected in parallel combined with small appropriately placed series damping resistors.
  • a single-element capacitor that is integrated into the circuit board that could distribute power, as a power plane, while providing wide-band, resonant free, high shunt admittance everywhere on the circuit board surface.
  • Such a buried capacitor could eliminate most, if not all, discrete bypass capacitors and their associated dampening resistors and ferrite beads.
  • a large capacitor spread across a printed circuit board or other substrate could provide shunt admittance large enough that other bypass elements would not be necessary.
  • internal reflections off the finite boundaries of such a capacitor induce many resonances in its admittance, destroying the decoupling characteristics of the capacitor at its parallel-resonant frequencies, where its admittance is relatively small.
  • Resonances can be sorted into two types, parallel resonances where the admittance is small and the decoupling is poor, and series resonances where the admittance is large and the decoupling is excellent.
  • An additional requirement is to provide sufficient charge storage electrically close to the devices requiring it.
  • the capacitor must be placed physically close to the devices needing to be decoupled, thereby providing low external inductance and series resistance between the physical charge storage and the circuitry requiring the charge.
  • using several layers of a circuit board to create a whole board integral capacitor provides charge physically close to the components requiring charge, it does not solve the fundamental resonance problems that limit the upper frequency use of the capacitor.
  • a parallel plate capacitor This capacitor consists of parallel electrically conductive plates separated by free space or a dielectric medium. Resonance, in general, occurs when reinforcing in-phase feedback is provided. In this case the capacitor has a resonance at any wavelength ⁇ where constructive feedback occurs. This constructive feedback causes the resonances that limit the upper frequency use of a parallel plate capacitor. The feedback is created by repeated, reinforcing, multiple, low loss edge reflections of laterally flowing Transverse Electric Magnetic (TEM) waves between the parallel plates. These parasitic laterally flowing waves are initiated whenever a pulse of charge is added to or taken from the capacitor. They are initiated at the point in the capacitor where the charge transfer occurs.
  • TEM Transverse Electric Magnetic
  • Each wave travels laterally from its initiation point until it encounters one of the capacitor's highly reflective edges, whereupon the reflected wave continues traveling in the opposite direction until it encounters another reflective edge.
  • the wave continues traveling, bouncing back and forth between edges, creating resonances whenever the round trip for the wave is in phase. These resonances are called "N* ⁇ /2" resonances because they occur when the distance between reflective edges is a multiple number (N) of half (1/2) wavelengths ( ⁇ ).
  • the upper frequency limit to the capacitor gets lower and lower as the boundary conditions, within the capacitor, which determine its internal resonances, get electrically further apart. So, once again, while converting several of the board's layers to one large integral capacitor solves the problem of the stored charge being physically far from circuits requiring the charge, it does not address the fundamental self resonance problems that result from attempting to use a single large capacitor physically big enough to be close to all board components and electrically large enough to bypass the lowest frequencies of the wide band circuitry. As matter of fact, a large in-board capacitor promotes coupling between circuit elements at the frequencies where capacitor resonances occur such that a by passed component sees a parallel resonance where it is attached to the large buried capacitor.
  • a need exists for a charge delivery source implemented integral to an integrated circuit device such as the integrated circuit die, the integrated circuit package, the printed circuit board, or the circuit substrate
  • an integrated circuit device such as the integrated circuit die, the integrated circuit package, the printed circuit board, or the circuit substrate
  • the present invention is a capacitive structure and technique for allowing near- instantaneous charge transport and reliable, wide-band RF ground paths in integrated circuit devices such as integrated circuit dies, integrated circuit packages, printed circuit boards, and electronic circuit substrates.
  • a basic premise of this invention is that the upper frequency limit of a capacitor can be eliminated or greatly extended by any and all means of suppressing these lateral resonances by implementation of a loss mechanism that does not substantially increase the Effective Series Resistance (ESR) of the capacitor. It is appreciated that there are many ways to do this.
  • the concept of "perimeter absorption” is introduced to facilitate the creation of integrated structures that absorb the capacitor's internal laterally flowing Electro-Magnetic (E&M) waves.
  • E&M Electro-Magnetic
  • the waves will usually be a subclass of these E&M waves called Transverse Electric Magnetic (TEM) waves, and so throughout this document the laterally flowing waves will be referred to as TEM waves without lack of generality.
  • TEM waves Transverse Electric Magnetic
  • a lossy signal absorption ring structure is implemented, preferably at the capacitor's perimeter, to eliminate or greatly reduce the edge reflection and thereby eliminate or greatly reduce the resonances that determine the upper frequency limit of the capacitor's use.
  • the perimeter loss function can be accomplished by any and all combination of the four absorptive modes: conductive loss, dielectric loss, magnetic loss, and radiative loss. Also, the perimeter loss function can be accomplished using a continuous or discontinuous ring of absorptive material. The lossy material can be patterned in discontinuous pieces.
  • the lossy material is formed as a continuous ring, it in fact can be implemented as discrete lossy chunks scattered in a pattern to obtain the desired perimeter loss function.
  • the idea is to absorb the laterally flowing waves without impeding the supply of charge to the components the device is designed to supply charge for, and any means of achieving the absorptionis acceptable. This includes the following methods but does not preclude other methods: adding or taking away material, or converting the properties of materials so that they selectively become absorptive in a pattern that absorbs the laterally flowing waves while minimizing any restriction of the charge flow vertically out of or into the charge storage device.
  • This pattern could be anywhere within the volume of the charge storage device and is not limited to the physical perimeter of a layer.
  • the invention includes all methods, and materials of obtain a loss pattern within a capacitor that inhibits the lateral flowing waves induced within a capacitor whenever charge is added or removed while minimizing the restriction of charge transport in and out of the capacitor itself.
  • the exact loss pattern can also be tailored for specific applications and specific placement of parts. Additional isolation can be provided between individual circuits by implementing a respective signal absorption ring around each circuit that needs additional isolation
  • an integrated circuit device includes an integral set of high- dielectric layers interleaved with highly-conductive layers, with at least one signal absorption ring implemented on or in at least one of the conductive and/or dielectric layers.
  • the signal absorption ring operates to dampen lateral traveling waves generated in the structure so as to eliminate or at least substantially mitigate the resonant frequency limitations of the plate capacitor formed by the structure.
  • charge storage basement The structure of integral charge storage layers with signal absorption ring(s) (termed herein “charge storage basement” or “CSB”) provides near-instantaneous charge delivery and good wide-band RF shorts, that is high wide-band shunt admittance , at any point on the surface of any substrate containing a CSB.
  • a "good” RF short (1) is non-resonant (i.e. does not become inductive or open at certain frequencies), (2) has low RF impedance, and 3) the charge is stored physically and electrically close to the capacitor terminal where the charge is to be accessed.
  • CSB implementation is not limited to a "whole board/substrate" use, and that it can also be implemented piece meal in any area/area's of the substrate desired. In this partial board area implementation all of the virtues of the CSB are retained in the area's in which it is implemented. Also, it is possible to implement a CSB to distribute power from one source in one section of the substrate, and implement a second CSB to distribute power from another source in the same section or an entirely different section. This may be done, for example to distribute the several voltage supplies frequently required in today's diverse circuitry.
  • At least one of the conductive layers is connected to a power source and operates as a power plane, while at least one other of the conductive layers is connected to the circuit/chip/board ground and operates as a ground plane.
  • the signal absorption ring(s) are preferably implemented at the outside edge of the layer(s) and/or circuitry to be isolated and surrounds the internal useful area of the power and/or ground layer(s) where charge storage and power supply decoupling takes place. Ideally the signal absorption ring(s) absorb all or most of the energy of any waves generated within the CSB, thereby eliminating or substantially mitigating the ⁇ / ⁇ /2 resonances that would otherwise limit the upper frequency of the buried capacitor.
  • FIG. 1 is a perspective view of a conventional parallel plate capacitor along with a corresponding graph of the current distribution for the lowest-order resonance of the capacitor;
  • FIG. 2A is a side cross-sectional view of a capacitor implemented in accordance with the principles of the invention;
  • FIG. 2B is a top plan view of at least one of the layers of the capacitor of FIG. 2A in which a perimeter absorption ring is illustrated;
  • FIG. 3 is a side cross-sectional view of a an integrated circuit device illustrating an example general application of the invention
  • FIGS. 4A 1 4B, and 4C are plan views illustrating example layouts for a CSB layer that implements a continuous signal absorption ring;
  • FIG. 4D is a plan view illustrating an example layout for a CSB layer that implements a signal absorption mechanism implemented using an alternative pattern
  • FIG. 4E is a plan view illustrating an example layout for a CSB layer that implements a signal absorption mechanism implemented using another alternative pattern
  • FIG. 5A is a plot of a preferred resistive profile for an example signal absorption ring
  • FIG. 5B is the corresponding waveform diagram illustrating the effect of the signal absorption ring characterized by the resistive profile shown in FIG. 4A on lateral waves generated in the CSB;
  • FIG. 6A is a plot of a preferred resistive profile for another example signal absorption ring
  • FIG. 6B is the corresponding waveform diagram illustrating the effect of the signal absorption ring characterized by the resistive profile shown in FIG. 5A on lateral waves generated in the CSB;
  • FIG. 7A is a plot of resistance versus distance illustrating a discrete version of the preferred resistive profile of FIG. 5A for a signal absorption ring on lateral waves generated in the CSB;
  • FIG. 7B is the corresponding waveform diagram illustrating the effect of the signal absorption ring characterized by the resistive profile shown in FIG. 7A;
  • FIG. 8A is a plot of resistance versus distance illustrating a resistive profile for a signal absorption ring having a single resistive step
  • F(G. 8B is the corresponding waveform diagram illustrating the effect of the signal absorption ring characterized by the resistive profile shown in FIG. 8A;
  • FIGS. 9A - 91 are cross-sectional side views of CSB layers implementing signal absorption rings with corresponding cross-sectional top views of portions of the signal absorption rings;
  • FIG. 1OA is a cross-sectional side view of a CSB with a signal absorption ring implemented on a top surface of one of the conductive layers;
  • FIG. 1OB is a cross-sectional side view of a CSB with a signal absorption ring implemented on a top surface of one of the conductive layers and on a bottom surface of one of the conductive layers;
  • FIG. 10C is a cross-sectional side view of a CSB with a signal absorption ring implemented on one surface of a dielectric layer;
  • FIG. 1OD is a cross-sectional side view of a CSB with a signal absorption ring implemented on both surfaces of the dielectric layer;
  • FIG. 11 A is a perspective view of an integrated circuit device implementing a
  • FIG. 11B is a side cross-sectional view of the integrated circuit device of FIG. 11 B;
  • FIG. 12 is a side cross-sectional view of an integrated circuit device implementing a CSB in accordance with the invention and which allows circuit isolation;
  • FIG. 13A is a side cross-sectional view of a single-sided integrated circuit device implementing a CSB in accordance with the invention and which allows circuit isolation using different power sources;
  • FIG. 13B is a side cross-sectional view of a double-sided integrated circuit device implementing a CSB in accordance with the invention and which allows circuit isolation using different power sources;
  • FIG. 14 is a plan view of a CSB layer implemented according to the invention to allow both signal isolation and signal protection with an exploded view of a section of a signal absorption ring;
  • FIGS. 15A-15D are exploded plan views of sections of various signal absorption rings illustrating various embodiments for achieving both isolation and protection of components connected inside and outside the signal absorption rings;
  • FIG. 16 is a side cross-sectional view of an integrated circuit illustrating a variation of the CSB technique for achieving isolation of circuits
  • FIG. 17 is a side cross-sectional view of an integrated circuit illustrating an alternative variation of the CSB technique for achieving isolation of circuits
  • FIG. 18 is a side cross-sectional view of an integrated circuit illustrating another variation of the CSB technique for achieving isolation of circuits;
  • FIG. 19 is a side cross-sectional view of an integrated circuit package implemented according to the invention.
  • FIG. 20 is an operational flowchart illustrating an exemplary method for providing charge to an electronic component.
  • FIG. 21 is an operational flowchart illustrating a method for fabricating a CSB in accordance with the invention.
  • the structure 2 is formed with a dielectric 6 sandwiched between two conductive plates 4 and 8 at different voltage potentials (e.g., V C c and ground, respectively).
  • the first resonance, fi occurs at the frequency where the capacitor is half a wavelength ( ⁇ /2) long.
  • the invention requires implementation of a signal absorption mechanism that operates to dampen or absorb the laterally flowing waves in the capacitor without impeding the supply of charge to the components the device is designed to supply charge for.
  • any means of achieving the dampening or absorption is acceptable, including all methods and/or materials of generating a loss function within the capacitor that inhibits the lateral flowing waves induced within the capacitor whenever charge is added to or removed from the capacitor while minimizing the restriction of charge transport in and out of the capacitor itself.
  • FIG. 2A is a side cross-sectional view
  • FIG. 2B is a top plan view, of a preferred embodiment of a capacitor 20 implemented in accordance with the principles of the invention.
  • the invention is a capacitor 20 having at least two conductive layers 14, 18, each interleaved by a dielectric layer 16. At least one layer 14, 16, 18 is implemented with a signal absorption mechanism 25a, 25b, and/or 25c for dampening laterally flowing Transverse Electric Magnetic (TEM) waves between the conductive layers 14, 16.
  • TEM Transverse Electric Magnetic
  • the signal absorption mechanism 25a, 25b, and/or 25c introduces loss into the capacitor 20 in the form of one or more of resistive loss, conductive loss, dielectric loss, magnetic loss, and radiation loss.
  • the signal absorption mechanism 25a, 25b, and/or 25c is a signal absorption ring (shown as 32a in FIG. 2B) formed at the outer perimeter of one or more of the capacitor layers 14, 16, 18 (shown as 30a in FIG. 2B) which bounds a non- absorptive area 24a, 24b, and/or 24c (shown as 34a in FIG. 2B) to which the capacitor terminals are coupled.
  • a signal absorption ring refers to a generally circumferential discrete or continuous boundary of any shape and size, wherein the boundary implements a signal absorption function and includes a non-absorptive area within the circumference of the boundary.
  • FIG. 3 is a side cross-sectional view of a preferred general application which utilizes the capacitor of the invention.
  • the capacitor is essentially a buried capacitor (herein called a "charge storage basement", or "CSB") 20 for an integrated circuit device 10 comprising an electrical component 11 such as an integrated circuit, a signal interconnect stack 12, and the CSB 20 of the invention.
  • the signal interconnect stack 12 includes a plurality of interleaved conductive and dielectric layers that route signals between terminals of electronic components (e.g., component 11) mounted thereon.
  • the CSB 20 comprises at least two conductive layers 14 and 18 separated by a dielectric layer 16 wherein one or more of the two conductive layers 14, 18 and dielectric layer 16 implements a respective signal absorption ring 25a, 25b, 25c that bounds a corresponding respective non-absorptive area 24a, 24b, 24c on the respective layer 14, 16, 18.
  • One of the conductive layers 14 is connected to a power source 19 and serves as a power plane, and the other conductive layer is 18 is connected to ground 17 and serves as a ground plane.
  • the electronic component 11 connects to the power plane 14 by way of a conductive path 13a through the signal interconnect stack 12 (e.g. by way of vias and traces), and to the ground plane 18 by way of an alternate conductive path 13b.
  • FIGS. 4A, 4B, and 4C are plan views illustrating example layouts for a CSB layer that implements a signal absorption ring. As illustrated, in each layout, the signal absorption ring bounds a non-absorptive (i.e., substantially non-lossy) area of the layer on which it is implemented.
  • a non-absorptive i.e., substantially non-lossy
  • the signal absorption ring 32a is implemented at the outer perimeter of the layer 30a and surrounds a non-absorptive area 34a.
  • the signal absorption ring 32a attenuates the resonances initiated in the non-absorptive area 34a by reducing the reflections at the boundary edges of the substrate or board by means discussed hereinafter with respect to FIGS. 9A through 9I.
  • implementation of the signal absorption ring is not limited to the outer perimeter of the layer, but can be implemented anywhere on the CSB layer.
  • one or more signal absorption rings 36b, 38b are implemented, but not necessarily at the perimeter of the layer 30b.
  • FIG. 4C illustrates a layout that implements a signal absorption ring 32c at the outer perimeter of the layer 30c and one or more signal absorption rings 36c, 38c, 38d implemented within the area 34c bounded by the first signal absorption ring 32c.
  • the inner signal absorption rings 36c, 38c, 38d may be implemented, for example, to provide isolation between components connected within the respective inner bounded areas 37c, 39c, 39d from components connected to the first bounded area 34c outside of the respective inner signal absorption rings 36c, 38c, 38d or within other bounded areas, as discussed hereinafter.
  • the signal absorption mechanism is implemented as a signal absorption ring according to the definition given above, the signal absorption mechanism used may not even be in the form of a "ring".
  • the signal absorption mechanism may be implemented using a pattern that does not form a circumferential boundary. For example, FIG.
  • FIG. 4D illustrates a layout of a CSB layer 3Od that implements a plurality of signal absorption areas 32d discretely situated around the edges of the capacitor. Each of the signal absorption areas 32d operates to dampen laterally traveling waves generated in the non-absorptive area of the CSB.
  • FIG. 4E illustrates a layout for a CSB layer 3Oe that implements a plurality of signal absorption areas 32e according to a "waffle" pattern.
  • the layout pattern chosen may vary from implementation to implementation and should be designed to meet the frequency requirements of the particular circuits that the CSB is to supply charge to.
  • a given signal absorption ring 32a, 32c, 36b, 38b, 36c, 38c, 38d or signal absorption mechanism 32d, 32e may be implemented in a number of ways, as discussed in detail hereinafter with respect to FIGS. 9A through 91.
  • common to all implementations is the resulting signal dampening property that dampens/prevents reflections of signals flowing laterally within the CSB. Inherent in this property is that resistive discontinuities should be avoided or minimized as much as possible, and the resistive profile of the signal absorption ring preferably generally increase as signals travel into the ring.
  • FIG. 5A is a plot of resistance versus distance illustrating one example of a preferred resistive profile for a signal absorption ring (for example 32a of layer 30a shown in FIG. 4A), and FIG. 5B is the corresponding waveform diagram illustrating the effect of the signal absorption ring on lateral waves generated in the non-absorptive area (for example 34a of FIG. 4A) of the CSB.
  • the resistive profile is a continuous exponential function that exponentially increases in resistivity the further the wave travels into the signal absorption ring (from point to A to point B), thereby dampening the wave preferably to the point of extinguishing it.
  • FIG. 6A is a plot of resistance versus distance illustrating another example of a preferred resistive profile for a signal absorption ring (for example 32a of the CBS layer 30a shown in FIG. 4A), and FIG. 6B is the corresponding waveform diagram illustrating the effect of the signal absorption ring on lateral waves generated in the non-absorptive area (for example 34a of FIG. 4A) of the CSB.
  • the resistive profile is a continuous linear function that linearly increases in resistivity the further the wave travels into the signal absorption ring (from point to A to point B), again, preferably dampening the wave to the point of extinction.
  • the rate of dampening is dependent on the slope of the resistive profile line.
  • FIG. 7A is a plot of resistance versus distance illustrating a discrete version of the preferred resistive profile of FIG.
  • FIG. 7B is the corresponding waveform diagram illustrating the effect of the signal absorption ring on lateral waves generated in the non-absorptive area of the CSB.
  • the resistive profile is a discrete exponential function having small incremental steps that increase in resistivity the further the wave travels into the signal absorption ring (from point A to point B), preferably dampening the wave to the point of practical extinction.
  • it is preferred to implement a discrete resistive profile function using multiple increments (in terms of electrical characteristics) a signal absorption ring can in fact actually be implemented using a single absorptive step.
  • FIG. 8A is a plot of resistance versus distance illustrating a resistive profile comprising a single step function for a signal absorption ring
  • FIG. 8B is the corresponding waveform diagram illustrating the effect of the signal absorption ring on lateral waves generated in the non-absorptive area of the CSB. As shown in this example, waves traveling into the signal absorption ring are still dampened at an exponential rate of decay.
  • FIGS. 9A through 9I illustrate some of the many techniques, including adding lossy material to a CSB layer or altering the characteristics of the CSB layer itself to become lossy in the area of the signal absorption ring.
  • Various methods for introducing lossy signal absorption mechanisms include: a. Adding lossy material 81 to the layer 80, as shown in FIG. 9A. Depending on the underlying layer 80 (conductive or dielectric), the lossy material 81 may introduce resistive, conductive, magnetic, dielectric, and/or radiation loss.
  • the lossy material 81 can be characterized by a resistive profile that is either a continuous function (as shown in FIGS.
  • the lossy material 81 may be formed by "growing" a resistive oxide on the conductive layer(s), printing, laminating, or otherwise applying lossy material to achieve the desired resistive profile.
  • the lossy material 83 may introduce resistive, conductive, magnetic, dielectric, and/or radiation loss.
  • the lossy material 83 can be characterized by a resistive profile that is either a continuous function (as shown in FIGS. 5A and 6A) or can be a discrete function (as shown in FIGS.
  • the lossy material 83 may be formed by "growing" a resistive oxide on the conductive layer(s), printing, laminating, or otherwise applying lossy material to achieve the desired resistive profile. c. Adding lossy material 85 to the layer 84, as shown in FIG. 9C. Depending on the underlying layer 84 (conductive or dielectric), the lossy material 85 may introduce resistive, conductive, magnetic, dielectric, and/or radiation loss.
  • the lossy material 85 can be characterized by a resistive profile that is either a continuous function (as shown in FiGS. 5A and 6A) or can be a discrete function (as shown in FIGS.
  • the lossy material 85 may be formed by "growing" a resistive oxide on the conductive layer(s), printing, laminating, or otherwise applying lossy material to achieve the desired resistive profile.
  • d Altering the composition of the material of the layer 86 in the region of the signal absorption ring, as shown in FIG. 9D, for example by adding impurities with increasing density of lossy material to achieve the desired resistive profile.
  • e Gradually thinning the material of the layer(s) 87 to achieve higher resistivity, as shown in FIG. 9E. f.
  • the signal absorption ring 94 is etched or otherwise formed with a fractal pattern that begins near the inner perimeter of the signal absorption ring 94 and gradually increases as it approaches the outer perimeter of the signal absorption ring 94.
  • the etched lines 96 on the conductive layer 93 operate as an electrical open or a high- resistance barrier, and therefore operate to increase the resistivity of the conductive material as the number of etched lines 96 is increased. Etched fractal patterns other than that illustrated may also achieve similar results. h. Creating holes 100 in a layer 97 of material on the surface of the layer(s) 96 in a pattern within the signal absorption ring 98 that becomes more dense with holes (or other patterns) for higher resistivity, as shown in FIG. 9H.
  • the holes 100 operate as an electrical open, and therefore increase the resistivity of the conductive material as the number of holes 100 is increased.
  • the number of holes 100 is few near the inner perimeter of the signal absorption ring 98 and gradually increases as it approaches the outer perimeter of the signal absorption ring 98.
  • a signal absorption ring should have at least approximately 5 dB of loss from the inner perimeter of the ring to the outer perimeter of the ring over the potential resonant frequencies. In general, this means to set 5 dB of loss at the first resonant frequency, because as the frequency increases, the loss is greater.
  • a 5 dB signal absorption ring loss corresponds to approximately 10 dB of return loss, which is known to dampen out the resonance.
  • FIG. 10A illustrates a CSB 110a with a signal absorption ring 115a implemented according to the method shown in FIG. 9A on the inside surface (facing the dielectric 112) of one of the conductive layers 111a.
  • a resistive material 114a is formed on the conductive layer 111a within the area defined by the signal absorption ring 115a.
  • FIG. 10B shows a CSB 110b with a signal absorption ring 115b implemented according to the method shown in FIG. 9A on the inside surfaces (facing the dielectric 112b) of both of the conductive layers 111b and 113b.
  • a resistive material 114b formed on the conductive layer 111b within the area defined by the signal absorption ring 115b
  • a resistive material 116b is formed on the inside surface of the conductive layer 113b within the area defined by the signal absorption ring 115b.
  • FIG. 10C illustrates a CSB 110c with a signal absorption ring 115c implemented according to the method shown in FIG. 9A on one surface (facing the conductive layer 113c) of the dielectric layer 112c.
  • a resistive material 116c is formed on the dielectric layer 112c within the area defined by the signal absorption ring 115c.
  • FIG. 10D shows a CSB 110d with a signal absorption ring 115d implemented according to the method shown in FIG. 9A on both surfaces (facing the conductive layers 111d and 113d) of the dielectric layer 112d.
  • a resistive material 114d and 116d is formed on the surfaces of the dielectric layer 112d within the area defined by the signal absorption ring 115d.
  • signal dampening can be achieved by implementing a single signal absorption ring on any one of the layers of the CSB (which include at least two conductive layers and an intervening dielectric layer).
  • faster and more effective dampening will be achieved through implementation of additional signal absorption rings that co-align through the z-axis (orthogonal to the x-y plane of the layers) of the CSB.
  • the implementation of a signal absorption ring on a particular CSB layer does not preclude use of the area above the perimeter absorption ring for component attach as long as connection to the layer implementing the signal absorption ring (e.g., connection to a power plane implementing the signal absorption ring or ground plane implementing the signal absorption ring) is not required in that area.
  • the CSB is effectively a large plate capacitor that is formed with at least one signal absorption ring that dampens lateral flowing waves created by charge movement to and from sources and loads coupled to the large integral storage layer, thereby eliminating or at least substantially mitigating the resonance limitations of the capacitor.
  • the reflective edge is effectively erased, yet the bypassing and isolating ability of the capacitor is not adversely affected.
  • FIG. 11 A is a perspective view
  • FIG. 11B is a cross-sectional side view an integrated circuit device 200 implementing a CSB 210 of the invention.
  • the integrated circuit device 200 includes a substrate 220.
  • the substrate 220 comprises a set of signal layers 230 and a charge storage basement (CSB) 210.
  • CSB charge storage basement
  • the CSB 210 comprises a plurality of conductive material layers 211 , 213, 215 interleaved with layers of dielectric material 212, 214. More particularly, the CSB 210 includes a top conductive layer 211 , a top high-dielectric layer 212, a center conductive layer 213, a bottom high-dielectric layer 214, and a bottom conductive layer 215.
  • the center conductive layer 213 is connected to a power source Vcc 275 and operates as a power plane.
  • the bottom conductive layer 215 is connected to a device ground 272 and operates as a ground plane.
  • the top and bottom conductive layers 211 and 215 are electrically connected by an array of vias 270a, 270b, 270c, 27Od, 27Oe.
  • the array of vias 270a, 270b, 270c, 27Od, 27Oe provides intimate ground connections between the top and bottom conductive layers 211 and 215 so that the two conductive layers 211 and 215 together act as if they are one continuous ground plane, thereby increasing the length L of the plate capacitor.
  • the CSB 210 provides a near-instantaneous charge supply to electronic components 250a, 250b, 250c, 25Od that may be attached to the substrate 220 and that connect to the power plane 213 of the CSB 210 through the signal layers 230 by way of one or more conductive paths 260 (implemented, for example, with vias and/or traces, preferably using the shortest path possible). Connections between the electronic components 250a, 250b, 250c, 25Od and the ground plane (through connection to one of the top or bottom conductive layers 211 or 215) provides good wide-band RF ground returns.
  • electronic components 250a, 250b, 250c, 25Od attached to the substrate 220 may utilize one or more of the signal layers 231 , 232, 233, 234, 235, 236 for routing signals between electronic components in a conventional manner that is well-known in the art.
  • the electronic components 250a, 250b, 250c, 25Od utilizing the CSB 210 as a source of near- instantaneous charge each contact the power plane 213 of the CSB 210, preferably by way of one or more vias (through the signal layers 230 and CSB layers 210) that are, if possible, co-located at the location that the charge is needed in the electronic component 250a, 250b, 250c, 25Od.
  • electronic component 250a is connected to the CSB power plane 213 by way of via 260b; electronic component 250b is connected to the CSB power plane 213 by way of via 260c; electronic component 250c is connected to the CSB power plane 213 by way of via 6Oe; electronic component 25Od is connected to the CSB power plane 213 by way of via 260k.
  • Electronic components 250a, 250b, 250c, and 25Od are also connected to CSB ground plane 211 to provide a good RF ground return.
  • electronic component 250a is connected to the CSB ground plane 211 by way of via 260a; electronic component 250b is connected to the CSB ground plane 211 by way of via 26Od; electronic component 250c is connected to the CSB ground plane 211 by way of via 26Og; electronic component 25Od is connected to the CSB ground plane 211 by way of via 26Oi.
  • Each of the conductive planar layers 211 , 213, and 215 includes a non- absorptive area of respective substantially constant resistance.
  • the power plane 213 is formed with a signal absorption ring 280 that bounds a non-absorptive area 281.
  • the power plane 213 includes the signal absorption ring 280, illustrated using tapered edges in FIG. 11 B.
  • the purpose of the signal absorption ring 280 is to dampen signal waves generated within the non-absorptive area 281 of the conductive plane 213 to eliminate or at least significantly reduce reflections. In this manner, the ⁇ / ⁇ /2 resonances that would otherwise arise at particular resonant frequencies are avoided, allowing a wide-band RF ground return.
  • the CSB 210 provides excellent isolation between electronic components 250a, 250b, 250c, 25Od that are attached to it due to the good, low-impedance ground return that the CSB 210 maintains over a wide band of frequencies.
  • the impedance between the ground planes 211 and 215 is low due to the array of connecting jumpers 270a-270e.
  • the actual value of the impedance between the ground planes 211 and 215 can be adjusted by adjusting the number of connections between the planes and / or the material used to connect the ground planes.
  • the CSB can be implemented as illustrated in FIG. 12. As shown, this embodiment involves increasing the impedance between the ground planes 311 and 315 by reducing the number of jumpers between them to a single jumper 370a (illustrated, or a small few such jumpers to achieve the desired impedance) near the voltage source 375. Then, attaching electronic components to different ground planes 311 or 315 provides additional isolation between the electronic components due to the impedance that arises from the path from electronic component to electronic component and the impedance that arises on the single jumper 370a (or small few such jumpers) between the two ground planes 311 and 315. In the arrangement shown in FIG.
  • electronic component 350a is connected to the first plane 311 by way of via 360a; electronic component 350b is connected to the second ground plane 45 by way of via 360c; electronic component 350c is connected to the first ground plane 311 by way of via 36Og; electronic component 35Od is connected to the second ground plane 315 by way of via 36Oi.
  • Electronic components 350a and 350c are therefore additionally isolated from electronic components 350b and 35Od.
  • the CSB 310 services a single-sided printed circuit board with all components 350a, 350b, 350c, and 35Od mounted to the same side of the substrate.
  • the CSB may be implemented to service a double-sided PCB.
  • the CSB 310 could be fabricated in the center of the substrate 320, utilizing one set of CSB layers to service components mounted on one side of the PCB and another set of CSB layers to service components mounted on the other side of the PCB. If no isolation is required between the components on either side of the PCB, then the components on both sides of the board could tap into any of the layers of the CSB. Increased isolation between electronic components may also be achieved by using separate power sources feeding the power planes of the CSB.
  • the CSB 410 includes at least three conductive planes 411 , 413, and 415, interleaved by dielectrics 412 and 414 as shown.
  • This embodiment 400 achieves greater isolation by creating two separate circuits with the conductive planes 411 , 413, and 415.
  • a separate voltage source 475a and 475b is coupled to each power plane 411 and 415, and a ground is coupled to plane 413.
  • electronic components 450a and 450c are connected to the power plane 411 by way of vias 460a and 46Oe respectively, and return ground paths are provided by way of via connections 460b and 46Of respectively to ground plane 413.
  • Electronic components 450b and 45Od are connected to the power plane 415 by way of vias 460c and 460g respectively, and return ground paths are provided by way of via connections 46Od and 46Oh respectively to ground plane 413.
  • Additional isolation may be achieved by increasing the number of power conductive layers and respective power source connections (interleaved by dielectric layers) in the stack. Additional ground conductive layers (coupled to the first ground layer 413 and interleaved by dielectric layers) may also be included in the stack to achieve additional capacitance.
  • the CSB 410 of FIG. 13B may be implemented to service a double-sided PCB.
  • the CSB 410 could be fabricated in the center of the substrate 420, utilizing one set of CSB layers 411 , 412, 413, powered by one power source Vi, to service components 450a, 450c mounted on one side of the PCB, and another set of CSB layers 413, 414, 415, powered by one power source V 2 , to service components 450b, 45Od mounted on the other side of the PCB.
  • the various embodiments shown may be combined to produce variations.
  • FIG. 14 shows a top plan view of a conductive planar layer 500 for implementing at least one of the conductive layers in a CSB.
  • an electronic component 550a may be further isolated from surrounding circuitry (e.g., electronic component 550b) by implementing a second signal absorption ring 580 around a non-absorptive zone 504 and connecting electronic component 550a to the CSB within the area defined by the non-absorptive zone 504.
  • the signal absorption ring 580 preferably is preferably implemented with a graded resistive profile that maximizes at the center (or somewhere between the inner and outer perimeters 581 and 585 of the signal absorption ring 580, and which gradually increases in a preferably linear or exponential manner from the perimeters 581 and 582 to the center or other chosen interior line of the signal absorption ring 580.
  • This provides maximum isolation between electronic components 550a and 550b connected to the conductive layer 500, while also allowing signal dampening in both areas.
  • FIGS. 15A-15D show continuous resistive grading which begins with low resistivity at each of the perimeters 581 and 582 of the signal absorption ring 580 and increases, preferably in a substantially linear or exponential manner, as the center of the signal absorption ring 580 is approached.
  • FIG. 15A shows continuous resistive grading which begins with low resistivity at each of the perimeters 581 and 582 of the signal absorption ring 580 and increases, preferably in a substantially linear or exponential manner, as the center of the signal absorption ring 580 is approached.
  • FIGS. 15B, 15C, and 15D illustrate techniques for achieving step- wise resistive grading using, respectively, smooth step grading, hole step grading, and fractal step grading.
  • the embodiments of FIGS. 15B, 15C, and 15D also begin with low resistivity at the perimeters 581 and 582 and increase, preferably in a step-wise linear or exponential manner, as the center of the signal absorption ring 580 is approached.
  • the signal absorption ring 580 is implemented with resistive grading according to one of the embodiments shown in FIGS.
  • the signal absorption ring 580 adds isolation to protect the sensitive circuits 550a connected within the sub-area 504 from circuitry 550b connected to the conductive layer in the first area 501 outside the signal absorption ring 580.
  • the graded resistive profile of the signal absorption ring 580 goes from low impedance at the outer perimeter 581 of the signal absorption ring 580 to high impedance at the inner perimeter 582 of the signal absorption ring 580.
  • the isolation arises from the RF absorption that occurs as small signals from area 501 travel through the signal absorption ring 580 towards the isolated area 504. In this way, noise created by electronic components connected to the area 501 outside the signal absorption ring 580 do not contaminate the sensitive circuitry connected to the area 504 bounded by the signal absorption ring 580.
  • the signal absorption ring 580 may be alternatively implemented to isolate electronic components 550b connected to the area 501 of the conductive layer 500 outside the signal absorption ring 580 from signals traveling from electronic components 550a connected to the conductive layer 500 within the area 504 bounded by the signal absorption ring 580.
  • the graded resistive profile of the signal absorption ring 580 goes from low impedance at the inner perimeter 582 of the signal absorption ring 580 to high impedance at the outer perimeter 581 of the signal absorption ring 580.
  • absorptive boundaries may be implemented anywhere on the conductive plane as needed to create isolated areas of integral charge storage for use in isolating the electronic components of the integrated circuit from one another where desired. Absorptive boundaries may also be implemented within sub-areas, sub- sub-areas, and so on, for the same reasons.
  • resistive grading need not be implemented at the physical edges of the conductive planes of the CSB if signal absorption rings with resistive grading are formed around charge storage areas on the substrate to minimize reflections of signals enclosed in the charge storage areas.
  • resistive grading at one or more of the physical edges of the conductive planes of the CSB for power reasons. More specifically, if the integrated circuit power source is connected in the center of the chip, as it often is, for example in the non- absorptive area 501 of a conductive plane implemented according to the CSB layer illustrated in FIG. 14, but not in non-absorptive area 504, all the power loads are located in area 501.
  • FIG. 16 illustrates a charge storage basement 610 implemented integral to a circuit package 620 rather than as part of the integrated circuit die 600 itself.
  • an integrated circuit package 620 includes a number of interconnect layers 630 and a charge storage basement 610.
  • the package 620 includes a circuit bed 640 for seating an integrated circuit die 600.
  • the integrated circuit die 600 is provided with input/output (I/O) pads or leads.
  • the integrated circuit die utilizes ball grid array (BGA) or flip-chip technology for attachment of the integrated circuit die to the package.
  • BGA ball grid array
  • I/O power and ground
  • the CSB 610 is implemented in the same manner as described above with respect to the CSB 610 for the circuit die' 600. Thus the concepts are identical and the CSB 610 may be implemented in accordance with any of the example embodiments discussed herein. The only real difference is that the CSB 610 is implemented in the circuit packaging and thus has a longer path and potentially more resonance limitations then when implemented integral to the integrated circuit die itself.
  • the CSB is integrated into the integrated circuit die itself, providing extremely fast charge delivery and good wide-band RF return paths to the components of the IC.
  • FIGS. 17, 18, and 19 various partial implementations of CSBs of the invention are illustrated. These partial implementations allow for the power distribution of multiple power supplies V-i, V 2 , V 3 , V 4 to the same or different sections of any given substrate in which the CSB power distribution circuits are implemented.
  • V-i multiple power supplies
  • V 2 , V 3 , V 4 to the same or different sections of any given substrate in which the CSB power distribution circuits are implemented.
  • FIG. 17 illustrates an integrated circuit device 700 with a CSB 710 comprising four conductive layers 711 , 712, 713, and 714.
  • Conductive layer 714 comprises two mutually exclusive areas 714a, 714b of conductive material.
  • Each conductive layer 711 , 712, 713, 714 (and sub-area 714a, 714b of the layer 714) implements a signal absorption ring 780, 781 , 782.
  • Layer 712 operates as the ground layer, which is connected to a circuit ground.
  • Component 750a connects to conductive layer 714a, which is connected to a power source Vi.
  • Component 750b connects to conductive layer 711 , which is connected to a power source V 2 .
  • Component 750c connects to conductive layer 713, which is connected to a power source V 3 .
  • Component 75Od connects to conductive layer 714b, which is connected to a power source V 4 .
  • Each of components 750a, 750b, 750c, 75Od are electrically isolated from one another between they are connected to different power planes sourced by different power supplies. V 1 , V 2 , V 3 , and V 4 .
  • FIG. 18 illustrates another example of an integrated circuit device 800 with a CSB 810 comprising four conductive layers 811 , 812, 813, and 814.
  • conductive layer 814 comprises two mutually exclusive areas 814a, 814b of conductive material.
  • Each conductive layer 811 , 812, 813, 814 (and sub-area 814a, 814b of the layer 814) implements a signal absorption ring 880, 881 , 882.
  • Layers 811 and 813 are electrically connected to one another, and together operate as the ground layer, which is connected to a circuit ground.
  • Component 850a connects to conductive layer 814a, which is connected to a power source V-
  • Components 850b and 850c connect to conductive layer 812, which is connected to a power source V 2 .
  • Component 85Od connects to conductive layer 814b, which is connected to a power source V 3 .
  • Component 850a is electrically isolated from components 850b, 850c, and 85Od.
  • Components 850b and 850c are electrically isolated from components 850a and 85Od.
  • Component 85Od is electrically isolated from components 850a, 850b, and 850c.
  • FIG. 19 illustrates another example of an integrated circuit device 900 having three separate integral CSBs 910a, 910b, 910c, implemented using only two conductive layers 911 , 913 and an intervening dielectric layer 912.
  • Conductive layer 913 comprises three mutually exclusive areas 913a, 913b, 913c of conductive material, each connected to a different power source Vi, V 2 , V 3 .
  • Each conductive layer 911 , 913 (and sub-areas 913a, 913b of the layer 913) implements a signal absorption ring 980.
  • Component 950a connects to conductive layer 913a, which is connected to a power source Vi .
  • Components 950b and 950c connect to conductive layer 913b, which is connected to a power source V 2 .
  • Components 95Od and 95Oe connect to conductive layer 913c, which is connected to a power source V 3 .
  • Component 950a is electrically isolated from components 950b, 950c, 95Od, and 95Oe.
  • Components 950b and 950c are electrically isolated from components 950a, 95Od, and 95Oe.
  • Components 95Od and 95Oe are electrically isolated from components 950a, 950b, and 950c.
  • FIGS. 17, 18, and 19 illustrating separate yet integral CSBs used to implement a particularly complex and diverse power distribution set of networks.
  • multi-power supplies being distributed to various sections of the board. Some supplies are attached to a single CSB while others are attached to more than one CSB. In fact for many single or dual power supply applications a single or dual CSB may be used. However the use of a generalized set of CSBs both integral and discrete to solve any particular single or multi-power-supply power distribution network is covered by the present invention.
  • FIG. 20 illustrates a flowchart of an exemplary method 1000 for providing charge to a circuit component.
  • this method comprises the steps of: implementing one or more signal absorption rings that respectively bounds a respective non- absorptive area of at least one of a respective first conductive surface and/or a respective second conductive surface, the signal absorption ring operating to dampen laterally flowing Transverse Electric Magnetic (TEM) waves between the respective non- absorptive area of the first conductive surface and the respective non-absorptive area of the second conductive surface (step 1001); connecting a power signal terminal of the circuit component to the respective non-absorptive area of the first conductive surface (step 1002); connecting a power signal return terminal of the circuit component to the respective non-absorptive area of the second conductive surface (step 1003); connecting the first conductive surface to a first power source (step 1004); and connecting the second conductive surface to a second power source, the second power source at a different potential than the first power source (step 1005).
  • TEM Transverse Electric Magnetic
  • FIG. 21 illustrates a flowchart of an exemplary method 1010 for fabricating a capacitor in accordance with the invention. As illustrated, this method comprises the steps of: providing a first conductive surface (step 1011); providing a second conductive surface isolated from the first conductive surface but capacitively coupled to the first conductive surface (step 1012); and implementing a signal absorption mechanism that operates to dampen laterally flowing Transverse Electric Magnetic (TEM) waves between the first conductive surface and the second conductive surface (step 1013).
  • TEM Transverse Electric Magnetic
  • the CSB provides near-instantaneous charge by reducing the distance between the circuit loads and the power source to the length of a single via (i.e., the length of a lead through layers in the substrate to the electronic components on top of it.)
  • the CSB is a structure of layered conductive and dielectric materials integrated into the chip die or die packaging, creating charge storage available to the electronic components located above or below it. Because the CSB provides a power source that is nearly co-located with the load, inductance over the power-delivery path is very low, making power- delivery extremely responsive, nearly instantaneous. Also, because the charge is stored everywhere in the IC or printed circuit board, designers are free to locate the electronic components anywhere on the substrate without having to develop power delivery circuitry.
  • the CSB eliminates the design complexities outlined in the background section by providing a good RF ground path over a wide range of frequencies.
  • the mechanism by which it provides this ground path is by providing such a short path (i.e., as short as a via length) to available charge storage that it practically eliminates the parasitic inductance.
  • Yet another advantage of the present invention over the prior art is that the CSB replaces all the bypass capacitors, thereby reducing the number of circuit elements on the chip.
  • the CSB replaces all the bypass capacitors, thereby reducing the number of circuit elements on the chip.
  • many of the bypass capacitors on the PCB can be eliminated.
  • Another advantage of the present invention over the prior art is the CSB's ability to isolate electronic components.
  • the preferred embodiment of the CSB provides good isolation between electronic components and/or circuits on the integrated circuit by providing improved wideband ground returns. Where additional isolation is needed, circuits can be isolated from one another by implementing separate signal absorption rings around them.

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Abstract

L'invention concerne une structure capacitive (20) et une technique permettant un transport de charges quasi instantané et des trajets de mise à la masse RF à large bande fiables pour des dispositifs à circuits intégrés tels que des puces à circuits intégrés, des boîtiers de circuits intégrés, des cartes de circuits imprimés, et des substrats de circuits électroniques. L'invention concerne également des méthodes pour créer des pertes résistives, des pertes diélectriques, des pertes magnétiques, et/ou des pertes par radiation dans un anneau absorbant les signaux (25a, 25b, 25c) réalisé autour d'une zone non absorbante (34a) d'une ou plusieurs couches conductrices (14, 18) d'une structure de circuit intégré (20) pour amortir les ondes électromagnétiques (EM) se propageant latéralement entre des couches conductrices électriquement adjacentes du dispositif.
PCT/US2006/030986 2006-08-09 2006-08-09 Embase de stockage de charges intégrée et structure de découplage large bande incorporée pour circuits intégrés WO2008018870A1 (fr)

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WO2005104149A1 (fr) * 2004-04-19 2005-11-03 Wemtec, Inc. Systemes et procedes de blocage de la propagation de micro-ondes dans des structures de plaques paralleles a l'aide d'ensembles de trous d'interconnexion

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US9570783B1 (en) 2015-08-28 2017-02-14 General Electric Company Radio frequency micro-electromechanical systems having inverted microstrip transmission lines and method of making the same
US9806390B2 (en) 2015-08-28 2017-10-31 General Electric Company Radio frequency die package with inverted ground plane and method of making same
US9954263B2 (en) 2015-08-28 2018-04-24 General Electric Company Radio frequency micro-electromechanical systems having inverted microstrip transmission lines and method of making the same

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