WO2008015725A1 - Dispositif et procédé pour évaluer la capacité électrostatique à authentifier - Google Patents

Dispositif et procédé pour évaluer la capacité électrostatique à authentifier Download PDF

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Publication number
WO2008015725A1
WO2008015725A1 PCT/JP2006/315122 JP2006315122W WO2008015725A1 WO 2008015725 A1 WO2008015725 A1 WO 2008015725A1 JP 2006315122 W JP2006315122 W JP 2006315122W WO 2008015725 A1 WO2008015725 A1 WO 2008015725A1
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WIPO (PCT)
Prior art keywords
pulse
determination
output
authentication target
level
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PCT/JP2006/315122
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English (en)
Japanese (ja)
Inventor
Koichiro Niinuma
Takashi Shinzaki
Seiichi Iwasa
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Fujitsu Limited
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Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2008527600A priority Critical patent/JP4653222B2/ja
Priority to PCT/JP2006/315122 priority patent/WO2008015725A1/fr
Publication of WO2008015725A1 publication Critical patent/WO2008015725A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/1382—Detecting the live character of the finger, i.e. distinguishing from a fake or cadaver finger
    • G06V40/1394—Detecting the live character of the finger, i.e. distinguishing from a fake or cadaver finger using acquisition arrangements

Definitions

  • the present invention relates to a capacitance determination device and a determination method for an authentication target (for example, a finger) that is a part of a living body, and in particular, to determine whether the authentication target (for example, a finger) is authentic or not.
  • the present invention relates to an apparatus and a method for determining based on capacitance.
  • biometric information In recent years, opportunities for performing personal authentication using biometric information (biometric information) have increased.
  • Patent Document 1 requires a low-pass filter, a comparator, an edge detection circuit, etc. to convert a change in finger capacitance into a change in oscillation frequency, which complicates the hardware configuration. There is.
  • An object of the present invention is to provide an authentication target capacitance determination device that is used by being incorporated in a biometric authentication device or the like, and that can determine the authentication target capacitance with a simple configuration and method. It is to provide a determination method.
  • the capacitance determination device for authentication of the first aspect of the present invention is a biocapacitance that is a pulse having a pulse width corresponding to the capacitance of the authentication target that is a part of the living body placed between the electrodes.
  • a biocapacitance pulse output unit that outputs a pulse, and a first determination pulse that is output after a predetermined time delay from a pulse that determines the output timing of the biocapacitance pulse, and that is used to determine the authenticity of the authentication target.
  • the determination pulse output unit and a pulse that determines the output timing of the biological volume pulse are output with a time delay greater than the predetermined time, and a second determination pulse that is used to determine the authenticity of the authentication target is output.
  • the authentication target capacitance determination device includes a determination unit that outputs a signal indicating that the authentication target is true.
  • the capacitance determination device for authentication of the second aspect of the present invention is a biocapacitance that is a pulse having a pulse width corresponding to the capacitance of the authentication target that is a part of the living body placed between the electrodes.
  • a bio-capacity pulse output unit that outputs a pulse, and a determination pulse output that outputs a determination pulse that is output after a predetermined time delay from a pulse that determines the output timing of the bio-capacity pulse, and that is used to determine the authenticity of the authentication target And an output timing force of the determination pulse, and a signal indicating that the authentication target is false when it falls within the pulse width of the biocapacitance pulse, and an output timing force of the determination pulse
  • An authentication target capacitance determination apparatus comprising: a determination unit that outputs a signal indicating that the authentication target is true when the signal does not fall within a pulse width. .
  • the capacitance determination method of the authentication target according to the third aspect of the present invention includes a clock pulse having a constant period. And a biocapacitance pulse output for outputting a biocapacity pulse, which is a pulse having a pulse width corresponding to the capacitance of the authentication target, which is a part of the living body placed between the electrodes, at the timing of the clock pulse.
  • a first determination pulse output step that outputs a first determination pulse that is output after being delayed by a predetermined time from the clock pulse and is used to determine whether the authentication target is authentic, and from the clock pulse,
  • a second determination pulse output step that outputs a second determination pulse that is output with a time delay greater than a predetermined time and that is used to determine the authenticity of the authentication target; the first determination pulse and the second determination pulse;
  • both output timing forces fall within the pulse width of the biological volume pulse, a signal indicating that the authentication target is false is output, and the first determination parameter is output.
  • the authentication target is true when the output timing of the target falls within the pulse width of the biocapacitance pulse and the output timing of the second determination pulse does not fall within the pulse width of the biocapacitance pulse.
  • a determination step for outputting a signal indicating that the capacitance is to be verified.
  • the authentication target capacitance determination method corresponds to a step of generating a clock pulse having a fixed period and a capacitance of the authentication target that is a part of a living body placed between electrodes.
  • a biocapacitance pulse output step for outputting a biocapacity pulse, which is a pulse having a pulse width to be used, at a timing of the clock pulse, and a delay after the clock pulse for a predetermined time, which is output for the authenticity determination of the authentication target.
  • FIG. 1 is a block diagram showing a configuration of a capacitance determination device according to an embodiment of the present invention.
  • FIG. 2 is a diagram (part 1) illustrating a more detailed configuration of the clock generation circuit of FIG.
  • FIG. 3A is a diagram (part 1) illustrating a more detailed configuration of the first determination pulse generation circuit of FIG.
  • FIG. 3B is a diagram (part 1) illustrating a more detailed configuration of the second determination pulse generation circuit of FIG. 1;
  • FIG. 4 is a diagram (No. 1) showing a more detailed configuration of the biocapacitance pulse generation circuit of FIG.
  • FIG. 6 is a diagram showing waveforms input and output by each circuit part (contact determination circuit and authentication target authenticity determination circuit) of FIG. 5.
  • FIG. 7 is a diagram for explaining the operation of a NAND gate that is a part of FIG. 5.
  • FIG. 8A is a diagram (part 1) illustrating an operation of a latch circuit that is a part of FIG. 5.
  • FIG. 8B is a diagram (part 2) illustrating the operation of the latch circuit that is part of FIG. 5.
  • FIG. 9 is a diagram showing an IC used in the clock generation circuit, first determination pulse generation circuit, and first determination pulse generation circuit of FIG. 1.
  • FIG. 10 is a diagram (part 2) illustrating a more detailed configuration of the clock generation circuit of FIG.
  • FIG. 11A is a diagram (part 2) illustrating a more detailed configuration of the first determination pulse generation circuit of FIG.
  • FIG. 11B is a diagram (part 2) illustrating a more detailed configuration of the second determination pulse generating circuit of FIG.
  • FIG. 12 is a diagram (part 2) illustrating a more detailed configuration of the biocapacitance-compatible pulse generation circuit of FIG.
  • FIG. 1 is a block diagram illustrating a configuration of a capacitance determination device according to an embodiment of the present invention.
  • a capacitance determination device 10 includes a part of a living body (in the figure, a finger placed between electrodes). ) For determining the capacitance of the authentication target.
  • the capacitance determination device 10 is built in a biometric authentication device that performs biometric authentication based on biometric information (for example, a fingerprint) obtained from the authentication target.
  • biometric information for example, a fingerprint
  • This capacitance determination device 10 outputs a pulse having a pulse width corresponding to the capacitance to be authenticated at the timing of the clock pulse generated by the clock pulse generation circuit 11.
  • the first determination that outputs a first determination pulse that is output after a predetermined time delay from the clock pulse output from the biocapacity-compatible pulse generation circuit 14 and the clock pulse generation circuit 11 that is used to determine the authenticity of the authentication target.
  • a pulse output unit 12 and a clock pulse generation circuit 11 output a second determination pulse that is output after being delayed by a time longer than the predetermined time and used for the authenticity determination of the authentication target.
  • the first determination pulse is also a pulse indicating whether or not the authentication target (finger) is in contact with both electrodes, and is also referred to as a “contact determination pulse”.
  • FIG. 2 is a diagram showing a more detailed configuration of the clock generation circuit of FIG. 1 in the first embodiment.
  • a fast multivibrator is configured by the NAND gate (NAND1), inverter (INV1), capacitor (CI1), and resistors (R12 and R13).
  • Resistor R13 is a (protective) resistor that limits the current that flows through the clamp diode built in the input terminal of the NAND gate (NAND1), and is set to a value about 20 times the resistance value of resistor R12. It is appropriate to do.
  • the level of the oscillation control terminal F in the figure is changed from the “L” level to the “H” level (hereinafter, this “H” level is maintained while the power is on). .
  • FIG. 3A is a diagram (part 1) showing a more detailed configuration of the first determination pulse generation circuit of FIG. 1.
  • a NAND gate NAND2
  • an inverter INV4
  • a capacitor C13
  • a monostable multivibrator hereinafter referred to as monomano vibrator
  • R15 resistor
  • the value of resistor R15 In order to keep the level at point J below the input threshold level of the inverter (INV4) in the steady state, the value of resistor R15 needs to be below a predetermined value. If the value of the resistor R15 is not less than this predetermined value, the above-described operation cannot be guaranteed.
  • the resistor (R15) is a resistor that determines the amount of delay of the clock pulse output from the clock pulse generation circuit (the delay amount is proportional to the value of the resistor R15), the resistor R15 is a variable resistor. This makes it easier to adjust the generation timing of the pulses output by the circuit in Figure 3A.
  • FIG. 3B is a diagram (part 1) showing a more detailed configuration of the second determination pulse generation circuit of FIG. 1. This circuit is input in comparison with the first determination pulse generation circuit of FIG. 3A. The operation is the same as the circuit in Figure 3A, except for the amount of delay that indicates how much the clock pulse is delayed.
  • FIG. 4 is a diagram (part 1) showing a more detailed configuration of the biocapacitance pulse generation circuit of FIG. is there.
  • the resistance value of the authentication target (finger) is in the range of several tens to several hundreds.
  • the capacitor C7 is a capacitor for blocking a current flowing through the authentication target (resistor). Without this capacitor, circuit operation becomes unstable.
  • the capacitance value of capacitor C7 should be at least 10 times the capacitance value (approximately 5nF) of the authentication target (finger), for example, 50nF or more! /.
  • the NAND gate (NAND4) and the inverter (INV10) are TTL-ICs.
  • NAND4 and the inverter (INV10) are TTL-ICs.
  • This biocapacitance-compatible pulse generation circuit has an external capacitance C7 and a capacitance of a pair of electrode portions (capacitance of an authentication target (finger) or capacitance of air, etc.) Cy in series.
  • the operation of the circuit in Fig. 4 is the same as the operation of NAND2, capacitor C13, resistor R15, and inverter INV4 in Fig. 3A, except that the capacitance of the capacitor (Cx) is different.
  • the authentication target (finger) contacts only the electrode on one side! In this state, the contribution to the capacitance from the electrode is approximately 0 (Cy is approximately 0).
  • the capacitance (Cx) that combines the capacitance of the electrode and capacitor (C7) provided between the NAND gate (NAND4) and inverter (IN V10) in Fig. 4 is the capacitance of the capacitor (C7) (for example, 300pF) Almost equal.
  • the biocapacity corresponding pulse generation circuit in the figure outputs a pulse having a time width (1 ⁇ sec), for example.
  • the human finger in a state where a true finger (human finger) is in contact with both electrodes! /, The human finger usually has a capacitance of about InF to several nF.
  • the pulse generation circuit corresponding to the biocapacitance outputs a pulse corresponding to the capacitance, for example, a pulse of about 10 sec to 50 ⁇ sec.
  • a pulse having a time width (for example, a time width of about 500 sec or more) corresponding to the finger capacitance (for example, several tens of nF) is output from the biocapacitance-compatible pulse generation circuit in FIG. 4, for example, when gelatin or the like to which a fingerprint has been transferred is in contact with both electrodes (correctly), that is, when a fake finger is in contact with both electrodes.
  • a pulse having a time width for example, a time width of about 500 sec or more
  • the finger capacitance for example, several tens of nF
  • FIG. 5 is a diagram showing a more detailed configuration of the contact determination circuit and the authentication target authenticity determination circuit of FIG.
  • FIG. 6 is a diagram showing waveforms input and output by each circuit portion (contact determination circuit and authentication target authenticity determination circuit) of FIG.
  • a contact determination circuit is configured by the NAND gate (NAND) 21 and the first latch circuit (NAND22 and NAND23). Also, the authentication target authenticity determination circuit is configured by the NAND gate (NAND) 24, the inverter (INV) 25, the NAND gate (NAND) 26, and the second latch circuit (NAND27 and NAND28).
  • the contact determination circuit consists of NAND21 and the first latch circuit (NAND22 and NAND23) Consists of
  • the first judgment pulse rises after the fall of, and the biocapacity compatible panoreth that is output in response to the state where the authentication target (finger) is in contact with both electrodes
  • the delay amount of the contact judgment pulse in terms of the clock pulse is set so that the rise and fall of the touch judgment pulse are included between the rise and fall of the biocapacity corresponding pulse.
  • the capacitance of the fake finger having a fingerprint transferred to gelatin or the like is larger than that of the true finger, for example, a biocapacitance-compatible pulse that is output when the true finger is placed on both electrodes
  • the rising and falling edges of the contact judgment pulse should be included between the rising and falling edges.
  • the time width of the biocapacity-corresponding pulse having the largest possible size / time width is included in the cycle of the clock pulse.
  • the period of the clock pulse is set in advance.
  • NAND 21 is a two-input NAND gate, and receives a biocapacitance pulse as one input, and receives a contact determination pulse obtained by delaying a clock pulse for a predetermined time as the other input.
  • the timing of the contact determination pulse for example, the rising timing of the contact determination pulse, at this timing, the level of the contact determination pulse is " At “H” level), as described above, the level of the biocapacitance pulse becomes “L”. For this reason, as shown in FIG. 7, the output level of NAND21 is “H” level.
  • the timing of the contact determination pulse (at this timing, the level of the contact determination pulse is At “H” level), as described above, the level of the biocapacitance corresponding pulse becomes “H”. Therefore, as shown in FIG. 8, the output level of the NAND 21 is “L” level.
  • NAND22 which is one of the two NAND gates constituting the first latch circuit, has two inputs Output of NAND21, which is the NAND gate that receives the output signal of NAND21 in the previous stage as one input (for example, “Input 1” in FIGS. 8A and 8B), and is the other NAND gate that forms the first latch circuit The signal is received as the other input.
  • NAND23 which is the other of the two NAND gates constituting the first latch circuit, is a two-input NAND gate, and the inverted signal of the clock pulse output from the clock pulse generation circuit in the previous stage is sent to one of the NAND gates. It receives as an input (for example, “Input 2” in FIGS. 8A and 8B) and receives the output signal of NAND22, which is the other NAND gate constituting the first latch circuit, as the other input.
  • the level of the biocapacitance pulse is “H” level and the level of the contact determination pulse is “L” level.
  • the output becomes “H” level. That is, the NAND 22 of the first latch circuit receives an “H” level signal from the NAND 21.
  • the output signal of the first latch circuit is also referred to as a "contact flag" because flag information indicating whether or not the authentication target is in contact with both electrodes is reflected in that level. For example, when the level of the contact flag is “H” level, it indicates that the authentication target (finger) is in contact with both electrodes.
  • the level of the contact determination pulse is “H” level
  • the authentication target finger
  • the biocapacity pulse is at the “L” level
  • the output of NA ND21 is at the “H” level. That is, the NAND 22 of the first latch circuit receives an “H” level signal from the NAND 21.
  • the authentication target authenticity determination circuit includes a NAND 24, an inverter (INV) 25, a NAND 26, and a second latch circuit (NAND 27 and NAND 28).
  • the second latch circuit is also reset to output a signal of level “L” at the timing of the inverted signal of the clock pulse, similarly to the first latch circuit. .
  • the rising and falling edges of the contact determination pulse occur between the rising and falling edges of the biocapacity corresponding pulse that is output when the true finger is placed on both electrodes.
  • the delay amount from the clock pulse of the contact determination pulse (first determination pulse) is set. Therefore, it is set so that it rises after the fall of the biocapacitance pulse that is output corresponding to the case where the finger is placed on both electrodes.
  • the determined second determination pulse has a larger delay amount with respect to the clock pulse than the contact determination pulse.
  • NAND24 is a two-input NAND gate that receives an inverted signal of the biocapacitance pulse as one input, and the clock pulse is delayed by a time longer than the delay time of the contact determination pulse (first determination pulse). 2 Accept the decision pulse as the other input.
  • the timing of the second determination pulse (for example, At the timing of the rise of the second determination pulse, at this timing, the level of the second determination pulse is “H” level), as described above, the level of the inverted signal of the biocapacitance pulse is set to “H”. Become. Therefore, as shown in FIG. 7, the output level of the NAND 24 is the “L” level.
  • the timing of the second determination pulse (at this timing, the level of the second determination pulse is “H” level) Then, as described above, the level of the inverted signal of the biological volume corresponding pulse becomes “L”. Therefore, as shown in FIG. 7, the output level of NAND24 is “H” level.
  • the NAND 26 is a two-input NAND gate, and receives the output signal (contact flag) of the contact determination circuit as one input, and receives the inverted signal (via INV 25) of the NAND 24 output as the other input.
  • the output level of NAND24 is “L” level.
  • the NAND 26 receives an inverted signal (level “H” signal) (through the INV 25) of the output of the NAND 24 as one input, and receives an “L” level signal from the contact determination circuit as the other input. Then, the NA ND 26 outputs an “H” level signal.
  • the “H” level output of the NAND 26 is input to the NAND 27, which is one of the two NAND gates constituting the second latch circuit.
  • an inverted signal of the clock pulse is input to the NAND 28, which is the other of the two NAND gates constituting the second latch circuit.
  • the level of the clock pulse is the “L” level, and therefore the level of the inverted signal is the “H” level. Therefore, as shown in FIGS. 8A and 8B, the output level of the second latch circuit does not change. That is, as described above, the second latch circuit is reset to output a signal of level “L” with the inverted signal of the clock pulse immediately before the second determination pulse. The output remains at “L” level.
  • the output level of the NAND 24 is “L” level.
  • the NAND 26 receives an inverted signal (level “H” signal) of the output of the NAND 24 (via INV 25) as one input, and receives an “H” level signal from the contact determination circuit as the other input.
  • the NAND 26 outputs an “L” level signal.
  • the “L” level output of the NAND 26 is input to the NAND 27, which is one of the two NAND gates constituting the second latch circuit.
  • an inverted signal of the clock pulse is input to the NAND 28, which is the other of the two NAND gates constituting the second latch circuit.
  • the level of the clock pulse is “L” level, and therefore the level of the inverted signal is “H” level.
  • the second latch circuit outputs an “H” level signal.
  • the output level of the NAND 24 is “H” level.
  • the NAND 26 receives an inverted signal (level “L” signal) of the output of the NAND 24 (via INV 25) as one input, and receives an “H” level signal from the contact determination circuit as the other input. The NAND 26 outputs an “H” level signal.
  • the “H” level output of the NAND 26 is input to the NAND 27, which is one of the two NAND gates constituting the second latch circuit.
  • an inverted signal of the clock pulse is input to the NAND 28, which is the other of the two NAND gates constituting the second latch circuit.
  • the level of the clock pulse is the “L” level, and therefore the level of the inverted signal is the “H” level. Therefore, as shown in FIGS. 8A and 8B, the output level of the second latch circuit does not change. That is, as described above, the second latch circuit is reset to output a signal of level “L” with the inverted signal of the clock pulse immediately before the second determination pulse. The output remains at “L” level.
  • the output signal of the second latch circuit includes the flag information indicating whether the authentication target is true or false from the viewpoint of the capacitance, so that the level is considered to be “ Also called “true / false flag”.
  • the true / false flag level being “H” indicates that the authentication target (finger) is determined to be true in view of the electrostatic capacity force.
  • the output signal of the second latch circuit is also referred to at the time of authentication on the side of the biometric authentication device that performs biometric authentication based on the biometric information (for example, fingerprint) obtained from the authentication target. Conceivable.
  • a biocapacitance pulse having a pulse width corresponding to the capacitance of an authentication target, which is a part of the living body placed between the electrodes generated by the biocapacitance pulse output unit. Therefore, since the pulse width is determined based on the contact flag obtained from the first determination pulse and the second determination pulse, it is possible to determine the capacitance to be authenticated with a simple configuration. it can.
  • the clock generation circuit, the first determination pulse generation circuit, and the second determination pulse generation circuit are configured using NAND gates, inverters, resistors, and capacitors, but are commercially available.
  • the clock generation circuit, the first determination pulse generation circuit, and the second determination pulse generation circuit can be configured using an IC.
  • FIG. 9 is a diagram showing an IC used for the clock generation circuit, the first determination pulse generation circuit, and the first determination pulse generation circuit of FIG.
  • Fig. 9 ⁇ Koo! /, IC30i, 74HC123, 74LS123, etc. ICs with mono-multivibrators housed in a 16-pin socket.
  • IC30 has positive trigger input terminal (B terminal), negative trigger input terminal (A terminal), clear terminal ( CLR terminal), external capacitance connection terminal (Cext terminal), external resistance connection terminal (Rext terminal)
  • a bipolar transistor circuit combining a Schottky NOR diode and a transistor is used, and its input impedance is a number.
  • IC30 outputs a pulse having a time width (Tw) proportional to the product of external capacitance C and external resistance R.
  • Tw time width
  • Tw 0.45CR (sec).
  • the value of the external resistance R is several hundred ⁇ .
  • the value of the external resistance R can range from 5kQ to 260kQ due to the limitation of the base current range in which the bipolar transistor operates.
  • the IC 30 has the following three startup methods.
  • the external capacitance C is charged by the power supply (+ 5V) through the external resistor R, and the voltage at the Rext pin also increases linearly.
  • the voltage at the Rext terminal exceeds a certain value (approximately 2V)
  • the Q terminal becomes ⁇ L '' level and the Q bar terminal becomes ⁇ H '' level, and the series of operations ends, and the next trigger noise is input to the CLR terminal. Until a steady state is maintained.
  • FIG. 10 is a diagram (part 2) illustrating a more detailed configuration of the clock generation circuit of FIG.
  • the circuit shown in FIG. 10 combines a mono multivibrator configured using IC32 (for example, 74HC123) and a monomultivibrator configured using IC31 (for example, 74HC123), It is a circuit that functions as a self-oscillating hastable multivibrator.
  • IC32 for example, 74HC123
  • IC31 for example, 74HC123
  • This circuit changes the oscillation control terminal (CLR2 terminal) from “L” level to “H” level. Starts oscillation and stops from “H” level to “L” level.
  • the pulse width of the pulse output from this pulse generation circuit is proportional to the product of the external resistance R2 and the external capacitance C2, and the cycle of the pulse is the product of the external resistance R1 and the external capacitance C1. Proportional to.
  • the 1A and 2A terminals connected to the Q2 and Q1 terminals are both “L” level
  • the 1B and 2B terminals connected to the Q2bar and Qlbar terminals are both “H” level. It is a bell.
  • the external capacitances C1 and C2 are fully charged, the voltage at the Cextl and Cext2 pins is “OV”, and the voltage at the Rextl and Rext2 pins is “+ 5V”.
  • the oscillation control terminal (CLR2 terminal) becomes “H” level
  • the 2A terminal and 2B terminal satisfy the above-mentioned start condition 3. Therefore, at the rising edge, they are configured by IC32, R2, and C2.
  • the mono multivibrator is activated and the Q2 terminal goes to “H” level and the Q2bar terminal goes to “L” level.
  • Tw2 l.
  • the 1A and 1B pins are set to the start-up conditions described above 1. Therefore, the mono multivibrator composed of IC31, Rl, and CI is activated, and the Q1 pin is set to “H” level and the Qlbar pin is set to “L” level.
  • Twl l.
  • 4-Cl -Rl (sec) elapses, the Q1 pin becomes “L” level and the Qlbar pin becomes “H” level, returning to a stable state.
  • the oscillation control terminal (CLR2 terminal) is “H” level
  • the 2A terminal and the 2B terminal satisfy the above-mentioned start condition 3. Therefore, at the rising edge, IC32, R2, C2
  • the Q2 terminal changes to the “H” level
  • the Q2 bar terminal changes to the “L” level
  • Tw2 l. 4'C2'R2 (sec) has elapsed
  • the Q2 terminal “L” level, Q2bar terminal is set to “H” level. Generates a luth.
  • FIG. 11A is a diagram (part 2) illustrating a more detailed configuration of the first determination pulse generation circuit of FIG.
  • the circuit shown in FIG. 11A is a circuit in which a mono multivibrator configured using IC42 (eg, 74HC123) is subordinately connected to a monomultivibrator configured using IC41 (eg, 74HC123). It is. Then, the delay amount of the pulse output from the second-stage IC 42 with the first-stage external resistor R3 and the external capacitance C3 is reduced to the second-stage external resistor R4 and the external capacitance C4. The pulse width of the output pulse is determined.
  • IC42 eg, 74HC123
  • IC41 eg, 74HC123
  • the operation of the first determination pulse (contact determination pulse) generation circuit in FIG. 11A will be described below.
  • the clear terminal (CLR1 terminal) is “H” level
  • the negative trigger input terminal (1 A terminal) is “L” level
  • the clear terminal (CLR2 terminal) is “H” level, negative
  • the trigger input terminal (2A terminal) is at “L” level
  • FIG. 11B is a diagram (part 2) illustrating a more detailed configuration of the first determination pulse generation circuit of FIG. The operation of the circuit shown in FIG. 11B can be considered similarly to the circuit shown in FIG. 11A.
  • FIG. 12 is a diagram (part 2) illustrating a more detailed configuration of the biocapacitance-compatible pulse generation circuit of FIG.
  • the circuit shown in FIG. 12 is a mono multi-vibrator configured using IC51 (for example, 74LC123).
  • IC51 for example, 74LC123.
  • a large-capacitance capacitor C7 is attached to the external capacitance connection terminal (Cext terminal) of the IC51, and two electrodes that are in contact with the authentication target (finger) are provided in series with the capacitor C7.
  • the resistance value of the authentication target (finger) is in the range of several tens to several hundreds.
  • the capacitor C7 is a capacitor for blocking a current flowing through the authentication target (resistor). Without this capacitor, circuit operation becomes unstable.
  • the capacitance value of capacitor C7 should be at least 10 times the capacitance value (approximately 5nF) of the authentication target (finger), for example, 50nF or more! /.
  • the IC used to construct the mono multivibrator is preferably a TTL-IC such as 74LS123. This is because when a CMOS IC with very high input impedance (such as 74HC123) is used, the probability of malfunctioning increases when a finger that is part of the human body touches the terminal, for example.
  • This biocapacitance-capable pulse generation circuit has an external capacitance C7 and the capacitance of the pair of electrodes (capacitance of the authentication target (finger) or capacitance of air, etc.) Cy in series.
  • the clear terminal (CLR1 terminal) is at “H” level
  • the negative trigger input terminal (1 A terminal) is at “L” level
  • the biocapacitance pulse at the timing of the second determination pulse According to the level, it was judged whether the authentication target was true due to the capacitance force. In other words, at the timing of the second determination pulse, if the level of the biocapacity-corresponding pulse is “H” level, “false finger”, and if the level of the biocapacitance-capable pulse is “L” level, It was determined to be “finger”.
  • the first determination pulse generation circuit 12 and the contact determination circuit 15 are eliminated from FIG. 1, and the authentication target authenticity determination circuit is based on the clock pulse, the second determination pulse, and the biocapacitance pulse. The true / false of this is determined.
  • a finger is used as an example of an authentication target that is a part of a living body, but the authentication target may be another part of the living body.

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Abstract

La présente invention concerne un dispositif à construire dans un dispositif d'authentification biométrique pour évaluer une capacité électrostatique à authentifier qui peut évaluer une capacité électrostatique à authentifier avec une configuration simple. Le dispositif pour évaluer une capacité électrostatique à authentifier évalue une largeur d'impulsion d'une impulsion de capacité biométrique ayant une largeur d'impulsion correspondant à une capacité électrostatique d'un objet d'authentification dans le cadre d'un corps vivant placé entre des électrodes générées par une unité de production d'impulsion de capacité biométrique, à l'aide d'une première impulsion d'évaluation et d'une seconde impulsion d'évaluation. La première impulsion d'évaluation est produite avec un retard prédéterminé à partir de l'impulsion de capacité biométrique et la seconde impulsion d'évaluation est produite avec un retard supérieur au retard prédéterminé.
PCT/JP2006/315122 2006-07-31 2006-07-31 Dispositif et procédé pour évaluer la capacité électrostatique à authentifier WO2008015725A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008527600A JP4653222B2 (ja) 2006-07-31 2006-07-31 認証対象の静電容量判定装置および判定方法
PCT/JP2006/315122 WO2008015725A1 (fr) 2006-07-31 2006-07-31 Dispositif et procédé pour évaluer la capacité électrostatique à authentifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/315122 WO2008015725A1 (fr) 2006-07-31 2006-07-31 Dispositif et procédé pour évaluer la capacité électrostatique à authentifier

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WO2008015725A1 true WO2008015725A1 (fr) 2008-02-07

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JP (1) JP4653222B2 (fr)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010000224A (ja) * 2008-06-20 2010-01-07 Nippon Telegr & Teleph Corp <Ntt> 生体認識装置

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* Cited by examiner, † Cited by third party
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CN110108239B (zh) * 2019-05-21 2021-04-02 东莞维科电池有限公司 极片质量信息获取方法、系统及设备

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JPH10165382A (ja) * 1996-12-16 1998-06-23 Sony Corp 生体検知装置
JPH11197135A (ja) * 1998-01-16 1999-07-27 Sony Corp 指紋画像入力装置及び指紋照合装置
JP2000172833A (ja) * 1998-12-10 2000-06-23 Omron Corp 指紋照合装置
JP2003111749A (ja) * 2001-10-09 2003-04-15 Bmf:Kk ヒューマン判定装置
JP2004234245A (ja) * 2003-01-29 2004-08-19 Sony Corp 指紋照合装置

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JPH10302047A (ja) * 1997-04-25 1998-11-13 Sony Corp 指紋照合装置
JP2005143804A (ja) * 2003-11-14 2005-06-09 Glory Ltd 生体検知装置、生体検知方法および指紋認証装置

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Publication number Priority date Publication date Assignee Title
JPH10165382A (ja) * 1996-12-16 1998-06-23 Sony Corp 生体検知装置
JPH11197135A (ja) * 1998-01-16 1999-07-27 Sony Corp 指紋画像入力装置及び指紋照合装置
JP2000172833A (ja) * 1998-12-10 2000-06-23 Omron Corp 指紋照合装置
JP2003111749A (ja) * 2001-10-09 2003-04-15 Bmf:Kk ヒューマン判定装置
JP2004234245A (ja) * 2003-01-29 2004-08-19 Sony Corp 指紋照合装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010000224A (ja) * 2008-06-20 2010-01-07 Nippon Telegr & Teleph Corp <Ntt> 生体認識装置

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JPWO2008015725A1 (ja) 2009-12-17
JP4653222B2 (ja) 2011-03-16

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