WO2007140664A1 - récepteur et procédé pour la réception d'un signal sans fil - Google Patents

récepteur et procédé pour la réception d'un signal sans fil Download PDF

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Publication number
WO2007140664A1
WO2007140664A1 PCT/CN2006/003473 CN2006003473W WO2007140664A1 WO 2007140664 A1 WO2007140664 A1 WO 2007140664A1 CN 2006003473 W CN2006003473 W CN 2006003473W WO 2007140664 A1 WO2007140664 A1 WO 2007140664A1
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WO
WIPO (PCT)
Prior art keywords
amplitude
branch
module
correction
signal
Prior art date
Application number
PCT/CN2006/003473
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English (en)
French (fr)
Inventor
Siqing Ye
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to EP06828384.5A priority Critical patent/EP2023494B1/en
Publication of WO2007140664A1 publication Critical patent/WO2007140664A1/zh
Priority to US12/277,069 priority patent/US8194788B2/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits
    • H04L27/3845—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier
    • H04L27/3854—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
    • H04L27/3863—Compensation for quadrature error in the received signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/001—Digital control of analog signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • H04B2001/045—Circuits with power amplifiers with means for improving efficiency

Definitions

  • the present invention relates to wireless receiving technologies, and more particularly to a receiver and a method of receiving a wireless signal. Background of the invention
  • a wireless communication system or radar system it is necessary to receive a wireless signal by some means, which is commonly referred to as a wireless receiver or receiver.
  • a wireless receiver or receiver There are many types of receivers, and the dynamic range is an important indicator for measuring the pros and cons of the receiver.
  • the dynamic range of the receiver is generally divided into simultaneous dynamic range and non-simultaneous dynamic range.
  • the dynamic range is the simultaneous presence of a large signal and a small signal, and the receiver can correctly demodulate the large signal and the small signal at the same time, and the value is generally the maximum value of the large signal and small signal power ratio.
  • simultaneous dynamic range is the ability of the receiver to correctly demodulate signals that fluctuate over time, typically in the ratio of the maximum signal power to the minimum signal power that fluctuates.
  • the non-simultaneous dynamic range of the receiver is generally larger than its simultaneous dynamic range.
  • the receiver and the small signal are simultaneously input and the receiver can correctly demodulate, then when the large signal and the small signal are not simultaneously input, there is no mutual interference.
  • the problem is that the receiver is more capable of correct demodulation.
  • the receiver can use the Analog Automatic Gain Control (AAGC) technique to achieve the goal of extending the non-simultaneous dynamic range.
  • AAGC Analog Automatic Gain Control
  • AAGC technology can generally be divided into two categories: one is a single variable gain branch, and the other is a multiple fixed gain branch.
  • the idea of a single variable gain branch is to use a branch to transmit or process the received signal, but the gain of the branch is variable; and the idea of multiple fixed gain branches is to use multiple branches
  • the received signals are transmitted or processed simultaneously, but the gain of each branch is fixed and the gains of the different branches are different.
  • Figure 1 shows the basic block diagram of a receiver that receives wireless signals by a single variable gain branch technique.
  • the receiver of the single variable gain branch generally includes: an upstream analog receiving channel module, a variable gain analog receiving channel, an analog to digital converter, a power detection and AAGC control module, and a digital receiving channel module.
  • the upstream analog receive channel module generally includes a low noise amplifier, and may also include a mixer and a filter, and is mainly used for preprocessing the received input signal.
  • the upstream analog receives the input signal of the channel module, that is, the receiver input signal is an analog band pass signal. If the analog I&Q demodulation section is not included in the upstream analog receive channel module, the output is still an analog bandpass signal after the upstream analog receive channel module. If the upstream analog receive channel module contains the analog I&Q demodulation section, the output is Simulate I&Q signals.
  • the variable gain analog receive channel module generally includes a multi-stage mixing, filtering module, and amplification module, and can change its gain under the control of the power detection and AAGC control module.
  • Analog to digital converters are used to convert analog signals to digital signals.
  • the analog-to-digital converter includes one ADC, a single-channel analog-to-digital converter; and when the input is an analog I&Q signal, the analog-to-digital converter includes an I&Q two-way ADC. That is, a dual channel analog to digital converter.
  • the power detection and AAGC control module processes the signal output from the analog to digital converter module to obtain the signal power value, and then determines the gain configuration according to the signal power value, and then changes the variable gain analog reception under the control of the demodulation synchronization signal.
  • the gain of the channel is too small.
  • the digital receiving channel module is used for filtering, extracting, etc. the signal input from the analog to digital converter to obtain a baseband signal, and then demodulating the baseband signal to obtain a bit stream.
  • the digital receiving channel module will output one bit stream; if it is a multi-carrier receiver, it outputs multiple bit streams.
  • variable gain analog receive channel As can be seen from Figure 1, the variable gain analog receive channel, analog to digital converter, power sense and AAGC control form a feedback loop.
  • variable gain analog receive channel When the input signal is received through the upstream analog Channel module, variable gain analog receive channel, analog to digital converter, power detection and
  • the AAGC control module detects the magnitude of the input signal power and sets the variable gain analog receive channel to a suitable gain value based on the receiver's own dynamic range and a certain AAGC algorithm.
  • the disadvantages of the single-variable gain branch technique are: (1) Since the feedback loop is used to control the power of the input signal, a certain reaction time is required to change the gain of the receiver when the input signal changes, and the control speed is reacted. Time constraints. (2) The power detection and AAGC control module cannot update the gain at any time. Instead, the gain needs to be updated under the control of the synchronous demodulation signal, that is, the gain can be updated at the synchronization boundary. Otherwise, the gain of the analog device will change and The resulting phase changes affect the demodulation performance. This requires the receiver's gain to remain constant for the duration of the signal, ie, synchronous AAGC is required, which not only increases the complexity of the circuit, but also does not track channel changes quickly.
  • AAGC technology is a multi-fixed gain branching technique, which is characterized in that: instead of using a feedback loop to control the gain size, a plurality of fixed branches of different gain sizes are used to amplify the input signal. , then select the appropriate branch output, that is, switch between the branches.
  • Receivers based on multiple fixed gain branch techniques are generally divided into two types: one is a multi-fixed gain branch receiver that switches before demodulation, and the other is a multi-fixed gain branch that switches after demodulation. ⁇ Received.
  • FIG. 2 shows the basic block diagram of a multiple fixed gain branch receiver switched before demodulation.
  • the receiver generally includes: an upstream analog receiving channel module, M fixed gain branch modules, M analog to digital converters, M digital receiving channel front sections, a multi-branch synchronous switching module, and digital receiving.
  • the upstream analog receiving channel module is the same as the corresponding module of the single variable gain branch receiver, and is not described here.
  • fixed-gain tributary modules Compared with single-variable-gain tributary receivers, fixed-gain tributary modules generally include multi-stage mixing, filtering, and amplification modules, but the gain is fixed, and the gain between the M fixed-gain tributary modules is sequentially formed.
  • a certain step distribution, called step gain processing for example: the gain of the first branch is 80db, the second gain branch is 60db, and the third gain branch is 40db, and so on.
  • the adjacent two branches can also use the gain difference of unequal intervals.
  • Each analog to digital converter is the same as the corresponding module of the single variable gain branch receiver, and will not be described here.
  • the digital receiving channel module is configured to perform multiple filtering, decimation, etc. on the signal input by the analog to digital converter to obtain a baseband signal, and then demodulate the baseband signal to obtain a bit stream.
  • the digital receiving channel module is divided into two parts by the multi-branch synchronous switching module: one part is the front part of M digital receiving channels, and the other part is a number. Receive the back of the channel.
  • the front sections of the M digital receiving channels are for partially processing the signals input by the analog to digital converters, and then the multi-branch synchronous switching module performs synchronous switching under the control of the demodulated synchronous signals, and selects a branch with a suitable signal size.
  • the signal output is then further digitally processed by the digital receive channel, such as demodulation, and finally the bit stream is output.
  • the digital receive channel such as demodulation
  • bit stream is output.
  • the position of the multi-branch synchronous switching module in the middle of the digital receiving channel module is not strictly defined, and is related to the design of the actual receiver, but only before the demodulation processing.
  • the upstream analog receiving channel module When the multi-fixed gain branch receiver switched before demodulation receives the input signal, the upstream analog receiving channel module performs mixing, filtering, and amplifying processing, and then the signal is changed by M fixed gain branches respectively. The power level, and then the signal is filtered and extracted by M analog-to-digital converters respectively to obtain digital signals, and finally After passing through the front sections of the M digital receiving channels, and selecting a branch suitable for the size signal by the multi-branch synchronous switching module, the signal is demodulated and outputted by the rear section of the digital receiving channel;
  • the input signal of the multi-fixed gain branch receiver switched before demodulation is an analog band pass signal, if the upstream analog receive channel module and the fixed gain branch block include analog I&Q demodulation
  • the output of the fixed gain tributary module is an analog baseband signal, that is, two analog low-pass signals of I and Q; otherwise, the output signal is an analog band-pass signal.
  • analog to digital converters also include a single ADC and an I&Q dual ADC.
  • each digital receive channel outputs one bit stream; if it is a multi-carrier receiver, outputs multiple bit streams.
  • the disadvantages of the multi-fixed gain branch technique that is switched before demodulation are: (1) Since the switching performed before demodulation must be synchronous switching, that is, switching can be performed on the synchronization boundary of the received signal, which not only increases the complexity of the circuit. And it is not possible to switch the real-time tracking channel changes. (2) On the other hand, although the input signal is input to multiple branches at the same time, the circuit characteristics of the multiple branches are different, which causes the phase and amplitude of the respective branch signals to be the same at the same time before switching. On the other hand, the receiver generally demodulates the signal of the entire signal at the same time, so the time granularity of the switching is generally greater than the signal duration.
  • the output signal cannot be normal for the entire signal duration. This will affect the demodulation performance during the duration of the signal.
  • Figure 3 shows the basic structure of a multi-fixed gain branch receiver switched after demodulation.
  • the receiver is basically the same as the multi-fixed gain branch receiver switched before demodulation, except that the digital receiving channel module is not divided into two parts by the multi-drop switching module, the signal It is only after the full demodulation that the multi-drop switching module selects one signal.
  • the small suitable branch output "number. Since the synchronization signal can be obtained directly from the demodulated signal, the demodulation switching branch does not require a dedicated demodulation synchronization signal to control the switching.
  • the receiver may not include an upstream analog receiving channel, that is, the receiver input signal may be input into the fixed gain branch module.
  • the analog I&Q demodulation part may not be included in the upstream analog receiving channel module, but included in each fixed gain branch module, or the upstream analog receiving channel module and each fixed gain branch module do not include analog I&Q demodulation.
  • the digital I&Q signal is obtained from the digitally sampled digital bandpass signal by digital means.
  • the disadvantages of the multi-fixed gain branch technique for switching after demodulation are: (1) Since the receiver needs to be demodulated and switched first, such a receiver requires M digital receiving channel modules including a demodulating portion, which causes waste of resources. . (2) Like the multi-fixed gain branch technique switched before demodulation, the multi-fixed gain branch technique after demodulation still cannot solve the problem that the demodulation performance is degraded under the condition that the signal changes greatly during the signal duration. problem.
  • the invention provides a receiver and a method for receiving a wireless signal, which can switch between branches without special synchronization signal control, and can quickly track signal changes to ensure a sudden change of input signal during the duration of the signal. Demodulation performance.
  • the technical solution proposed by the invention is:
  • a receiver comprising at least a multi-branch correction pre-processing module and a digital receive channel rear segment, the receiver further comprising:
  • Multi-branch correction and switching module for M input by multi-branch correction pre-processing module
  • the digital baseband signal performs amplitude and phase correction, and selects one output to the rear of the digital receiving channel according to the switching strategy.
  • a wireless signal receiving method comprising the following steps:
  • the input signal of the receiver is subjected to multi-branch correction pre-processing to obtain a digital baseband signal whose M-channel has not undergone amplitude-phase correction;
  • the receiver and the method for receiving a wireless signal proposed by the present invention have the following advantages:
  • the amplitude and phase are consistent, and on the one hand, it can be switched at any time, or can be switched point by point without the control of the synchronization signal, reducing the synchronization circuit.
  • the complexity of the design On the other hand, if the input signal suddenly changes during the duration of the signal, it can also be switched immediately to achieve the purpose of quickly tracking the change of the signal.
  • the multi-channel digital baseband signal before the switching of the present invention is corrected, it can be switched between any two branches, does not affect the amplitude and phase continuity of the switched output signal, can increase the non-simultaneous dynamic range, and improve the solution. Adjust performance. -
  • FIG. 1 is a basic structural diagram of a receiver of a single variable gain branching technique in the prior art
  • FIG. 2 is a basic structure of a multi-fixed gain branching and receiving apparatus for switching before demodulation in the prior art
  • FIG. 3 is a basic structural diagram of a multi-fixed gain branch receiver that is switched after demodulation in the prior art
  • FIG. 4 is a basic structural diagram of a receiver according to an embodiment of the present invention.
  • Figure 5 is a schematic diagram showing the first internal structure of the multi-branch correction pre-processing module in the embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing a second internal structure of a multi-branch correction pre-processing module in an embodiment of the present invention.
  • Figure ⁇ is a third internal structure diagram of the multi-branch correction pre-processing module in the embodiment of the present invention.
  • FIG. 8 is a first internal structural diagram of a digital down conversion module according to an embodiment of the present invention
  • FIG. 8b is a second internal structure diagram of a digital down conversion module according to an embodiment of the present invention
  • FIG. 9 is an intermediate ladder of an embodiment of the present invention
  • FIG. 10 is a schematic structural diagram of an internal structure of a multi-branch correction and switching module according to an embodiment of the present invention
  • FIG. 11 is a schematic structural view of Embodiment 1 of the apparatus of the present invention.
  • Figure 12 is a schematic structural view of a second embodiment of the apparatus of the present invention.
  • Figure 13 is a schematic structural view of a third embodiment of the apparatus of the present invention.
  • FIG. 14 is a schematic diagram showing a first internal structure of a correction signal injection module in an embodiment of the present invention.
  • 15 is a schematic diagram showing a second internal structure of a correction signal injection module in an embodiment of the present invention.
  • Figure 16 is a schematic structural view of Embodiment 4 of the apparatus of the present invention.
  • 17 is a flowchart of a method for receiving a wireless signal according to an embodiment of the present invention.
  • FIG. 18 is a flowchart of a method for calculating an initial value of an amplitude correction coefficient in Embodiment 1 of the method of the present invention
  • Figure 19 is a flow chart of Embodiment 1 of the method of the present invention
  • FIG. 21 is a flowchart of a method for calculating an initial value of a filter coefficient in Embodiment 3 of the method of the present invention.
  • Figure 22 is a flow chart of the third embodiment of the method of the present invention. Mode for carrying out the invention
  • the basic idea of the invention is to add a multi-branch correction and switching module to the receiver, correct the amplitude and phase of the input signal of the multi-branch correction pre-processing module, and select a piece according to the condition of each branch signal before correction.
  • the branch output is digitally processed to the digital receive channel for output of the bit stream.
  • the receiver of the embodiment of the present invention includes at least:
  • the multi-branch correction pre-processing module 401 the multi-branch correction and switching module 402, and the digital receiving channel rear section 403.
  • the multi-branch correction pre-processing module 401 is configured to output the M-channel digital baseband signal to the multi-branch correction and switching module 402 after the receiver input signal is processed by the M-stage step gain and the digital baseband processing is obtained.
  • the acquisition of digital baseband processing described herein generally includes I&Q demodulation, sampling, and the like, and may also include amplification, mixing, and the like.
  • the multi-branch correction and switching module 402 is configured to perform amplitude and phase correction on the M-channel digital baseband signal input by the multi-branch correction pre-processing module 401, and select one signal to output to the digital receiving channel rear segment 403 according to the switching strategy.
  • Digital receive channel rear section 403 for input by multi-branch correction and switching module 402 a digital baseband signal for further digital processing to obtain and output a bit stream, ie a bit stream
  • the receiver input signal is an analog band-pass signal, and a sensor such as a receiver antenna may have a single carrier of a certain bandwidth, or may have multiple carriers of the same bandwidth or multiple carriers of different bandwidths.
  • the receiver input signal first needs to be processed into an M-channel digital baseband signal by the multi-branch correction pre-processing module 401. Since the process of processing the receiver input signal into the M-channel digital baseband signal is relatively complicated, for the sake of simplicity of description, the portion of the embodiment of the present invention that processes the receiver input signal into the M-channel digital baseband signal is collectively referred to as the multi-branch correction pre-processing module 401. . There are many ways to form the multi-branch correction pre-processing module 401.
  • the composition of the multi-branch correction pre-processing module 401 is roughly as shown in FIG. 5, FIG. 6, and FIG.
  • Digital baseband acquisition refers to the process of obtaining a digital baseband signal, the digital I&Q signal, from an analog bandpass signal.
  • the multi-branch correction pre-processing module 401 may include: an upstream analog receiving channel module 501 including analog I&Q demodulation functions, M dual-channel fixed gain branch modules 502, and M dual-channel analog-to-digital conversions. 503.
  • the upstream analog receiving channel module 501 including the analog I&Q demodulation function generally includes a low noise amplifier and an analog I&Q demodulation part, and may also include a mixing and filtering part, and is mainly used for amplifying the input signal, and
  • the analog bandpass signal is demodulated into an analog baseband_signal and output to the M dual channel fixed gain branch modules 502.
  • the M dual channel fixed gain tributary modules 502 include a dual channel fixed gain tributary module 502 #1 to a dual channel fixed gain tributary module 502 #M for input by an upstream analog receive channel module 501 containing analog I&Q demodulation functions.
  • the analog baseband signal is subjected to step gain processing, and the processed M-channel analog baseband signal is output to M two-channel analog-to-digital converters 503.
  • M dual-channel analog-to-digital converters 503 including dual-channel analog-to-digital converters 503 # 1 to dual channel analog to digital converter 503 # M, for sampling the analog baseband signal input by M dual channel fixed gain branch module 503, converting to digital baseband signal, and outputting to multi-branch correction And switching module 402.
  • the multi-branch correction pre-processing module 401 may also include M fixed gain branch modules 601 and M dual-channel analog-to-digital converters 602 including analog I&Q demodulation functions.
  • M fixed gain branch modules 601 including analog I&Q demodulation function include: fixed gain branch module 601 #1 with analog I&Q demodulation function to fixed gain branch module 601 # M with analog I&Q demodulation function And used to perform step gain processing including analog I&Q demodulation function on the receiver input signal, and output the processed M analog baseband signal to M two-channel analog-to-digital converters 602.
  • M dual-channel analog-to-digital converters 602 include dual-channel analog-to-digital converters 602 #1 to dual-channel analog-to-digital converters 602 #M for fixed gain branches from M with analog I&Q demodulation functions
  • the M-channel analog baseband signal input by the module 601 is sampled, converted into an M-channel digital baseband signal, and output to the multi-branch correction and switching module 402.
  • FIG. 6 may further include an upstream analog receiving channel module without analog I&Q demodulation function, and its connection relationship and function are similar to the upstream analog receiving channel module 501 with analog I&Q demodulation function in FIG. 5, except that It also includes the function of outputting analog J&Q signals after analog I&Q demodulation, instead of outputting analog bandpass signals. -
  • the multi-branch correction pre-processing module may further include: M single-channel fixed gain branch modules 701, M single-channel analog-to-digital converters 702, and digital I&Q demodulation section 703.
  • the M single-channel fixed gain branch module 701 and the M single-channel analog-to-digital converters 702 are similar in function and connection relationship to the corresponding modules in FIG. 6, except that the analog bandpass signals are processed instead of the analog I&Q signals.
  • the digital I&Q demodulation section 703 includes a digital down conversion module 7031 and a plurality of low pass filter modules 7032.
  • the digital down conversion module 7031 includes a DDC multiplier and a numerically controlled oscillator (NCO) for shifting the spectrum of the digital band pass signal input from the single-channel analog to digital converter 702 to a position of 0 frequency, and then outputting A low-pass filter process is performed on the low-pass filter module 7032 to obtain a digital digital baseband signal, that is, a digital digital complex signal, which is represented as a digital I&Q signal.
  • NCO numerically controlled oscillator
  • a digital I&Q signal is obtained. Since the modulus of the digital I&Q signal directly reflects the envelope shape of the receiver input signal, it can also be called a complex envelope. Figure 7 does not describe the I and Q signals separately, which means that one way is complex.
  • the internal structure of the digital down conversion module 7031 may be in the form of Fig. 8a or Fig. 8b.
  • the digital down conversion module 7031 may include M DDC multipliers and an NCO, and the M DDC multipliers respectively input M digital bandpass signals from the M single channel analog to digital converters 702 and The digital local oscillator signal input by the NCO is multiplied to complete the frequency shift and output to the M low pass filter modules 7032.
  • the digital down conversion module 7031 can also include M DDC multipliers and M NCOs, which function similarly to Fig. 8a, except that each DDC has a separate NCO, which is no longer obscured. _
  • FIG. 7 may further include an upstream analog receiving channel module without analog I&Q demodulation function, and its connection relationship and function are similar to the upstream analog receiving channel module 501 with analog I&Q demodulation function in FIG. 5, except that It also includes the function of outputting analog I&Q signals after analog I&Q demodulation, but outputs analog band-pass signals.
  • the receiver input signal is typically an analog bandpass signal that needs to be processed by the multi-branch correction pre-processing module 401 into a digital baseband signal.
  • I&Q demodulation it is in the stage of analog signal processing. This is done in the segment, or in the digital signal processing phase, which is related to the actual receiver design, and is no longer listed here.
  • the digital processing performed by the digital receiving channel rear stage 403 is different depending on the receiver input signal.
  • the digital receive channel back-end 403 needs to perform multiple steps of down-conversion, filtering, decimation, and demodulation, and then output multiple bit streams.
  • the digital receive channel back-end 403 needs to perform multiple steps of down-conversion, filtering, decimation, and demodulation, and then output multiple bit streams.
  • only one filtering, decimation, and demodulation processing is required, and then one bit stream is output.
  • the M fixed gain branches included in the multi-branch correction pre-processing module 401 may be a fixed gain branch including an analog I&Q demodulation function, or may be a dual-channel fixed gain branch module or a single
  • the channel is fixed to the gain branch module. Since the demodulation to analog baseband processing is performed once in the entire receive channel, the analog processing before the analog I&Q demodulation function is single-channel, and the analog processing after the analog I&Q demodulation function is dual-channel.
  • the dual-channel fixed-gain tributary module is located after the analog I&Q demodulation function.
  • the two parallel channels process the analog low-pass signals of I and Q respectively. Since the frequency is already mixed to the baseband, there is no mixing stage in the processing channel.
  • the input and output of the single-channel fixed-gain tributary module are analog band-pass signals, but the output signal frequency may have changed from the input signal frequency, that is, there may be one or even more stages of mixing processing in the processing channel.
  • M branches are fixed gains, and M branches form a certain gain step, so that the signals of the M branches at the same time are unsaturated. In the case of different amplitudes, for example, the amplitude of the output signal of the first branch is the largest, the amplitude of the output signal of the second branch is second, and so on.
  • step gain processing There are two general methods for step gain processing: One is the parallel method, which sets the gain of each fixed gain tributary module to a gain of different magnitude, and the M branches are completely parallel. The other is a stepped approach, as shown in Figure 9.
  • the common fixed gain stage module 901 is common to all branches. Increase in each branch The difference is mainly caused by the fixed gain step 1 module 902-1 ⁇ fixed gain step M-1 module 902-M-1.
  • the dedicated fixed gain stage 1 module 903-1 ⁇ dedicated fixed gain stage M module 902-M can take the same gain, or can take different gains to form a further gain difference.
  • All of the modules in Figure 9 may contain mixing stages. In order to reduce circuit complexity and increase resource sharing rate, as long as performance allows, all mixing stages should be placed in the upstream module as much as possible. If all the mixing stages are placed in the common fixed gain stage or the upstream circuit in Figure 9, the resources of the entire receiver will be saved the most, which is not much difference between the maximum gain branch and the minimum gain branch. The situation is entirely possible. However, in the case where the gain difference between the maximum gain branch and the minimum gain branch is large, the case of the mixing stage of the fixed gain step 1 to the fixed gain step M-1 in FIG. 9 is included, and the intermediate tap is taken out at this time. The corresponding mixing stage must be filled in the dedicated gain stage so that the output frequencies of all the branches are the same.
  • the internal structure of the multi-branch correction and switching module 402 is as shown in FIG. 10.
  • the multi-branch correction and switching module 402 includes at least: an amplitude phase correction module 1001, an M-channel selection one-way control module 1002, and an M-channel selection one-way module 1003.
  • the amplitude and phase correction module 1001 includes M amplitude and phase correction multipliers, that is, the amplitude and phase correction multiplier 1001 #1 to the amplitude and phase correction multiplier 1001 #M, for using the M input by the multi-branch correction pre-processing module 401.
  • the digital baseband signal and the amplitude and phase correction coefficient configured in itself are used to obtain the corrected M-channel digital baseband signal, and output to the M-channel 1-way module 1003.
  • the M-channel selection 1 channel control module 1002 is configured to determine a branch from the M-channel digital baseband signal input by the multi-branch correction pre-processing module 401 according to the switching strategy, generate a switching control signal carrying the branch number, and output Select 1 way module 1003 for M road.
  • the M-channel 1 module 1003 is configured to select one of the M digital baseband signals input by the amplitude-correcting module 1001 according to the switching control signal input by the M-channel selection control module 1002, and output the signal to the digital receiving channel.
  • the last paragraph 403. in order to correct the M-channel digital baseband signal input from the multi-branch correction pre-processing module 401 in the amplitude and phase correction module 1001, it is necessary to configure a corresponding amplitude and phase correction coefficient for each branch.
  • the function of the amplitude and phase correction multiplier is to perform complex multiplication of the digital baseband signal expressed as a complex number and the amplitude and phase correction coefficient expressed as a complex number to change the amplitude and phase of the digital baseband signal so that all amplitudes are sufficiently large and unsaturated.
  • the amplitude and phase of the digital baseband signal of the branch remain the same.
  • the signal amplitude is too small or too large, so that the branch below the sensitivity or saturation may not be able to match its amplitude and phase to the normal branch after correction, but it will not be used as an output according to the switching strategy.
  • the corrected digital baseband signal branch the correction of which will not be repeated here.
  • the amplitude and phase correction coefficients there are two ways to configure the amplitude and phase correction coefficients:
  • One is an offline configuration mode, that is, the initial values of the M amplitude and phase correction coefficients are pre-configured to the amplitude and phase correction module before the receiver starts to receive the wireless signal. 1001 and remains unchanged throughout the receiver's operation.
  • the pre-configuring the initial values of the M amplitude correction coefficients to the amplitude and phase correction module before starting to receive the wireless signal further includes two cases: First, the receiver is calculated according to the test result before leaving the factory. The initial value of the amplitude and phase correction coefficient is solidified into the amplitude and phase correction module.
  • the initial value of the amplitude and phase correction coefficient is calculated by the input signal, and is configured to the amplitude and phase correction module at one time.
  • the offline configuration mode is suitable for the case where the relative characteristics of the respective branch circuits of the receiver are relatively stable.
  • the relative characteristics described herein refer to the ratio of the transfer functions between the two branches, and the relative characteristics between the M branches refer to the ratio of the transfer functions between the M branches.
  • the circuit can be considered to be linear, that is, it can be described by a transfer function.
  • an online configuration method which means that after the power-on starts working, the receiver calculates the initial value of the amplitude-correction coefficient by using the input signal, and then configures it to the amplitude-phase correction module. Then, the receiver constantly recalculates the new amplitude and phase correction coefficients using the input signal periodically or irregularly to compensate for the change in the relative characteristics of the respective branch circuits over time.
  • an online configuration method It is suitable for the case where the relative characteristics of the respective branch circuits of the receiver are unstable.
  • the M amplitude and phase correction multipliers in the amplitude and phase correction module 1001 have two input terminals, one of which is input by the multi-branch correction pre-processing module 401, and the digital baseband signal is input.
  • the amplitude and phase correction coefficient register in module 1001 inputs the amplitude and phase correction factor.
  • the initial value of the amplitude and phase correction coefficient can be written into the amplitude correction coefficient register at one time; for the online configuration mode, the calculated new amplitude and phase correction coefficient is continuously written to the amplitude and phase correction. In the coefficient register.
  • the calculation of the M amplitude and phase correction coefficients can be performed by a similar method.
  • the relative characteristics of the respective branch circuits of the receiver are stable, and the initial value of the amplitude correction coefficient is calculated and written at one time before the receiver starts to receive the working signal, that is, the offline configuration method is used, and is working.
  • the value of the amplitude and phase correction factor is no longer changed during the process.
  • the receiver includes: an upstream analog receiving channel module 1101 including analog I&Q demodulation functions, M dual-channel fixed gain branch modules 1102, and M dual-channel analog-to-digital converters 1103.
  • the upstream analog receive channel module 1101 including an analog I&Q demodulation function includes a low noise amplifier and an analog I&Q demodulation section for performing upstream analog reception processing of the receiver input signal with analog I&Q demodulation function, that is, amplification, Mixing and other processing, and demodulating the analog bandpass signal into an analog baseband signal, and then outputting to the M dual-channel fixed gain branch module 1102.
  • M dual-channel fixed gain tributary module 1102 including Han channel fixed gain tributary module 1102 #1 to dual channel fixed gain tributary module 1102 # M, for stepped gain processing of the analog baseband signal input by the upstream analog receiving channel module 1101 including the analog I&Q demodulation function, and processing the processed M-channel analog baseband
  • the signal is output to M two-channel analog to digital converters 1103.
  • the analog baseband signal of each channel is a complex signal, including two parallel analog signals of I and Q.
  • the amplitude and phase correction module 1104 includes an amplitude and phase correction multiplier 1104 #1 to an amplitude and phase correction multiplier 1104 #M for configuring the digital baseband signal input by the M dual channel analog to digital converters 1103 and pre-configuring in itself
  • the amplitude and phase correction coefficients are used to obtain the corrected digital baseband signal and output to the M-channel 1-way module 1106.
  • the M-channel 1 control module 1105 is configured to determine a branch from the M digital baseband signals input by the M dual-channel analog to digital converters 1103 according to the switching strategy of the present invention, and generate a branch carrying the branch number.
  • the control signal is switched, and the switching control signal is output to the M-channel 1-way module 1106.
  • the M-channel 1 module 1106 is configured to select one of the M digital baseband signals input from the amplitude-correcting module 1104 according to the switching control signal input by the M-channel selection control module 1105, and output the signal to the digital receiving channel. Segment 1107.
  • the digital receiving channel rear section 1107 is used for further digital processing of the corrected one-way digital I&Q baseband input by the M-channel selection 1 module 1106 to obtain and output a bit stream.
  • the upstream analog receiving channel module 1101 including the analog I&Q demodulation function first amplifies the receiver input signal in the form of an analog bandpass signal.
  • the analog I&Q demodulation process is performed to obtain an analog baseband signal, which is output to M dual-channel fixed gain branch modules 1102; in the dual-channel fixed gain branch module 1102, the open-circuit analog I&Q signals are respectively supported by respective two-channel fixed gains.
  • the step module After the step module is processed by the step gain, it is output to a dual-channel analog-to-digital converter 1103; a dual-channel analog-to-digital converter 1103 samples the input analog analog baseband signal to obtain a digital baseband signal, and The signal is output to the amplitude and phase correction module 1104 and the first channel control module 1105.
  • the amplitude and phase correction module 1104 performs amplitude and phase correction on the input signal, so that the digital baseband signals between the branches are consistent in amplitude and phase, and output to the UI.
  • the circuit selects 1 module 1106; the ⁇ 1 channel control module 1105 determines the branch of the signal with the largest amplitude but not the saturation according to the digital digital baseband signal and the switching strategy input by the two-channel analog-to-digital converter 1103.
  • the road is notified to the bypass circuit selection module 1106 by the switching control signal carrying the branch road number; the circuit selection 1 channel module 1106 is selected according to the channel selection control module 1105
  • the input switching control signal selects a corrected digital baseband signal and outputs it to the digital receiving channel rear segment 1107; the digital receiving channel rear segment 1107 further filters the corrected digital baseband signal input by the chirped circuit selection 1 module 1106 Digital processing such as decimation, demodulation, etc., to obtain and output a bit stream.
  • the receiver may not include the upstream analog receiving channel module 1101 including the analog I&Q demodulation function, but replace the M dual-channel fixed gain branch modules 1102 with M fixed analog I&Q demodulation functions.
  • the gain branch module the inventive solution can also be implemented.
  • the digital baseband signals between all the sufficiently large and unsaturated branches can be aligned in amplitude and phase, and point-by-point switching can be realized to achieve fast tracking of signal changes.
  • Device embodiment 2
  • the receiver uses an online configuration method to configure an initial value of the amplitude and phase correction coefficient. And during the operation of the receiver, the new amplitude and phase correction coefficients are continuously recalculated and written according to changes in the receiver input signal.
  • the receiver includes: M fixed gain tributary modules 1201 including analog I&Q demodulation functions, M dual-channel analog-to-digital converters 1202, M decimation filter modules 1203, M amplitude and phase correction feedforward loop delay compensation module 1204, amplitude and phase correction module 1205, amplitude and phase correction coefficient calculation module 1206, M channel selection 1 channel control module 1207, switching feedforward loop delay compensation module 1208, M path selection 1 way module 1209, digital receiving channel rear section 1210.
  • M fixed gain tributary modules 1201 with analog I&Q demodulation function M dual-channel analog-to-digital converters 1202, amplitude phase correction module 1205, M-channel selection 1 control module 1207, M-channel 1 module 1209.
  • the digital receiving channel rear section 1210 has the same function as the corresponding module in the first embodiment of the apparatus, and the difference is that: M fixed gain tributary modules 1201 including analog I&Q demodulation function can not only perform step gain processing on the receiver input signal. And analog I&Q demodulation can be performed; the M-channel 1-way control module 1207 will also generate a switching flag signal according to the switching strategy.
  • M decimation filter modules 1203 are configured to further extract the digital baseband signals input by the M dual-channel analog-to-digital converters 1202, and output them to M amplitude-corrected feedforward loops.
  • the M amplitude and phase correction feedforward loop delay compensation module 1204 is configured to delay compensate the digital baseband signals input by the M decimation filter modules 1203, and output the signals to the amplitude and phase correction module 1205.
  • the amplitude and phase correction coefficient calculation module 1206 is configured to perform amplitude phase correction coefficient calculation according to the digital baseband signal input by the M decimation filter modules 1203, and calculate according to the switching flag signal input by the M channel selection 1 channel control module 1207.
  • the amplitude and phase correction coefficient is output to the amplitude Phase correction module 1205.
  • the amplitude and phase correction coefficient calculation module 1206 can also calculate the amplitude and phase correction coefficient according to the amplitude-corrected digital baseband signal input by the amplitude and phase correction module 1205, and input according to the M-channel selection and control module 1207.
  • the switching flag signal outputs the calculated amplitude and phase correction coefficient to the amplitude and phase correction module 1205, that is, constitutes a feedback loop.
  • the amplitude and phase correction coefficient calculation module 1206 performs the calculation of the amplitude and phase correction coefficients according to the digital baseband signal input by the amplitude and phase correction module 1205, since the digital baseband signal at this time has undergone the amplitude and phase correction, When calculating the new amplitude and phase correction factor, it is necessary to remove the influence of the original amplitude and phase correction coefficient.
  • the feedforward loop delay compensation module 1208 is configured to delay the switching control signal input by the M-channel selection control module 1207, and output the signal to the M-channel selection 1 module 1209.
  • the receiver input signal is first input to the M fixed-gain tributary module 1201 including the analog I&Q demodulation function, and the step gain processing and the analog I&Q demodulation process are performed to obtain the simulation.
  • the baseband signal is then output to the M analog to digital converters 1202.
  • the M analog to digital converters 1202 sample the input M analog baseband signals to obtain a digital baseband signal, and output the signals to the M decimation filter modules.
  • M decimation filter modules 1203 extract signals and output to M amplitude and phase correction feedforward loop delay compensation module 1204, amplitude phase correction coefficient calculation module 1206 and M channel selection 1 control module 1207;
  • the amplitude and phase correction feedforward loop delay compensation module 1204 delays the input signal and outputs it to the amplitude and phase correction module 1205.
  • the amplitude and phase correction coefficient calculation module 1206 calculates the M digital baseband signal input by the M decimation filter modules 1203.
  • M-channel selection 1 control module 1207 determines a branch according to the switching strategy, generates a switching control signal and outputs it to the M-channel selection 1 module 1208, Generating a flag signal if the switch is determined to be switched according to the new branch, and the switching flag signal to the amplitude and phase correction coefficient calculating module 1206; amplitude and phase correction coefficient calculating module 1206 according to mux M
  • the switching flag signal input by the 1-way control module 1207 configures the calculated M amplitude and phase correction coefficients to the amplitude and phase correction module 1205; the amplitude and phase correction module 1205 inputs according to the M amplitude and phase-corrected feedforward ring delay compensation module 1204.
  • the M-channel digital baseband signal is multiplied by the amplitude-correction coefficient input by the amplitude-correction coefficient calculation module 1206, so that the digital baseband signals between the branches are consistent in amplitude and phase, that is, the amplitude-phase correction is completed, and
  • the output is to the M-channel 1 module 1209; the M-channel 1 module 1209 selects a digital baseband signal according to the delay-compensated switching control signal input by the switching feedforward loop delay compensation module 1208, and outputs the digital baseband signal to the digital receiving channel.
  • the rear stage 1210; the digital receiving channel rear section 1210 performs a digital processing of a digital baseband signal input by the M-channel selection 1 module 1209 for further extraction, filtering, and demodulation, and finally obtains and outputs a bit stream.
  • M includes analog I&Q solutions.
  • Fixed gain branch module 1201 M analog to digital converter 1202, amplitude phase correction module 1205, amplitude phase correction coefficient calculation module 1206, M channel selection 1 channel control module 1207, M channel selection 1 channel module 1209, The digital receiving channel rear section 1210 is necessary, and other modules can be traded according to actual conditions.
  • M decimation filter modules 1203 may be added, that is, the signals to be calculated are first extracted, and the signals of the modules such as the input amplitude and phase correction module 1205 and the amplitude and phase correction coefficient calculation module 1206 are passed. The rate is reduced, reducing the digital processing capacity of the module and the demand for resources.
  • the current sample or the sample of the current amplitude correction coefficient can be amplitude-corrected by the amplitude and phase correction module 1205, FIG.
  • the M amplitude and phase correction feedforward loop delay compensation module 1204 is used to compensate for the delay caused by the amplitude phase correction coefficient calculation.
  • M The amplitude and phase correction feedforward loop delay compensation module 1204 can also be located between the amplitude and phase correction coefficient calculation module 1206 and the amplitude and phase correction module 1205, that is, the M amplitude and phase correction feedforward loop delay compensation modules 1204 are used for
  • the M amplitude and phase correction coefficients input by the correction coefficient calculation module 1206 are subjected to time delay compensation, and then output to the amplitude and phase correction module 1205.
  • the delay generated by the amplitude phase correction coefficient calculation is equal to the delay of the amplitude and phase correction module, it may not be necessary.
  • the function of the switching feedforward loop delay compensation module 1208 is to ensure that the switching control signal corresponding to the same sample and the corrected M-channel digital baseband signal can simultaneously reach the M-channel selection module.
  • the switching feedforward loop delay compensation module 1208 module in FIG. 12 is located between the M-channel 1-way control module 1207 and the M-channel 1-way module 1209, and is suitable for M amplitude-phase-corrected feedforward loop delay compensation modules 1204 and The total processing delay of the amplitude and phase correction module 1205 is greater than the assumption of the processing delay of the M-channel 1-way control module 1207.
  • the total processing delay of the M amplitude-amplitude feedforward loop delay compensation module 1204 and the amplitude-phase correction module 1205 is exactly equal to the processing delay of the M-channel 1-way control module 1207, and is not used.
  • the feedforward loop delay compensation is performed, that is, the feedforward loop delay compensation module 1208 does not need to be switched.
  • the feedforward loop delay is switched.
  • the compensation module 1208 must be located on the signal path. Since the M amplitude and phase correction feedforward loop delay compensation module 1204, the amplitude and phase correction module 1205, and the amplitude and phase correction coefficient calculation module 1206 constitute a feedforward loop, the timing of the feedforward loop is not corrected for the amplitude and phase.
  • the delay compensation generates coupling
  • the switching feedforward loop delay compensation module 1208 module is preferably inserted outside the feedforward loop, that is, the connection relationship may be: M decimation filter modules 1203 output the extracted M digital baseband signals to Switching feedforward loop delay compensation module 1208 and M way selection 1 way control module 1207; switching feedforward loop delay compensation module 1208 will extract M
  • M decimation filter modules 1203 output the extracted M digital baseband signals to Switching feedforward loop delay compensation module 1208 and M way selection 1 way control module 1207; switching feedforward loop delay compensation module 1208 will extract M
  • the M-channel digital baseband signal input by the filter module 1203 is time-delay compensated, and then output to the M amplitude-phase-corrected feedforward loop delay compensation module 1204 modules, and the connection relationship of other modules remains unchanged.
  • connection relationship may also be:
  • the amplitude and phase correction module 1205 outputs the corrected M-channel digital baseband signal to the switching feedforward loop delay compensation module 1208; and the delay is compensated by the switching feedforward loop delay compensation module 1208, and then outputs The M path selects the 1 module 1209, and the other connection relationships remain unchanged.
  • the switching feedforward loop delay compensation module 1208 is placed before the M decimation filter modules 1203 and M amplitude and phase corrections.
  • the feed loop delay compensation module 1204 can save resources between modules.
  • each branch circuit In practical applications, if the relative amplitude and phase characteristics of each branch circuit are stable, only the receiver needs to configure the calculated amplitude and phase correction coefficient to the amplitude and phase correction module 1205 at the time of initialization, and it can be changed later. There is no amplitude phase correction coefficient calculation module 1206.
  • the amplitude and phase correction coefficient calculation module 1206 when the amplitude and phase correction coefficient calculation module 1206 receives the switching flag signal input by the M-channel selection control module 1207, the most recently calculated amplitude and phase correction coefficient can be immediately configured to the amplitude and phase correction module 1205.
  • the amplitude and phase correction coefficient calculation module 1206 may configure the new amplitude and phase correction coefficient to the amplitude only after the amplitude and phase correction coefficient calculation module 1206 has calculated the new amplitude and phase correction coefficient since the last time the amplitude correction coefficient was configured.
  • Phase correction module 1205. Device embodiment three
  • the receiver adopts an online configuration method to configure an initial value of the amplitude and phase correction coefficient, and can recalculate the amplitude and phase correction coefficient according to the obtained M digital baseband signal in the process of receiving the wireless signal, and the new amplitude and phase
  • the value of the correction factor is assigned to the amplitude and phase correction module, and then the amplitude and phase correction module will use the new value of the amplitude correction coefficient for correction processing.
  • the receiver includes: a correction signal injection module 1301. M single-channel fixed gain tributary modules 1302, M single-channel analog-to-digital converters 1303, delay correction module 1304, M decimating modules 1305, M amplitude-phase-corrected feedforward loop delay compensation modules 1306, amplitude and phase The correction module 1307, the amplitude and phase correction coefficient calculation module 1308, the M-channel selection 1 control module 1309, the switching feedforward loop delay compensation module 1310, the M-channel selection 1-way module 1311, and the digital reception channel rear-end 1312.
  • M single-channel fixed gain branch module 1302 M single-channel analog-to-digital converters 1303, M amplitude and phase-corrected feedforward loop delay compensation module 1306, amplitude and phase correction module 1307, amplitude and phase correction coefficient calculation module 1308, M-channel selection 1 control module 1309, switching feedforward loop delay compensation module 1310, M-channel selection 1-way module 1311, and digital reception channel rear-segment 1312 are similar to the modules corresponding to device implementation 2, the main differences are: M extracting modules 1305 are used for extracting the input M digital baseband signals without filtering; M single-channel fixed gain branch modules 1302 do not include analog I&Q demodulation functions; M single-channel analog to digital conversions Each of the devices 1303 has only one ADC.
  • the delay correction module 1304 includes a digital down conversion module 1304S!, M low pass filter modules 1304S 2 , a delay correction coefficient calculation module 1304S 3 , and a filter coefficient calculation module 1304S 4 ;
  • the correction module 1304 is configured to perform digital I&Q demodulation processing and delay correction processing according to the digital band-pass signals input by the M analog-to-digital converters 1303, and obtain digital baseband signals that are completely consistent in time, and output to the M extraction modules. 1305. -. .
  • the M low-pass filter modules 1304S 2 are the digital I&Q demodulation portion 703 in the figure, which is a part of the multi-branch correction pre-processing module 401, and the digital I&Q demodulation portion 703 is used in the present embodiment for delay.
  • Correction for the sake of uniformity in name, the digital I&Q demodulation section 703, the delay correction coefficient calculation module 1304S 3, and the filter coefficient calculation module 1304S 4 may also be collectively referred to as a delay correction module 1304.
  • the delay correction module 1304 can implement the principle of delay correction: the digital down conversion module 1304S! shifts the frequency of the digital band pass signals from the M single channel analog to digital converters 1303 to the center frequency.
  • M low-pass filter modules 1304S 2 0 frequency position, and output M low-pass filter modules 1304S 2 ; M low-pass filter modules 1304S 2 low-pass filter the input signal to filter out digital image and other interference signals, according to filter coefficients Performing delay correction to obtain IV [channel digital baseband signal, output to M extraction module 1305 and delay correction coefficient calculation module 1304S 3 ; delay correction coefficient calculation module 1304S 3 input according to M low-pass filter modules 1304S 2
  • the M-channel digital baseband signal signal calculates the delay correction coefficient of the M-channel signal, and outputs the delay correction coefficient to the filter coefficient calculation module 1 3 04S 4 , the filter coefficient calculation unit 1304S 4 according to the input delay correction coefficient
  • the filter coefficients are calculated and then assigned to the M low pass filter modules 1304S 2 .
  • the description of the digital I&Q signal obtained in this paper is based on the sequence of digital down-conversion and low-pass filtering.
  • obtaining digital I&Q signals can use the order of first-side bandpass filtering followed by digital downconversion. That is, M single-channel analog-to-digital converters 1303 can output digital band-pass signals to M single-sidebandpass filter modules, and perform single-side bandpass filtering and delay correction through M single-sidebandpass filter modules. After that, it is output to the digital down-conversion module 1304S.
  • the single-side bandpass filter is a complex filter. It is based on the Nyquist bandwidth in the frequency range between the half of the negative sampling frequency and the half of the positive sampling frequency.
  • the filter coefficients for delay correction are also changed correspondingly due to changes in filter form and processing order.
  • the offline configuration method can be used to configure the filter coefficients. Initial value. That is to say, in practical applications, the delay correction coefficient calculation module may not be included.
  • the 1304S 3 and filter coefficient calculation module 1304S 4 saves the delay correction coefficients in advance in the M low pass filters.
  • Non-volatile devices such as EPROM and FLASH can be used to cure in a low-pass filter, or a low-pass filter can be written once at power-on and reset.
  • correction signal injection module 1301 is configured to generate a signal for correction when the receiver is initialized or idle, and output it to the M fixed gain branch modules 1302.
  • the correction signal injection module 1301 includes a switch module 1401 and a correction signal generation module 1402.
  • the switch module 1401 is configured to output a receiver input signal received from a sensor such as an antenna and a correction signal generated by the correction signal generating module 1402 to the M fixed gain branch modules 1302.
  • the switch module 1401 needs to transmit the above two signals in a time-sharing manner, and must output the receiver input signal when there is a receiver input signal, and can output a correction signal for the calculation of the correction coefficient when the receiver is initialized or when the receiver is idle.
  • the switch module 1401 can be implemented with an electronic switch, and the correction signal generating module 1402 can be implemented with an oscillator. As for how the switch module transmits different signals in time division, it can be controlled by the system timing signal in the receiver, which is relatively easy to implement, and will not be described here.
  • the correction signal injection module 1301 may also include a switch module 1501 and a correction signal conversion module 1502, and FIG. 14 is similar to FIG. 15, and its area is mainly: if - in practical applications, the receiver is transmitting and transmitting If the machine coexists, then the correction signal may not be generated by the oscillator itself, but the signal to be transmitted by the transmitter when transmitting the signal is input to the correction signal conversion module 1502, and the correction signal conversion module 1502 converts the signal input by the transmitter into a signal. Signal for correction.
  • the receiver since the delay correction and the amplitude and phase correction are required, M single-channel fixed gain branch modules 1302, M single-channel analog-to-digital converters 1303, and digital
  • the down conversion module 1304S M low pass filter module 1304S 2 , the amplitude phase correction module 1307, the M way 1 control module 1309, the M way 1 module 1311, the digital receive channel 1312 are necessary, and other Modules can be arbitrarily chosen according to the actual situation.
  • the receiver may further include an upstream analog receiving channel module without analog I&Q demodulation function, and its function and connection relationship are similar to corresponding modules in the first embodiment of the apparatus, but only without analog I&Q demodulation.
  • the function, that is, the input of the switch module 1401 of the correction signal injection module 1301 is from the upstream analog receive channel module and the correction signal generation module 1402 or the correction signal conversion module 1502 without the analog I&Q demodulation function, and details are not described herein again.
  • Device embodiment four the input of the switch module 1401 of the correction signal injection module 1301 is from the upstream analog receive channel module and the correction signal generation module 1402 or the correction signal conversion module 1502 without the analog I&Q demodulation function, and details are not described herein again.
  • the receiver includes: a correction signal injection module 1601, M fixed gain branch modules 1602 including analog I&Q demodulation functions, M joy channel analog to digital converters 1603, and delay Correction module 1604, M extraction modules 1605, M amplitude and phase correction feedforward loop delay compensation modules 1606, amplitude and phase correction module 1607, amplitude and phase correction coefficient calculation module 1608, M channel selection 1 channel control module 1609, switching feedforward The ring delay compensation module 1610, the M-channel selection 1-way module 1611, and the digital reception channel rear-end 1612.
  • the fixed gain branch module of the embodiment is a fixed gain branch module with analog I&Q demodulation function, that is, M fixed gains including analog I&Q demodulation functions.
  • the branch module 1602 so the digital I&Q demodulation portion is not included in this embodiment; since the low-pass filter of the digital I&Q demodulation portion cannot be used for delay correction in this embodiment, it is necessary to add M low in the receiver.
  • the pass filter module 1604Si, the delay correction coefficient calculation module 1604S 2 , and the filter coefficient calculation module 1604S 3 .
  • the delay correction coefficient calculation module 1604S 2 and the filter coefficient calculation module 1604S 3 can be arbitrarily selected according to actual conditions, as in the third embodiment.
  • a DC and I&Q balance correction module is added between the correction module 1604 for removing circuit errors.
  • the circuit errors described herein include DC errors in the I and Q signals introduced by the circuit, and between the I and Q paths. Amplitude and phase error.
  • the multi-branch correction pre-processing module 401 is used to implement I&Q demodulation; whether the initial value of the amplitude-phase correction coefficient in the multi-branch correction and switching module 402 is an offline configuration method or an online configuration
  • the method includes whether the amplitude and phase correction coefficient calculation module is included; whether the fixed gain branch module is parallel or stepped; whether the signal needs to be extracted; whether the delay compensation needs to be performed during the operation of the receiver;
  • the signal before the amplitude and phase correction is time-delay corrected; whether the delay correction coefficient is an offline configuration method or an online configuration method, that is, whether the delay correction coefficient calculation module and the filter coefficient calculation module are included; whether DC and I&Q balance correction are included
  • the module; whether or not the correction signal injection module is included is related to the actual design of the receiver, and different combinations can be generated according to the actual situation, and here is no longer - a device structure that can be composed of a combination of these cases.
  • the receiver input signal in the form of an analog band pass signal can be processed into a digital baseband signal aligned in time, amplitude, and phase, and then one output is selected according to the switching strategy. Since the time, amplitude and phase of the signal are corrected according to the invention, when switching from the current one branch to another branch according to the switching strategy, the point can be switched point by point, that is, the time granularity of the switching is smaller than the number.
  • the time distance between the two samples of the baseband signal can achieve the purpose of quickly tracking the signal change, thereby increasing the non-simultaneous dynamic range and improving the performance of the receiver.
  • the present invention also provides a method for implementing receiving a wireless signal, the core idea of which is that the receiver processes the receiver input signal into an M-channel digital baseband signal. After the number, the M-channel digital baseband signal is first corrected for amplitude and phase, and then one output is selected according to the switching strategy, and finally digital processing is performed to obtain the bit stream.
  • FIG. 17 is a flow chart of a method for implementing a wireless signal in accordance with an embodiment of the present invention. As shown in FIG. 17, the method for receiving a wireless signal according to an embodiment of the present invention includes the following steps:
  • Step 1701 The multi-branch correction pre-processing module converts the receiver input signal into an M-channel digital baseband signal and outputs it to the multi-branch correction and switching module.
  • the multi-branch correction pre-processing module generally converts the receiver input signal in the form of an analog band-pass signal into a digital baseband signal by means of step gain processing, baseband demodulation, digital sampling, and the like.
  • Step 1702 The multi-branch correction and switching module performs amplitude and phase correction on the obtained M-channel digital baseband signal, and selects one digital baseband signal to output to the rear of the digital receiving channel according to the switching strategy.
  • Step 1703 The digital receiving channel is further digitally processed for the input digital baseband signal, and the bit stream is output.
  • the circuit in the case where the amplitude of the branch output signal is relatively large and not saturated, the circuit can be considered to be linear and can be described by a transfer function.
  • the transmission function of each branch is in the form of:
  • A(/)l ex p (/)) where / represents the signal frequency, represents the phase, and i represents the branch number corresponding to the branch, l ⁇ i ⁇ M.
  • the M-channel digital baseband signals obtained by the multi-branch correction pre-processing module are amplitude- and phase-corrected so that the amplitudes and phases of the signals in all the branches are sufficiently large and unsaturation, It can achieve point-by-point switching when selecting one output signal from M path, and quickly track signal changes.
  • the multi-branch correction pre-processing method may have the following methods:
  • the upstream analog receive channel module with analog I&Q demodulation function amplifies, mixes, and simulates I&Q demodulation of the analog bandpass signal, converts the receiver input signal into an analog baseband signal, and outputs M pairs of dual-channel fixed-gain tributary modules; M dual-channel fixed-gain tributary modules perform analog step-band gain processing through M branches and then output to M dual-channel analog-to-digital converters; M pairs The channel analog to digital converter samples the analog baseband signal to obtain a digital baseband signal.
  • M fixed-gain tributary modules with analog I&Q demodulation function first pass the analog band-pass signal through the M-branch with analog I&Q demodulation function for step gain processing to obtain the M-channel analog baseband signal. And output to M dual-channel analog-to-digital converters; M dual-channel analog-to-digital converters sample the analog baseband signals to obtain digital baseband signals.
  • M single-channel fixed gain tributary modules first pass the analog bandpass signal through the M branches for step gain processing and output to M single-channel analog-to-digital converters; M single-channel analog The digital converter converts the analog bandpass signal to obtain an M digital bandpass signal and outputs it to the digital I&Q demodulation section; the digital I&Q demodulation section performs the digital I&Q demodulation process on the M digital bandpass signal to obtain Digital baseband signal.
  • the present invention may first perform processing such as amplification and mixing of the receiver input signal before performing the step gain processing.
  • the signal input by the receiver is an analog band-pass signal, which is a real signal. It is a necessary step for the receiver to perform I&Q demodulation, which is to convert the real signal into a complex signal.
  • the "demodulation" word in the I&Q demodulation of the present invention is not a signal symbol on the constellation diagram before the restoration of modulation in the usual sense, but refers to shifting the carrier center frequency of the band-pass signal first. The process of obtaining an I&Q signal by going to the position of 0 frequency and then performing low-pass filtering to filter out the image and other interfering signals.
  • the 0 frequency here is 0 Hz. If frequency shifting and analog low-pass filtering are performed during the analog signal processing phase, it is analog I&Q demodulation; if frequency shifting and digital low-pass filtering are performed during the digital signal processing phase, it is digital I&Q demodulation.
  • the received digital baseband signal needs to be further down-converted in the digital receiver channel back-end module, that is, the center frequency of each carrier is respectively shifted to 0.
  • the position of the frequency is further filtered and deciphered to obtain an illuminating baseband signal corresponding to a plurality of carriers, and finally demodulated to obtain a multi-bit stream.
  • a single-carrier receiver that is, the receiver input signal has only one carrier
  • I&Q demodulation a unique baseband signal can be obtained, and there is no need to down-convert the module in the digital receiver channel, but only need to perform filtering. , extract processing, and then demodulate to obtain a bit stream.
  • the modulus of the digital baseband signal reflects the envelope of the receiver input signal in shape Shape, so digital baseband signals are often referred to as complex envelopes.
  • the following samples, digital baseband signals or complex envelopes of the present invention have the same meaning.
  • the sample point is each sampling point of the digital baseband signal
  • the power of the sample point is the power of the complex envelope of the sample point.
  • the multi-branch correction and switching module performs amplitude and phase correction on the M-channel digital baseband signal, and the key is to configure the amplitude-phase correction coefficient for the amplitude-phase correction module.
  • the method of configuring the positive phase coefficient is generally divided into two types: one is the offline configuration mode, and the other is the online configuration mode. But 'no matter which way, the calculation process of the amplitude and phase correction coefficients is similar.
  • the gains of the M branches are respectively GG M , wherein the gain of the first branch is the highest, the gain of the second branch is second, and so on.
  • the gain of the Mth branch is minimal.
  • the first branch and the second branch are the first pair of adjacent branch pairs, and the gain difference is ( ⁇ - G 2 , for; the second branch and the third branch)
  • the gain difference is AG 2 ; and so on, the M-1 branch and the Mth branch are the M - 1 pairs of adjacent branch pairs, and the gain difference is M M — X .
  • k denotes the kth branch
  • n denotes the nth sample, and it is assumed that the sample is after the extraction with the decimation rate ?, that is, the sample interval is ?r s .
  • the power of 3 ⁇ 4(/7) is defined as 101og 10 j3 ⁇ 4 (n)
  • the method for calculating the amplitude phase correction coefficient comprises the following steps: Step 1: Each adjacent branch pair performs screening on the input sample to determine a sample point to be used for performing relative amplitude phase correction calculation.
  • the same sample processed by the multi-branch correction pre-processing module 401 is different in amplitude and phase, and if the same sample is calculated on the M branches, The difference between the amplitude and the phase, then the amplitude and phase of each branch can be compensated differently, so that the digital baseband signals on the compensated M branches are consistent in amplitude and phase, thereby achieving the purpose of correction.
  • AP represents amplitude phase correction, indicating the envelope of the kth branch
  • the backoff value, [- ⁇ - w ⁇ -BCi ⁇ ) represents the amplitude and phase correction window of the high gain branch of the kth pair of adjacent branch pairs, [-BCE k - W ⁇ - G. -BCE, indicating the kth Amplitude and phase correction window for the low gain branch of the adjacent branch pair.
  • A indicates that the kth pair of adjacent branches corrects the window width of the amplitude and phase, and the minimum can be close to 0, and the maximum can be taken as infinity.
  • Step 2 Calculate the current power value iteration of the high gain branch according to the last power value iteration of the middle and high gain branches of each adjacent branch and the current sample power value of the high gain branch, according to the adjacent
  • the current power value iteration of the branch-to-low-gain branch and the current sample power of the low-gain branch to calculate the current power value of the low-gain branch iterative sum, according to the last mutual pair of adjacent branch pairs
  • the correlation value iteration sum and the current sample cross-correlation value are used to calculate the iterative sum of the adjacent branches to the current cross-correlation value.
  • ⁇ ( ⁇ ) indicates the sample number when the kth pair of adjacent branches is calculated for the current amplitude correction coefficient, that is, the amplitude phase correction window of the nth sample falls on the kth pair of adjacent branch pairs Medium, and the nth sample is the first time to fall into the amplitude phase correction window of the kth pair of adjacent branch pairs;
  • P k , H JAP , , ) and P k , H - 1) are adjacent Branch road centering high gain branch line and number AP, k 1 power value iteration sum, that is, the current power value iteration of the high gain branch and the last power value iteration of the high gain branch;
  • P k , L (l ⁇ ) and P k , L l ⁇ k - 1) respectively represent the iterative sum of the first and the first power values of the low gain branch of the adjacent branch pair, that is, the current power value iteration of the low gain branch and the last power value iteration; (l ⁇ ) and R
  • the power value iteration of the high gain branch, the power value iteration of the low gain branch, and the initial value of the cross-correlation value of the adjacent branch pair are set to 0, ie, after power up or reset, P k , H W
  • the values of ⁇ (0) and ? ⁇ (0) are 0.
  • RAP AP, / ) (1 - AP, k QAPJC )) X k ( N AP ( ⁇ AP,k )) ⁇ ⁇ ( N AP ( ⁇ AP,k )) + A AP,k H,k ) ⁇ AP , k ( ⁇ AP,k
  • ' represents the filter last value weight of the kth pair of adjacent branch pairs
  • the cylinder is called ⁇ - coefficient, represents the signal value of the first sample, the conjugate of the table,
  • the time interval of the amplitude phase correction window samples of the adjacent pair of the adjacent pairs of the kth pair should be relatively large, that is, "AP (JAP) - "The value of APU T S is relatively large, then ( ⁇ ) ⁇ ((' ⁇ ( ⁇ )- ⁇ ( ⁇ - is a positive number close to 0).
  • the conversion of "U-" (/ ⁇ - 1) to ⁇ ⁇ ) - " ⁇ (! k -1))RT S ) can be generated because it is directly used for alpha filtering for computational complexity.
  • the value of 1) can be obtained by using the counter, that is, the counter is incremented by 1 every s s , and when the new power integrated value needs to be calculated, it is recorded according to the counter.
  • ⁇ ( )- ⁇ ( ⁇ -i) is obtained directly from the conversion table ⁇ - ) and directly used to calculate the new power accumulation value, then clear the counter.
  • Step 3 Calculate the neighbor according to the current power value iteration of the high gain branch of the adjacent branch pair, the current power value iteration of the low gain branch, and the current correlation value of the adjacent branch pair. Relative amplitude and phase correction factor for the pair of branches.
  • ⁇ 1 ⁇ 22 represents the complex angle of the k-pair adjacent branch to the power multiplier of the high-gain branch relative to the low-gain branch.
  • the phase advancement of the kth pair of adjacent branch pairs of the high gain branch with respect to the low gain branch is indicated. Since the ratio of power is the square of the ratio of amplitudes, rk, L l AP, k
  • the amplitude of the output signal of the high and low gain branches is the same.
  • the output signal of the low gain branch is the kth
  • Step 4 Obtain the whole amplitude phase based on the relative amplitude and phase correction coefficients between all adjacent branches Correction coefficient.
  • the reference branch In order to calculate the overall amplitude and phase correction coefficient, it is necessary to determine a certain branch as a reference branch in advance, and the reference branch is fixed after it is determined. This branch is used as a reference branch each time the entire amplitude and phase correction coefficient is calculated. Each time the overall amplitude correction factor is calculated, the amplitude and phase correction coefficients of the reference branch are both 1, and remain unchanged. The remaining branches are recalculated based on the reference branch, and a new amplitude and phase correction coefficient is obtained. Assuming that the APREF branch is set as the reference branch, 1 ⁇ APREF ⁇ M, the calculation of the overall amplitude correction coefficient can be expressed by the following formula:
  • 7 , ,. represents the relative amplitude and phase correction coefficient of the pair of adjacent branches of the i-th pair, 1 ⁇ i ⁇ M-l.
  • the amplitude and phase correction coefficient of the kth branch is the kth pair to the APREF
  • Step 3 Step 2 to Step 3 are performed according to the third pair of adjacent branch pairs, and finally the calculation of the overall amplitude correction coefficient is performed to obtain the amplitude and phase correction coefficients of all the branches.
  • the digital baseband signal needs to be time-delay corrected before the amplitude phase correction.
  • the key of the delay correction is to calculate the filter coefficients, and the calculation method of the filter coefficients includes the following steps:
  • Step 1 The neighboring branch pairs the samples of the digital baseband signal to determine the samples for the delay correction calculation.
  • the sample points generally used are before the extraction, that is, the sample interval is r s .
  • the present invention sets a delay correction window for each pair of adjacent branch pairs, and stipulates that only the signal samples falling in the delay correction window are selected for relative delay correction of the adjacent branch pairs. Calculation. Each adjacent branch pair needs to discriminate the input signal samples, and only the signal samples satisfying the discriminating conditions can be used for the delay correction calculation. This discrimination condition can be expressed by the following formula: -BCE k -W T>k ⁇ P k ⁇ n) ⁇ -BCE k
  • ff ⁇ represents the k-pair adjacent branch pair delay correction window width
  • the minimum can be close to 0, and the maximum can be taken as infinity.
  • ⁇ Indicates the power level of the nth sample of the kth branch, ⁇ ⁇ . ( «-1) indicates the power level of the n-1th sample of the kth branch, and so on;
  • the power level of the nth sample of k+1 branches, ⁇ (“-1" indicates the power level of the n-1th sample of the k+1th branch, and so on.
  • the delay correction window can also be set by other methods, as long as it can filter the samples suitable for the delay correction calculation.
  • the delay correction window can also be set to: -BCE k -W 7 , k ⁇ P k (n) ⁇ -BCE k
  • Step 2 Calculate the iterative sum of the adjacent branches to the current delay cross-correlation value according to the iteration of the last delay cross-correlation value of the adjacent branch pair and the current cross-correlation value.
  • the kth branch Since there are 2L + 2 samples in step 1, the kth branch has L+1 samples, and the k+1 branch also has corresponding L+1 samples. Therefore, if the L+1 samples described on the kth branch are cross-correlated with the L+1 samples described on the k+1 branch, 2L+1 different cross correlations can be obtained. Value iterations and .
  • the initial value of the accumulated value of 2L+1 cross-correlation between the pair of adjacent branches, ie, the value after power-on or reset, is set to 0, namely:
  • T the delay correction
  • d the delay difference
  • R T , k (! T , k , d) represents the kth pair of adjacent branches
  • the correlation value, p T , k ⁇ l TJc , d) represents the current cross-correlation value of the adjacent branch pair, indicating that the k-th pair of branches is ⁇ -filtered last value weight, referred to as coefficient.
  • the meaning of the coefficient is similar to the meaning of the coefficient in the calculation of the amplitude and phase correction coefficient.
  • a similar processing method can also be adopted, which will not be described here. It can be known from the above formula that the last cross-correlation value iteration of the adjacent branch pair and the weighted average of the current cross-correlation values are the iterative sums of the cross-correlation values of the adjacent branch pairs.
  • the current cross-correlation value of the adjacent branch pair can be expressed as:
  • the current cross-correlation value of adjacent branch pairs can also be expressed as:
  • the former method is to take a sample on the kth branch with the k+1 Cross-correlation calculation is performed on a sample on the branch road
  • Step 3 Iterate the current delay cross-correlation value according to the adjacent branch and obtain the current delay residual between the adjacent branch pairs.
  • the delay residual between the kth pair of adjacent branch pairs refers to the time when the signal on the kth branch lags behind the signal on the k+1th branch.
  • the delay between the kth pair of adjacent branch pairs can be calculated by:
  • the cross-correlation value indicating the kth pair of adjacent branch pairs that is, the current delay is d
  • Re ⁇ ⁇ indicates the real part operation.
  • the high-gain branch and the low-gain branch of an adjacent branch pair each select 4 samples, corresponding to 4 moments, and the same sample of the high 4 ⁇ gain branch corresponds to the same moment. If only the calculated value of the correlation function with a delay value of 2 between adjacent branch pairs exists, the remaining values calculated by the correlation function are all 0, then That is, the third sample and the low gain branch of the high gain branch
  • the first sample of the road is most relevant, and it can be considered that the third sample of the high gain branch and the first sample of the low gain branch are actually the same sample before being divided into multiple branches.
  • the maximum is only because of the delay difference between the adjacent branch pairs, so that the signal of the high gain branch lags behind the signal of the low gain branch with a delay time of 2.
  • r fc can be an integer, but in most cases it is not an integer and can be positive, negative or zero.
  • Step 4 Determine the current relative delay correction coefficient between adjacent branches according to the current delay residual and the previous relative delay correction coefficient between adjacent branch pairs.
  • the delay residual r 4 is actually the relative delay correction coefficient between adjacent branch pairs, but after multiple delay correction calculations, there is the first TJc - 1 or the last relative between adjacent branch pairs. Delay correction factor. If the current relative delay residual between adjacent branch pairs is superimposed on the last relative delay correction coefficient between adjacent branch pairs, the relative delay of the adjacent branch can be easily obtained. Correction coefficient.
  • the k-pair adjacent branch pair last time relative delay correction coefficient
  • ( ) indicates the k-th pair adjacent branch pair current relative delay correction coefficient.
  • the above equation says that if the output signal is behind the k+1th branch when the kth branch is delayed (-1), the delay should be adjusted to (-1). ) - ⁇ Samples are aligned with the k+1 tributary signal in time. It should be noted that ⁇ ⁇ (1 ⁇ ) has different meanings from other formulas in the present invention, n T represents the number of updates of the relative delay correction coefficient, and n TT l ) represents the corresponding sample number.
  • the kth branch signal is delayed by a sample point and the k+1th branch signal is delayed. If you don't move, you can align with the k+1 tributary signal. In practice, it can be an integer, but in most cases it is not an integer, and it can be positive, negative, or zero.
  • Step 5 Obtain the overall delay correction coefficient based on the current relative delay correction coefficient between adjacent branch pairs.
  • the delay target value refers to the group delay requirement of the low pass filter used for delay correction.
  • the M-channel delay correction factor can be expressed as:
  • k does not mean the kth pair of adjacent branch pairs, but the kth branch.
  • the delay correction coefficient of the kth branch is the sum of the relative correction coefficients from the adjacent branch pair where the branch is located to the adjacent branch where the reference branch is located.
  • the receiver has a total of 5 branches, the 3rd branch is the reference branch, the 1st and 2nd branches are the first pair of adjacent branch pairs, and so on.
  • the delay correction coefficient may not be calculated. Even if the delay correction factor needs to be calculated, although the signals of the adjacent branch pairs are not completely aligned in time, as long as the system performance is not affected, the delay correction coefficients can be calculated periodically or irregularly, without frequent Delay correction.
  • the M-channel selection control module selects a method for outputting a digital baseband signal branch according to a switching strategy, for example, the following method can be implemented:
  • Step XI M-channel selection
  • the 1-way control module determines the branch with the largest gain but not saturation according to the digital baseband signal before correction, and selects the branch as the candidate.
  • the condition that the M-channel selection 1 control module determines whether the branch is saturated is not to judge whether the complex envelope power reaches 0dBFS, but to determine whether it reaches -5CE, dBFS, and if it is reached, it is judged as already Saturated, otherwise, it is judged to be unsaturated.
  • Step X2 The M-channel selection 1-way control module determines whether the previous sample is output by the adjacent low-gain branch of the candidate-selected branch, and the power of the sample in the candidate-selected branch is not lower than the hysteresis. Threshold, if yes, the adjacent low-gain branch of the candidate selected branch is used as the selected branch to output the current sample; otherwise, the candidate selected branch is used as the selected branch to output the current sample .
  • the candidate selected branch is used as the selected branch to output the current sample.
  • the high and low double thresholds that is, the switching hysteresis can be set. That is, set -BCE k dBFS to the hysteresis high threshold and set - (SC3 ⁇ 4 + H ⁇ 3 ⁇ 4 ⁇ ) dBFS to the hysteresis low threshold.
  • the kth branch is the unsaturated maximum output branch
  • the k+1th branch is the branch that outputs the last sample, then the power of the kth branch is not low.
  • the k +1th branch should continue to be the output branch of this sample, otherwise it will switch from the k + 1 branch to the kth branch.
  • Fig. 11 is a view showing the basic structure of the receiver in this embodiment.
  • this embodiment adopts a method for configuring the amplitude and phase correction coefficients offline, that is, before the receiver starts working, the initial values of the amplitude and phase correction coefficients of the M branches are calculated, and then configured to the amplitude and phase correction module 1104. , and no longer changes during receiver operation.
  • This includes two cases. One is to configure the correction factor in the receiver before powering up the receiver. In this case, the configured coefficient is power-down or reset and does not lose information. The other is at the receiver. Write once to the receiver after each reset, without losing power or resetting, the information will not be lost, but the information will be lost after power-off or reset, all write-once after each power-on or reset operating.
  • Fig. 18 is a flow chart showing the method of calculating the amplitude phase correction initial value in the present embodiment. As shown in FIG. 18, the method for calculating the amplitude phase correction initial value includes the following steps:
  • Step 1801 Set the last power value iteration of the adjacent high-gain branch of each adjacent branch, the last power value iteration of the low-gain branch, and the last cross-correlation value iteration to 0.
  • the initial value is calculated according to the initial value of the relative amplitude correction coefficient, and is configured to the amplitude and phase correction module. Then, based on this, the initialization process of the amplitude and phase correction coefficients is started, that is, the initial value of the true amplitude correction coefficient is calculated.
  • Step 1802 Each adjacent branch pair screens the sample points obtained by the multi-branch correction pre-processing module according to the respective amplitude and phase correction windows, and determines the sample points used for the current relative amplitude correction calculation.
  • Step 1803 Each adjacent branch calculates the current power value iteration of the own high-gain branch by iterating from the last power value of the high-gain branch and the current sample power value falling into the amplitude and phase correction window of the self-gain. According to the iterative sum of the last power value of the low-gain branch and the current power value of the current sample, the current power value iteration of the low-gain branch is iterated according to the last cross-correlation value of the adjacent branch pair. And the current sample cross-correlation value to calculate the iterative sum of the current cross-correlation values of the adjacent branch pairs.
  • the steps 1802 and 1803 are similar to the steps 1 and 2 in the method for calculating the amplitude and phase correction coefficients described in the present invention, and are not described herein again.
  • Step 1804 The number of times each adjacent branch pair determines whether the sample falls into the amplitude correction window of the user reaches a preset value. If yes, step 1805 is performed; otherwise, the process returns to step 1802.
  • the number of times that the kth pair of adjacent branch pairs fall into the sample point is recorded. If you want to get the ideal overall amplitude correction coefficient, you need a considerable number of samples for each pair of adjacent branch pairs to fall into the amplitude correction window. As for how many times each pair of adjacent branch pairs falls into the amplitude and phase correction window, it needs to be preset according to the actual situation, that is, the preset value of the number of times a sample falls into the amplitude and phase correction window needs to be determined. When the number of samples of all adjacent branch pairs falls within the amplitude correction window reaches the preset value, step 1805 is continued; otherwise, each adjacent branch pair continues to wait for the appropriate sample.
  • ⁇ , ⁇ , ⁇ ) ⁇ of each adjacent branch pair and ⁇ (Zw) The initial value after power-on or reset is 0, but each time a certain sample falls into the amplitude and phase correction window of an adjacent branch pair, ⁇ increases by 1, correspondingly ⁇ w ( ⁇ ), ⁇ and AP,,, ) will be updated, and as the last power value iteration and calculate the new / ⁇ (/ ⁇ ), ⁇ (/_ ⁇ ) when the next time the sample falls. And value. That is to say, in the process of the initial value of the amplitude correction coefficient, the values of P k , H ( k P (/ ⁇ ) and , will not be clear.
  • Step 1805 Each adjacent branch pair is calculated according to the current power value iteration of the high gain branch, the current power value iteration of the low gain branch, and the current correlation value of the adjacent branch pairs. The relative amplitude and phase correction factor of its own adjacent branch pair.
  • each adjacent branch pair can calculate the relative amplitude and phase correction coefficients according to the signal samples at the same time, that is, the input signal is not for one adjacent branch pair, but varies between the dynamic ranges of the respective branches. And each adjacent branch pair performs step 1802 to step 1805 at the same time until the calculation of the relative amplitude and phase correction coefficients of all adjacent branch pairs is completed; each adjacent branch pair can also calculate the relative amplitude and phase correction coefficient in time division.
  • the power of the input signal is controlled to fall into the amplitude and phase correction window of an adjacent branch pair, and after the calculation of the relative amplitude and phase correction coefficients of the adjacent branch pair is completed, the input signal is The power is controlled to fall into the amplitude and phase correction window of another adjacent branch pair, calculate the relative amplitude and phase correction coefficients of the other adjacent branch pair, and repeat the process until all adjacent branch pairs are completed. Relative amplitude phase correction factor calculation.
  • Step 1806 Obtain M amplitude and phase correction coefficients according to relative amplitude and phase correction coefficients between all adjacent branch pairs.
  • step 1805 and step 1806 are the same as step 3 and step bare 4 in the amplitude phase correction coefficient calculation method, and details are not described herein again.
  • Step 1807 Configure M amplitude and phase correction coefficients to the amplitude and phase correction module.
  • the receiver can receive the wireless signal from the antenna and does not change it afterwards.
  • the allocating the overall amplitude correction coefficient to the amplitude and phase correction module actually writes the entire amplitude and phase correction coefficient into the register corresponding to the M amplitude and phase correction coefficients in the amplitude correction module.
  • the input signal for offline configuration of the initial value of the amplitude correction coefficient may be a correction signal, or may be directly injected from the antenna input to be suitable for use.
  • the input signal may be a receiver input signal or a correction signal.
  • the wireless signal can be started to be received and processed as a bit stream output.
  • Fig. 19 is a flow chart showing the method of realizing reception of a wireless signal in this embodiment. As shown in FIG. 19, the method for receiving a wireless signal in this embodiment includes the following steps:
  • Step 1901 The upstream analog receiving channel module including the analog I&Q demodulation function amplifies the receiver input signal and performs analog I&Q demodulation to obtain an analog baseband signal, and outputs it to the M dual-channel fixed gain branch modules.
  • the upstream analog receive channel module with analog I&Q demodulation function can also perform mixing and filtering on the receiver input signal.
  • Step 1902 M dual-channel fixed gain tributary modules perform step gain processing on the input analog baseband signals and output them to M dual-channel analog-to-digital converters.
  • Step 1903 M dual-channel analog-to-digital converters process the M-channel analog baseband signals to obtain M-channel digital baseband signals and output them to M amplitude-phase correction multipliers and M-channel-selective 1-channel control modules.
  • Step 1904 M amplitude and phase correction multipliers perform amplitude phase correction processing on the input M digital baseband signal according to the amplitude and phase correction coefficient saved in advance, and output to the M channel selection 1 channel module; M channel selection 1 channel control module The branch of the current sample is selected according to the switching strategy, and the branch number is notified to the M-channel 1 module by switching the control signal.
  • the M amplitude and phase correction coefficients input to the M amplitude and phase correction multipliers are the initial values of the M amplitude and phase correction coefficients that are configured to the amplitude and phase correction module 1104 in advance in the present embodiment.
  • Step 1905 The M-channel selection 1-channel module selects one of the M-channel digital baseband signals after the amplitude-phase correction according to the switching control signal to output to the rear of the digital receiving channel.
  • Step 1906 The digital baseband signal is further digitally processed in the latter stage of the digital receiving channel, and the bit stream is output.
  • Method embodiment two The digital baseband signal is further digitally processed in the latter stage of the digital receiving channel, and the bit stream is output.
  • Fig. 12 is a view showing the basic structure of the receiver in this embodiment.
  • this embodiment adopts a method for configuring the amplitude and phase correction coefficients on the line, that is, when the receiver is powered on, the amplitude and phase correction coefficient calculation module calculates the initial values of the amplitude and phase correction coefficients of the M branches, and configures them to the amplitude and phase. Correction module 1205. Thereafter, the amplitude and phase correction coefficient calculation module continues to calculate the new amplitude and phase correction coefficients of the M branch and reconfigures the new amplitude and phase correction coefficients to the amplitude and phase correction module 1205.
  • FIG. 20 shows a flow chart of a method for implementing receiving a wireless signal in the embodiment.
  • the method for implementing the wireless signal in this embodiment includes the following steps:
  • Step 2001 A fixed gain tributary module including an analog I&Q demodulation function performs step gain processing and analog I&Q demodulation processing on the receiver input signal to obtain an M-channel analog baseband signal and outputs it to M dual-channel analog-to-digital converters. .
  • Step 2002 M dual-channel analog-to-digital converters sample and process the analog baseband signal to obtain and output a digital baseband signal to the M decimation filter modules.
  • Step dong 2003 M decimation filter modules perform low-pass filtering and decimation processing on the input digital baseband signal, and output to the amplitude-phase-corrected feedforward loop delay compensation module, amplitude-phase correction coefficient calculation module and M-channel selection 1 Control module.
  • Step 2004 The M-channel selection 1-channel control module determines the branch number of the current sample according to the switching policy, generates a switching control signal carrying the branch number information, and a switching flag signal indicating whether switching occurs, and performs switching control.
  • the signal is output to the switching feedforward loop delay compensation module, and the switching flag signal is output to the amplitude phase correction coefficient calculation module.
  • the M-channel selection control module can know whether the output of the current sample branch number and the output of the last sample branch number are the same according to the switching strategy, and thereby generate the switching control signal and the switching flag signal. If the M-channel selection 1 control module finds that the branch that should output the n-th sample is the same as the branch that outputs the n-1 sample, the branch number in the switching control signal is still the same as the output n-1 sample. The branch number is the same, the switching flag signal indicates that the current sample does not need to be switched; otherwise, the branch number in the switching control signal will be the new branch number, and the switching flag signal indicates that the current sample needs to be switched.
  • the switching flag signal can be designed as a lbit signal. If the current sample needs to be switched, the switching flag signal is 1; otherwise, the switching flag signal is 0.
  • Step 2005 The amplitude and phase correction coefficient calculation module performs screening and calculation of the correction signal, and determines whether the calculated amplitude phase is to be calculated according to the latest value of the switching flag signal and the amplitude phase correction coefficient.
  • the latest value of the correction coefficient is assigned to the amplitude and phase correction module. If yes, the latest value of the amplitude correction coefficient is configured to the amplitude and phase correction module; otherwise, no configuration is made.
  • the method of calculating the new amplitude and phase correction coefficient by the amplitude and phase correction coefficient calculation module is basically similar to the method of calculating the initial value of the amplitude and phase correction coefficient, except that each time a suitable sample falls into the correction window, it is directly based on the last power that already exists.
  • the value iteration sum and the current sample power value calculate a new amplitude and phase correction factor.
  • the steps to calculate the latest value of the amplitude correction coefficient are:
  • the amplitude and phase correction coefficient calculation module screens the input samples through the amplitude and phase correction window of each adjacent branch pair, and determines the sample points used for the current amplitude and phase correction calculation;
  • each adjacent branch is iteratively summed according to the last power value iteration of its own high gain branch and the current sample power of the own high gain branch which falls into the amplitude and phase correction window of its own, according to Iterative sum of the last power value of the low-gain branch of the own and the current power value of the current low-gain branch of the current sample, and the iteration of the last cross-correlation value of the adjacent branch pair and this time
  • the sample cross-correlation value calculates the iterative sum of the cross-correlation values of the adjacent branch pairs;
  • Each adjacent branch calculates itself according to the current power value iteration of its own high gain branch, the current power value iteration of the low gain branch, and the current correlation value of the adjacent branch pairs. Relative amplitude and phase correction coefficients of adjacent branch pairs;
  • the amplitude and phase correction coefficient calculation module obtains the latest value of the overall amplitude and phase iE coefficient according to the relative amplitude and phase correction coefficients of all adjacent branch pairs. ⁇ _ .
  • the signal input to the amplitude and phase correction coefficient calculation module may be an M-channel digital baseband signal that has not undergone amplitude and phase correction, or an M-channel digital baseband signal that has undergone amplitude and phase correction.
  • the method of calculating the amplitude and phase correction coefficients is basically similar whether it is the signal before the amplitude phase correction or the amplitude phase corrected signal. The difference is: If it is the sample of the amplitude phase corrected signal, it needs to be removed before the calculation.
  • the influence of the original amplitude correction coefficient that is, the M-channel digital baseband signal that has undergone the amplitude-phase correction is first divided by the original amplitude-phase correction coefficient, and is restored to The M-channel digital baseband signal before the amplitude and phase correction, and then the amplitude-phase correction coefficient calculation; or directly calculate the sample of the M-channel digital baseband signal that has undergone the amplitude-phase correction, and finally multiply the calculated amplitude-phase correction coefficient
  • the latest value of the true amplitude and phase correction factor is obtained with the original amplitude and phase correction factor.
  • the method for determining whether the amplitude phase correction coefficient latest value needs to be configured to the amplitude phase correction module is: when the amplitude phase correction coefficient calculation module receives the input of the M channel selection 1 channel control module When the current sample is switched, the amplitude and phase correction coefficient calculation module determines whether the current sample has a switch according to the switching flag signal. If there is a switch, the amplitude and phase correction coefficient calculation module determines that the previous phase amplitude correction module has been configured. Whether a new amplitude and phase correction coefficient has been calculated after the amplitude and phase correction coefficient, and if so, the latest value of the amplitude and phase correction coefficient is assigned to the amplitude and phase correction module.
  • the switching flag signal indicates that the current sample does not need to be switched, or the amplitude and phase correction coefficient calculation module has not calculated the new amplitude and phase correction coefficient after the amplitude phase correction coefficient was last configured for the amplitude and phase correction module, The phase correction factor does not need to be updated.
  • the amplitude-phase correction coefficient is calculated regardless of whether a new amplitude-phase correction coefficient is calculated.
  • the module can also configure the amplitude correction factor to the amplitude correction module.
  • the amplitude correction coefficient may be the latest value of the newly calculated amplitude and phase coefficient after the last configuration to the amplitude and phase correction module, or may be the last amplitude and phase correction coefficient, ie, the original coefficient value is only reconfigured. Once, it does not change the value of the amplitude and phase correction factor of the amplitude correction module.
  • the M-channel selection control module can also periodically configure the new amplitude-correction coefficient to M amplitude-correction multipliers, regardless of whether it needs to switch from one branch to another.
  • Step 2006 The amplitude and phase correction feedforward loop delay compensation module will process the delay compensation
  • the digital baseband signal is output to the amplitude phase correction multiplier.
  • the amplitude and phase correction feedforward loop delay compensation module, the amplitude and phase correction coefficient calculation module, and the M-channel selection and control module actually process the input digital baseband signal at the same time.
  • the current processed sample is the n-th sample
  • the amplitude-phase correction coefficient calculation module calculates the amplitude-correction coefficient according to the n-th sample
  • the M-channel-selective control module determines the branch of the current sample according to the switching strategy, and A switching control signal and a switching flag signal are generated.
  • the M-channel selection 1 control module sends a switching flag signal to the amplitude-correction coefficient calculation module to indicate that the current sample needs to be switched, and the amplitude-phase correction coefficient is calculated.
  • the amplitude correction coefficient calculation module immediately configures the calculated new amplitude and phase correction coefficient to the amplitude and phase correction module.
  • the n-th sample is output to the M amplitude-phase correction multipliers while the amplitude-phase correction coefficient is configured, and the M amplitude-phase correction multipliers are based on the new
  • the amplitude and phase correction coefficients are configured to perform amplitude and phase correction on the n-sample, and then output to the M-channel selection 1 module.
  • Step 2007 M amplitude and phase correction multipliers perform amplitude and phase correction on the input M digital baseband signal according to the latest value of the amplitude and phase correction coefficient, and then output to the M channel selection 1 channel module.
  • the M amplitude and phase correction multipliers will correct the M digital baseband signal according to the latest configuration of the amplitude and phase correction coefficients in the amplitude and phase correction module, that is, calculate the amplitude on the first online.
  • the M amplitude and phase correction multipliers are corrected based on the amplitude phase correction initial value. After that, it is corrected according to the latest value of the amplitude and phase correction coefficient configured in step 2005 for the amplitude and phase correction module.
  • Step 2008 The M-channel selection 1-channel module selects one channel from the input corrected digital M-band signal to the rear of the digital receiving channel according to the switching control signal for delay compensation by switching the feedforward loop delay compensation module. .
  • Step 2009 The digital baseband signal is further received by the digital receiving channel in the latter stage Digital processing, output bit stream.
  • Fig. 13 is a view showing the basic structure of the receiver in this embodiment.
  • the receiver in this embodiment is basically similar to the receiver used in the second embodiment of the method, and the difference is that: each branch of the embodiment has a delay error, and the time delay correction module is required to perform signal processing. Delay correction.
  • the analog I&Q demodulation function is not included in the processing of the analog signal, but the I&Q demodulation processing is performed by the digital I&Q demodulation section.
  • the delay correction in this embodiment is implemented by using M low-pass filter modules in the digital I&Q demodulation section, that is, the digital I&Q demodulation 'part, delay correction coefficient calculation module and filter coefficient calculation module are configured.
  • the delay correction module is implemented without using the M low-pass filter modes in the digital I&Q demodulation section, but the M low-pass filter modes are additionally added to implement the delay correction.
  • the calibration signal is injected into the module to switch to the contact 2
  • the correction signal generated by the correction signal injection module is used to perform amplitude phase correction coefficient calculation and filter coefficient calculation
  • the calculated initial values of the amplitude and phase correction coefficients and the initial values of the filter coefficients are respectively assigned to the amplitude and phase correction module and the M low-pass filters, and then the correction signal is injected into the module and the switch is switched to the contact 1 to be received from the antenna. input signal.
  • the calculation method of the initial value of the amplitude correction coefficient in the embodiment is the same as the calculation method of the initial value of the amplitude correction coefficient in the first embodiment of the method, and details are not described herein again.
  • Fig. 21 is a flow chart showing the method of calculating the initial value of the filter coefficient in the present embodiment.
  • the method for calculating the initial value of the filter coefficient in this embodiment includes the following steps: Step 2101: Obtain the overall delay correction coefficient according to the initial value of the relative delay correction coefficient set in advance for each adjacent branch, and then obtain the overall delay correction coefficient. The overall filter coefficients are obtained from the overall delay correction coefficients and are respectively assigned to M low pass filters.
  • Step 2102 Set the iteration and the last relative delay correction coefficient of all previous cross-correlation values of each adjacent branch pair to zero.
  • Step 2103 Each adjacent branch pair screens the sample points processed by the input signal through the excessive branch correction pre-processing module through respective delay correction windows, and determines the sample points used for the current delay correction calculation.
  • Step 2104 Each adjacent branch pair calculates an iterative sum of the current delay cross-correlation values according to the respective last delay cross-correlation bit iteration and the current delay cross-correlation value.
  • Step 2105 Each adjacent branch pair iterates and obtains the current delay residual of each adjacent branch pair according to the respective current delay cross-correlation values, and according to its own delay residual and the last relative The delay correction coefficient determines the current relative delay correction coefficient of each adjacent branch pair.
  • Step 2106 Each adjacent branch pair determines whether the number of times the sample falls into the delay correction window reaches a preset value. If yes, step 2107 is performed; otherwise, returns to step 2103.
  • the delay correction coefficient calculated after a large number of samples fall into the delay correction window is more reliable. Therefore, the number of times that it falls into the correction window is set in advance, and the size of the preset value is determined according to the actual situation.
  • all adjacent branch pairs can simultaneously calculate the relative delay correction coefficient according to the input signal, that is, steps 2102 to 2106 are simultaneously performed, and only all adjacent branch pairs have sufficient samples.
  • the relative delay correction coefficients of all adjacent branch pairs are calculated, and then step 2107 is started.
  • the power of the correction signal may be first controlled in a delay correction window of an adjacent branch pair, and the relative delay correction coefficients of the adjacent branch pairs are collectively calculated, and then other calculations are sequentially performed.
  • the adjacent branch pairs are then only executed in step 2107.
  • Step 2107 Each adjacent branch obtains a total delay correction coefficient according to the current relative delay correction coefficient, and obtains an initial value of the filter coefficient according to the overall delay correction coefficient and the previously set delay target value, and respectively allocates to the M A low pass filter.
  • the input signal for calculating the initial value of the filter coefficient may be an input signal for setting the initial value of the filter coefficient offline, or may be a receiver input signal, and its application environment and method The initial values of the calculated amplitude and phase correction coefficients described in Embodiment 1 are the same, and are not described herein again.
  • the receiver can start to work, receive the wireless signal, and output the bit stream.
  • Fig. 22 is a flow chart showing the method of realizing reception of a wireless signal in this embodiment. As shown in FIG. 22, the method for receiving a wireless signal in this embodiment includes the following steps:
  • Step 2201 The correction signal injection module transmits the receiver input signal to the M single-channel fixed gain tributary modules, and the M single-channel fixed gain tributary modules perform the step gain processing on the receiver input signal, and output to the M single channels. Analog to digital converter.
  • Step 2202 M single-channel analog-to-digital converters and digital down-conversion parts respectively perform signal processing and down-conversion processing to obtain digital I&Q signals, and output them to M low-pass filter modules.
  • Step 2203 M low-pass filter modules perform low-pass filtering on the digital I&Q signal, and perform delay correction according to the filter coefficients to obtain a digital baseband signal, and then output to the M extraction module and the delay correction coefficient calculation module;
  • the delay correction coefficient calculation module calculates a delay correction coefficient according to the input digital baseband signal, and sends a new delay correction coefficient to the filter coefficient calculation module to calculate a new value of the filter coefficient, and allocates to the M low pass filter modules.
  • the purpose of this step 2203 is to calculate a new filter coefficient, the method of which is similar to the method of calculating the initial value of the filter coefficient, the difference is that when calculating the new value of the filter coefficient, it will start directly on the basis of the initial value of the filter coefficient. It is also performed, and it is not necessary to judge whether the number of times the sample falls into the delay correction window reaches a preset value.
  • the method of calculating the new value of the filter coefficient includes the following steps:
  • the delay correction coefficient calculation module passes the delay correction window of each adjacent branch pair, The input samples are screened to determine the current sample used for the calculation of the delay correction;
  • the delay correction coefficient calculation module calculates the current delay cross-correlation value iteration of each adjacent branch pair according to the last delay cross-correlation value iteration of each adjacent branch pair and the current delay cross-correlation value ;
  • the delay correction coefficient calculation module iterates and obtains the current delay residual of each adjacent branch pair according to the cross-correlation value of each adjacent branch pair, and according to the current delay residual and the last relative time
  • the delay correction coefficient determines the current relative delay correction coefficient of each adjacent branch pair
  • the delay correction coefficient calculation module obtains the overall delay correction coefficient according to each adjacent branch to the current relative delay correction coefficient, and sends the entire delay correction coefficient to the filter coefficient calculation module;
  • the H5, filter coefficient calculation module obtains the latest value of the filter coefficient based on the overall delay correction coefficient and the previously set delay target value.
  • Steps 2204 to 2211 are similar to steps 2003 to 2009 in the second embodiment of the method, except that the filtering process is not performed in step 2205, and only the extraction process is performed, and details are not described herein again.
  • the method of receiving the wireless signal is similar to that of the present embodiment, except that the receiver input signal is first I&Q demodulated in the analog signal processing stage, and then Digital sampling is performed to obtain a digital baseband signal, and then a delay correction is performed using a dedicated delay correction module. Since the method is similar to this embodiment, it will not be described here.
  • the receiver includes a DC and I&Q balance correction module
  • DC and I&Q balance correction processing on the digital baseband signal output from the multi-branch correction pre-processing module to remove the error introduced by the circuit, that is, The DC error in the I and Q signals introduced by the circuit, and the amplitude and phase errors between the I and Q paths are removed. Then, processing such as delay correction and amplitude and phase correction is performed.
  • the receiver input signals of the analog bandpass signals can be converted into digital baseband signals first on each branch, and then the amplitude and phase correction are performed, and the digital baseband signals between the branches are in amplitude. Align with the phase.
  • the digital baseband signal is first subjected to delay correction before the amplitude and phase correction, so that the signal samples of each branch are time aligned. After that, the amplitude and phase correction is performed to align the digital baseband signals in amplitude and phase.
  • the present invention can realize point-by-point handover, and achieve the purpose of improving demodulation performance and increasing non-simultaneous dynamic range.

Description

一种接收机及接收无线信号的方法
技术领域
本发明涉及无线接收技术， 特别是涉及一种接收机及接收无线信号 的方法。 发明背景
在无线通信系统或雷达系统中，需要通过某种装置来接收无线信号， 该装置通常称为无线接收机或接收机。 接收机的种类有很多， 动态范围 是衡量接收机优劣的一个重要的指标。
接收机的动态范围一般分为同时动态范围和非同时动态范围。其中， 同时动态范围为大信号和小信号同时存在的情况下， 接收机能够同时正 确解调大信号和小信号的能力 , 其值一般为大信号和小信号功率比值的 最大值。 而非同时动态范围为接收机能够正确解调随时间起伏变化的信 号的能力， 其值一般为起伏变化的最大信号功率和最小信号功率的比 值。 接收机的非同时动态范围一般比其同时动态范围大， 这是因为如果 当大信号和小信号同时输入， 接收机能够正确解调， 那么当大信号和小 信号非同时输入， 由于没有相互干扰的问题，接收机就更能够正确解调。 实际上， 接收机可以利用模拟自动增益控制 （AAGC )技术来达到扩展 非同时动态范围的目的。
目前， AAGC技术一般可以分为两类： 一类为单变增益支路， 另一 类为多固定增益支路。 其中， 单变增益支路的思想是采用一条支路来传 输或处理所接收到的信号， 但该条支路的增益是可变的； 而多固定增益 支路的思想是采用多条支路同时传输或处理所接收到的信号， 但每一条 支路的增益是固定的， 而且不同支路的增益是不同的。 图 1显示了由单变增益支路技术来接收无线信号的接收机的基本结 构图。 如图 1所示， 单变增益支路的接收机一般包括： 上游模拟接收通 道模块、 变增益模拟接收通道、 模拟到数字转换器、 功率检测与 AAGC 控制模块、 数字接收通道模块。
其中， 上游模拟接收通道模块一般包括低噪声放大器， 还可能包括 混频器和滤波器等， 主要用于对接收到的输入信号进行预处理。 上游模 拟接收通道模块的输入信号， 即接收机输入信号为模拟带通信号。 如果 上游模拟接收通道模块中不包含模拟 I&Q解调部分，则通过上游模拟接 收通道模块以后输出一般仍然为模拟带通信号； 而如果上游模拟接收通 道模块中包含模拟 I&Q解调部分， 则输出为模拟 I&Q信号。
变增益模拟接收通道模块一般包括多级的混频、 滤波模块和放大模 块等， 并且可以在功率检测与 AAGC控制模块的控制下改变其增益。
模拟到数字转换器用于将模拟信号转换为数字信号。 当输入为一路 模拟带通信号时，模拟到数字转操器包含一路 ADC, 即单通道模拟到数 字转换器； 而当输入为模拟 I&Q信号时，模拟到数字转换器则包含 I&Q 两路 ADC, 即双通道模拟到数字转换器。
功率检测与 AAGC控制模块是将模拟到数字转换器模块输出的信 号进行处理， 获得信号功率值， 再 4艮据信号功率值确定增益配置， 然后 在解调同步信号的控制下改变变增益模拟接收通道的增益太小。
数字接收通道模块用于将从模拟到数字转换器输入的信号进行滤 波、 抽取等处理， 获得基带信号， 然后将基带信号经过解调后获得 bit 流。 这里， 如果接收机为单载波接收机， 数字接收通道模块将输出一路 bit流； 如果是多载波接收机， 则输出多路 bit流。
从图 1中可以看到， 变增益模拟接收通道、 模拟到数字转换器、 功 率检测与 AAGC控制构成一个反馈环路。当输入信号经过上游模拟接收 通道模块、 变增益模拟接收通道、 模拟到数字转换器之后， 功率检测与
AAGC控制模块检测到输入信号功率的大小， 并根据接收机自身的动态 范围和一定的 AAGC 算法来将变增益模拟接收通道设置为一个合适的 增益值。 '
单变增益支路技术的缺点在于： （1 ) 由于是利用反馈环路来控制输 入信号功率大小的， 在输入信号发生变化时需要一定的反应时间才能更 新接收机的增益大小， 控制速度受到反应时间的制约。 （2 )功率检测与 AAGC控制模块不能在任意时刻更新增益， 而是需要在同步解调信号的 控制下更新增益， 即在同步边界上才能更新增益大小， 否则会因为模拟 器件增益的改变和随之产生的相位的变化而影响解调性能。 这就要求接 收机的增益在信号的持续期内保持不变， 即需要进行同步 AAGC, 这不 但增加了电路的复杂性， 而且不能快速跟踪信道变化。 （3 )如果输入信 号在信号持续期内发生大的变化， 超过了单通道的非同时动态范围， 则 无论 AAGC如何控制 ,都不能避免经过变增益模拟接收通道模块以后信 号出现饱和或低于灵敏度的情况， 这将导致误码率的增加。
在现有技术中， 另外一类 AAGC技术为多固定增益支路技术， 其特 点为： 无需用反馈环路来控制增益大小， 而是采用多条固定的不同增益 大小的支路来放大输入信号， 然后选择一路合适的支路输出， 即在支路 间进行切换。 根据多固定增益支路技术构成的接收机一般又分为两种： 一种是在解调前切换的多固定增益支路接收机， 另一种是在解调后切换 的多固定增益支^ ^收机。
图 2显示了在解调前切换的多固定增益支路接收机的基本结构图。 如图 2所示， 该接收机一般包括： 上游模拟接收通道模块、 M个固定增 益支路模块、 M个模拟到数字转换器、 M个数字接收通道前段、 多支路 同步切换模块、 数字接收通道后段。 其中， 上游模拟接收通道模块与单变增益支路接收机相对应模块相 同， 此处不再赘述。
与单变增益支路接收机相比， 固定增益支路模块一般也包括多级混 频、 滤波和放大模块， 但其增益是固定的， 而且 M个固定增益支路模块 之间的增益依次形成一定的梯级分布， 称为梯级增益处理， 比如： 第一 条支路的增益为 80db,第二条增益支路为 60db,第三条增益支路为 40db, 此类推。 当然， 在实际应用中， 相邻两条支路也可以使用不等间隔的 增益差。
每一个模拟到数字转换器与单变增益支路接收机相对应模块相同， 此处不再赘述。
数字接收通道模块用于将由模拟到数字转换器输入的信号进行多次 滤波、 抽取等处理， 得到基带信号， 再将基带信号经过解调得到 bit流。 如图 2所示， 在解调前切换的多固定增益支路接收机中， 数字接收通道 模块被多支路同步切换模块分成两个部分：一部分为 M个数字接收通道 前段， 另外一部分为数字接收通道后段。 M个数字接收通道前段是对由 模拟到数字转换器输入的信号进行部分处理， 再由多支路同步切换模块 在解调同步信号的控制下进行同步切换， 选出一路信号大小合适的支路 的信号输出， 然后由数字接收通道后段进一步进行数字处理， 如解调等 处理， 最后输出 bit流。 这里， 需要说明的是： 多支路同步切换模块位 于数字接收通道模块中间的哪个位置并没有严格的规定， 与实际中接收 机的设计相关， 但只要位于解调处理前即可。
当解调前切换的多固定增益支路接收机接收到输入信号以后， 先由 上游模拟接收通道模块进行混频、 滤波和放大等处理之后， 再将信号经 过 M个固定增益支路分别改变信号功率大小， 然后将信号分别经过 M 个模拟到数字转换器进行滤波、 抽取等采样处理， 得到数字信号， 最后 再经过 M个数字接收通道前段，并由多支路同步切换模块选择一路适合 大小信号的支路后， 将信号由数字接收通道后段进行解调输出 bi1；流。
另外， 与单变增益支路接收机一样， 解调前切换的多固定增益支路 接收机的输入信号为模拟带通信号， 如果上游模拟接收通道模块和固定 增益支路模块包括模拟 I&Q解调部分，则固定增益支路模块输出为模拟 基带信号， 即 I路和 Q路两路模拟低通信号； 否则， 输出信号为模拟带 通信号。相应地，模拟到数字转换器也分别有包括一路 ADC和包含 I&Q 两路 ADC的情况。
最后， 如果解调前切换的多固定增益支路接收机是单载波接收机， 每一个数字接收通道输出一路 bit流； 如果是多载波接收机， 则输出多 路 bit流。
解调前切换的多固定增益支路技术的缺点在于： （1 ) 由于解调前进 行的切换必须是同步切换， 即在接收信号的同步边界上才能进行切换， 这不但增加了电路的复杂性， 而且不能使切换实时跟踪信道的变化。 ( 2 ) —方面， 输入信号虽然同时输入多个支路， 但由于多个支路的电 路特性不同， 导致在进行切换前各支路信号在同一时刻的相位、 幅度不 一致。 另一方面， 接收机一般将整个信号持续内的信号同时进行解调， 所以切换的时间粒度一般是大于信号持续期。 如果输入信号在持续期内 有较大的变化， 变化范围超过了单支路的非同时动态范围脉， 无论多支 路同步切换模块怎样切换， 都无法使输出的信号在整个信号持续期内正 常， 这将影响信号持续期内的解调性能。
图 3显示了解调后切换的多固定增益支路接收机的基本结构图。 如 图 3所示，这种接收机与解调前切换的多固定增益支路接收机基本一样， 所不同的是， 数字接收通道模块并没有被多支路切换模块分为两个部 分， 信号是在完全进行解调之后才由多支路切换模块来选择一路信号大 小合适的支路输出 "号。 由于可以直接从经过解调的信号中得到同步信 号， ^以解调后切换支路无需专门的解调同步信号来控制切换。
另外， 需要说明的是： 在实际应用中， 接收机中也可以不包含上游 模拟接收通道， 即接收机输入信号可以输入到固定增益支路模块中。 另 外，模拟 I&Q解调部分可以不包含于上游模拟接收通道模块中， 而是包 含于各个固定增益支路模块中， 或者上游模拟接收通道模块和各个固定 增益支路模块都不含模拟 I&Q解调部分，而由数字部分通过数字方法从 单路采样的数字带通信号中得到数字 I&Q信号。
解调后切换的多固定增益支路技术的缺点在于： （1 ) 由于需要先解 调后切换， 所以这种接收机需要 M个包括解调部分的数字接收通道模 块， 这造成了资源的浪费。 （2 )与解调前切换的多固定增益支路技术一 样， 解调后切换的多固定增益支路技术仍然无法解决在信号持续期内信 号发生较大变化的情况下， 解调性能降低的问题。
由此可见， 在现有技术中， 还没有一种无需专门的同步信号控制就 可以进行支路之间的切换， 而且可以快速跟踪信号变化， 保证在信号持 续期内输入信号突变时的解调性能的接收机以及接收无线信号的方法。 发明内容
本发明提供一种接收机和接收无线信号的的方法， 该接收机无需专 门的同步信号控制就可以进行支路之间的切换， 而且可以快速跟踪信号 变化， 保证在信号持续期内输入信号突变时的解调性能。
针对第一个发明目的， 本发明提出的技术方案为：
一种接收机，至少包括多支路校正前处理模块和数字接收通道后段， 该接收机进一步包括：
多支路校正与切换模块， 用于将由多支路校正前处理模块输入的 M 路数字基带信号进行幅度和相位校正， 并根据切换策略选择一路输出给 数字接收通道后段。
针对第二个发明目的， 本发明提出的技术方案为：
一种无线信号接收方法， 该方法包括以下步骤：
A、 将接收机的输入信号经过多支路校正前处理， 获得 M路未经过 幅相校正的数字基带信号；
B、 对未经过幅相校正的 M路数字基带信号进行幅度和相位校正， 再根据切换策略选择一路幅相校正后的数字基带信号；
C、 将所选择的数字基带信号进行进一步的数字处理， 获得比特流。 综上所述， 本发明提出的一种接收机和接收无线信号的方法具有以 下优点：
( 1 )由于本发明切换前的多路数字基带信号经过了校正，其幅度和 相位保持一致， 一方面可以在任意的时刻切换 , 或者说可以逐点切换而 无需同步信号的控制， 减少同步电路设计的复杂性。 另一方面， 如果输 入信号在信号持续期内发生突变， 也可以立刻切换， 达到快速跟踪信号 变化的目的。
( 2 )由于本发明切换前的多路数字基带信号经过了校正，可以在任 意的两条支路之间切换， 不影响切换输出信号的幅相连续性， 可以增加 非同时动态范围， 提高解调性能。—
( 3 )本发明中的切换位于解调之前， 所以在数字接收通道后段中 只需要一个解调器即可， 可以大大节约解调器资源。 附图简要说明
图 1是现有技术中单变增益支路技术的接收机的基本结构图； 图 2是现有技术中解调前切换的多固定增益支^ έ收机的基本结构 图；
图 3是现有技术中解调后切换的多固定增益支路接收机的基本结构 图；
图 4是本发明实施例的接收机基本结构图；
图 5是本发明实施例中多支路校正前处理模块的第一种内部结构示 意图；
图 6是本发明实施例中多支路校正前处理模块的第二种内部结构示 意图；
图 Ί是本发明实施例中多支路校正前处理模块的第三种内部结构示 意图；
图 8a是本发明实施例中数字下变频模块的第一种内部结构示意图； 图 8b是本发明实施例中数字下变频模块的第二种内部结构示意图； 图 9是本发明实施例中介梯式的固定增益模块内部结构示意图； 图 10是本发明实施例中多支路校正与切换模块内部结构示意图； 图 11是本发明装置实施例一的结构示意图；
图 12是本发明装置实施例二的结构示意图；
图 13是本发明装置实施例三的结构示意图；
图 14是本发明实施例中校正信号注入模块的第一种内部结构示意 图； _
图 15是本发明实施例中校正信号注入模块的第二种内部结构示意 图；
图 16是本发明装置实施例四的结构示意图；
图 17是本发明实施例实现接收无线信号方法的流程图；
图 18是本发明方法实施例一中实现计算幅相校正系数初始值方法 的流程图； 图 19是本发明方法实施例一的流程图；
图 20是本发明方法实施例二的流程图；
图 21 是本发明方法实施例三中实现计算滤波器系数初始值方法的 流程图；
图 22是本发明方法实施例三的流程图。 实施本发明的方式
下面结合附图及具体实施例对本发明详细说明。
本发明的基本思想是:在接收机中增加一个多支路校正与切换模块， 将由多支路校正前处理模块输入信号的幅度和相位进行校正， 并根据校 正前各支路信号的情况选择一条支路输出给数字接收通道进行进一步 的数字处理， 输出比特流。
图 4为本发明实施例的接收机基本结构图。 如图 4所示， 本发明实 施例的接收机至少包括：
多支路校正前处理模块 401、多支路校正与切换模块 402、数字接收 通道后段 403。
其中， 多支路校正前处理模块 401 , 用于将接收机输入信号经过 M 路梯级增益处理、获取数字基带处理之后，输出 M路数字基带信号给多 支路校正与切换模块 402。
这里所述的获取数字基带处理一般包括 I&Q解调、 采样等过程， 还 可能包括放大、 混频等处理。
多支路校正与切换模块 402, 用于将由多支路校正前处理模块 401 输入的 M路数字基带信号进行幅度和相位校正，并根据切换策略选择一 路信号输出给数字接收通道后段 403。
数字接收通道后段 403 , 用于将由多支路校正与切换模块 402输入 的一路数字基带信号进行进一步的数字处理，得到并输出比特流， 即 bit 流》
本发明实施例中， 接收机输入信号为模拟带通信号， 来自如接收机 天线等传感器， 可能含有某种带宽的单个载波， 也可能含有同带宽的多 个载波甚至不同带宽的多个载波。 接收机输入信号首先需要通过多支路 校正前处理模块 401处理为 M路数字基带信号。由于将接收机输入信号 处理为 M路数字基带信号的过程比较复杂， 为了叙述简单，本发明实施 例将接收机输入信号处理为 M路数字基带信号的部分统称为多支路校 正前处理模块 401。 组成多支路校正前处理模块 401的方式比较多， 但 按照数字基带获取方式的不同， 多支路校正前处理模块 401的组成情况 大致有如图 5、 图 6和图 7等几种情况。 数字基带获取指的是从模拟带 通信号中得到数字基带信号， 即数字 I&Q信号的过程。
如图 5所示， 多支路校正前处理模块 401可以包括： 含模拟 I&Q解 调功能的上游模拟接收通道模块 501、 M个双通道固定增益支路模块 502、 M个双通道模拟到数字转换器 503。
其中， 含模拟 I&Q解调功能的上游模拟接收通道模块 501 , 一般包 括低噪声放大器和模拟 I&Q解调部分， 也可能包括混频和滤波等部分， 主要用于将输入信号进行放大处理， 并将模拟带通信号解调为模拟基带 _信号， 再输出给 M个双通道固定增益支路模块 502。
M个双通道固定增益支路模块 502 包括双通道固定增益支路模块 502 # 1至双通道固定增益支路模块 502 # M，用于将由含模拟 I&Q解调 功能的上游模拟接收通道模块 501输入的模拟基带信号进行梯级增益处 理， 并将处理后的 M路模拟基带信号输出给 M个双通道模拟到数字转 换器 503。
M个双通道模拟到数字转换器 503 包括双通道模拟到数字转换器 503 # 1至双通道模拟到数字转换器 503 # M，用于将由 M个双通道固定 增益支路模块 503输入的模拟基带信号进行采样处理， 转换为数字基带 信号， 并输出给多支路校正与切换模块 402。
如图 6所示， 多支路校正前处理模块 401也可以包括 M个含模拟 I&Q解调功能的固定增益支路模块 601、 M个双通道模拟到数字转换器 602。
其中， M个含模拟 I&Q解调功能的固定增益支路模块 601包括：含 模拟 I&Q解调功能的固定增益支路模块 601 # 1至含模拟 I&Q解调功能 的固定增益支路模块 601 # M, 用于将接收机输入信号进行含模拟 I&Q 解调功能的梯级增益处理， 并将处理后的 M路模拟基带信号输出到 M 个双通道模拟到数字转换器 602。
M个双通道模拟到数字转换器 602 包括双通道模拟到数字转换器 602 # 1至双通道模拟到数字转换器 602 # M，用于将从 M个含模拟 I&Q 解调功能的固定增益支路模块 601输入的 M路模拟基带信号进行采样处 理， 转换为 M路数字基带信号， 并输出给多支路校正与切换模块 402。
当然，图 6中还可以进一步包括不含模拟 I&Q解调功能的上游模拟 接收通道模块，其连接关系和功能与图 5中的含模拟 I&Q解调功能的上 游模拟接收通道模块 501相似，只是不再包含模拟 I&Q解调后输出模拟 J&Q信号的功能,— 而是输出模拟带通信号。 —
如图 7所示， 多支路校正前处理模块还可以包括： M个单通道固定 增益支路模块 701、 M个单通道模拟到数字转换器 702、 数字 I&Q解调 部分 703。
其中， M个单通道固定增益支路模块 701、 M个单通道模拟到数字 转换器 702与图 6中对应模块的功能和连接关系类似， 只是处理的是模 拟带通信号而不是模拟 I&Q信号。 数字 I&Q解调部分 703 , 包括数字下变频模块 7031和 Μ个低通滤 波器模块 7032。其中，数字下变频模块 7031包括 DDC乘法器和数控振 荡器（ NCO ), 用于将从 Μ个单通道模拟到数字转换器 702输入的数字 带通信号的频谱搬移到 0频率的位置， 再输出给 Μ个低通滤波器模块 7032进行低通滤波处理， 得到 Μ路数字基带信号， 即为 Μ路数字复信 号， 表现为数字 I&Q信号。 这里， 搬移到 0频率位置的信号实际上分为 I路和 Q路两个并行的分支， 即 I路信号和 Q路信号， 然后分别输入低 通滤波器模块 7032进行低通滤波处理， 可以滤除数字镜像和其它干扰 信号， 得到 Μ路数字 I&Q信号。 因为数字 I&Q信号的模值直接反映了 接收机输入信号的包络形状， 所以也可以称为复包络。 图 7并没有将 I 路和 Q路信号分开描述， 即表示一路复信号。
另外，数字下变频模块 7031的内部结构可以为图 8a或者图 8b两种 形式。 如图 8a所示， 数字下变频模块 7031可以包括 M个 DDC乘法器 和一个 NCO, M个 DDC乘法器分别将从 M个单通道模拟到数字转换 器 702输入的 M路数字带通信号和共同的 NCO输入的数字本振信号作 相乘运算， 完成频语搬移， 并输出给 M个低通滤波器模块 7032。 如图 8b所示， 数字下变频模块 7031也可以包括 M个 DDC乘法器和 M个 NCO, 其作用与图 8a类似， 只是每一个 DDC都有一个单独的 NCO, 此处不再赘迷。 _
当然，图 7中还可以进一步包括不含模拟 I&Q解调功能的上游模拟 接收通道模块，其连接关系和功能与图 5中的含模拟 I&Q解调功能的上 游模拟接收通道模块 501相似，只是不再包含模拟 I&Q解调后输出模拟 I&Q信号的功能， 而是输出模拟带通信号。
总之， 接收机输入信号一般为模拟带通信号， 需要由多支路校正前 处理模块 401处理为数字基带信号。至于 I&Q解调是在模拟信号处理阶 段中进行， 还是在数字信号处理阶段中进行， 这与实际的接收机设计相 关， 此处不再——列举。
另外， 数字接收通道后段 403进行的数字处理是根据接收机输入信 号而不同的。 比如， 对于多载波的情况， 数字接收通道后段 403需要进 行多路的下变频、 滤波、 抽取和解调等处理过程， 再输出多路 bit流。 而对于单载波的情况， 则只需要进行一路滤波、 抽取和解调等处理， 然 后输出一路 bit流。
本发明实施例中，多支路校正前处理模块 401中所含的 M个固定增 益支路可以是含模拟 I&Q解调功能的固定增益支路，也可以是双通道固 定增益支路模块或单通道周定增益支路模块。 由于整个接收通道中只要 进行一次解调到模拟基带的处理 ,所以在模拟 I&Q解调功能之前的模拟 处理都是单通道的，而在模拟 I&Q解调功能之后的模拟处理都是双通道 的。双通道固定增益支路模块位于模拟 I&Q解调功能之后，其并行的两 个通道分别处理 I路和 Q路的模拟低通信号， 由于已经混频到基带， 所 以在处理通道中没有混频级。 单通道固定增益支路模块输入和输出都是 模拟带通信号， 但是输出信号频率较之输入信号频率可能已经发生变 化， 即在处理通道中可能有一级甚至多级混频处理。 不管是双通道还是 单通道固定增益支路模块， M个支路都是固定增益的， 而且 M个支路 形成一定的增益梯级，使 M个支路在同时刻的输出的信号在不饱和的情 况下具有不同幅度， 比如， 第一条支路输出信号的幅度最大， 第二条支 路输出信号的的幅度次之， 并依次类推。
梯级增益处理的方法一般有两种： 一种是并行式方法， 将每一个固 定增益支路模块的增益设置为大小不同的增益， M个支路完全是并行 的。 另外一种是阶梯式方法， 如图 9所示。
图 9中， 公共固定增益级模块 901是所有支路共用的。 各支路的增 益差主要是由固定增益梯级 1 模块 902-1 ~固定增益梯级 M-1 模块 902-M-1造成的。 而专用固定增益级 1模块 903-1 ~专用固定增益级 M 模块 902-M这些模块可以取相同的增益，也可以取不同的增益以形成进 一步的增益差。
图 9中的所有模块都可能含有混频级。 为了减少电路复杂性和提高 资源共用率， 只要性能允许应该尽量将所有混频级放在靠上游的模块 中。 如果将所有混频级放到图 9中的公共固定增益级或者更上游的电路 中， 会使整个接收机的资源最节省， 这在最大增益支路和最小增益支路 的增益差不大的情况下是完全可能的。 但是不排除最大增益支路和最小 增益支路的增益差较大的情况下图 9中的固定增益梯级 1 ~固定增益梯 级 M-1模块中含混频级的情况，这时在中间抽头引出的专用增益级中必 须补齐相应的混频级， 以使所有支路的输出频率相同。
多支路校正与切换模块 402内部结构如图 10所示，多支路校正与切 换模块 402至少包括： 幅相校正模块 1001、 M路选 1路控制模块 1002、 M路选 1路模块 1003。
其中， 幅相校正模块 1001包括 M个幅相校正乘法器， 即幅相校正 乘法器 1001 # 1至幅相校正乘法器 1001 # M, 用于根据由多支路校正前 处理模块 401输入的 M路数字基带信号和配置在自身中的幅相校正系数 来获得校正后的 M路数字基带信号 , 并输出给 M路选 1路模块 1003。
M路选 1路控制模块 1002，用于根据切换策略从多支路校正前处理 模块 401输入的 M路数字基带信号中确定一条支路，产生携带有该支路 号的切换控制信号， 并输出给 M路选 1路模块 1003。
M路选 1路模块 1003,用于根据由 M路选 1路控制模块 1002输入 的切换控制信号， 从由幅相校正模块 1001输入的 M路数字基带信号中 选择一路， 并输出给数字接收通道后段 403。 本发明实施例中，为了在幅相校正模块 1001中对从多支路校正前处 理模块 401输入的 M路数字基带信号进行校正，需要为每一支路配置相 应的幅相校正系数。 幅相校正乘法器的作用其实就是将表示为复数的数 字基带信号和表示为复数的幅相校正系数进行复数乘法运算， 改变数字 基带信号的幅度和相位， 使所有幅度充分大而又不饱和的支路的数字基 带信号的幅度和相位保持一致。 至于信号幅度过小或过大， 以致于低于 灵敏度或发生饱和的支路， 在经过校正后可能仍然无法使其幅度和相位 与正常支路保持一致， 但由于根据切换策略不会被作为输出经过校正的 数字基带信号的支路， 其校正情况此处不再赘述。
本发明实施例中， 配置幅相校正系数的方式有两种： 一种为离线配 置方式，即在接收机开始接收无线信号之前就将 M个幅相校正系数初始 值预先配置给幅相校正模块 1001 ,并且在接收机工作过程中始终保持不 变。这里，所述的在开始接收无线信号之前将 M个幅相校正系数初始值 预先配置给幅相校正模块又包括两种情况： 其一， 是接收机在出厂前就 将根据测试结果计算出来的幅相校正系数初始值固化到幅相校正模块 中； 其二， 是接收机上电开始工作时， 利用输入信号计算幅相校正系数 初始值， 并一次性配置给幅相校正模块。 本发明中， 离线配置方式适合 于接收机各个支路电路的相对特性比较稳定的情况。 这里所述的相对特 性指两个支路间的传输函数的比， M个.支路间的相对特性指的是 M个 支路之间的传输函数的比。 在支路输出信号幅度比较大而又不饱和的情 况下， 电路可以认为是线性的， 即可以用传输函数来描述。
另外一种方式是在线配置方法， 指接收机在上电开始工作后， 利用 输入信号计算幅相校正系数初始值，再将其配置给幅相校正模块。然后， 接收机定期或不定期地利用输入信号不断重新计算新的幅相校正系数， 以补偿各个支路电路相对特性随时间的变化。 本发明中， 在线配置方法 适合于接收机各个支路电路的相对特性不稳定的情况。
需要注意的是， 幅相校正模块 1001中的 M个幅相校正乘法器有两 个输入端， 其中一个由多支路校正前处理模块 401输入数字基带信号， 另夕 I、一个由幅相校正模块 1001 内的幅相校正系数寄存器输入幅相校正 系数。
对于离线配置的方式， 幅相校正系数初始值可以一次性写入幅相校 正系数寄存器中； 而对于在线配置方式， 则会将计算出来的新的幅相校 正系数不断地写入到幅相校正系数寄存器中。
另外， 本发明实施例中， 不管是离线配置还是在线配置， 都可以用 相似的方法进行 M个幅相校正系数的计算， 即幅相校正系数计算方法。 装置实施例一
本实施例中， 接收机的各个支路电路的相对特性稳定， 在接收机开 始接收工作信号之前， 一次性地计算和写入幅相校正系数初始值， 即釆 用离线配置方法， 并且在工作过程中不再改变幅相校正系数的值。
如图 11所示， 本实施例中， 接收机包括： 含模拟 I&Q解调功能的 上游模拟接收通道模块 1101、 M个双通道固定增益支路模块 1102、 M 个双通道模拟到数字转换器 1103、 幅相校正模块 1104、 M路选 1路控 制模块 1105、 M路选 1路模块 1106、 数字接收通道后段 1107。
其中, 含模拟 I&Q解调功能的上游模拟接收通道模块 1101， 包括 低噪声放大器和模拟 I&Q解调部分，用于将接收机输入信号进行含模拟 I&Q解调功能的上游模拟接收处理， 即放大、 混频等处理， 并将模拟带 通信号解调为模拟基带信号， 再输出给 M个双通道固定增益支路模块 1102。
M个双通道固定增益支路模块 1102,包括汉通道固定增益支路模块 1102 # 1至双通道固定增益支路模块 1102 # M, 用于将由含模拟 I&Q解 调功能的上游模拟接收通道模块 1101 输入的模拟基带信号进行梯级增 益处理， 并将处理后的 M路模拟基带信号输出给 M个双通道模拟到数 字转换器 1103。 这里， 每一路的模拟基带信号是一个复信号， 含 I路和 Q路两路并行的模拟信号。
M个汉通道模拟到数字转换器 1103 ,包括双通道模拟到数字转换器
1103 # 1至双通道模拟到数字转换器 1103 # M,用于将由 M个双通道固 定增益支路模块 1102输入的模拟基带信号进行釆样处理， 转换为数字 基带信号， 并分别输出给幅相校正模块 1104和 M路选 1路控制模块 1105。
幅相校正模块 1104, 包括幅相校正乘法器 1104 # 1至幅相校正乘法 器 1104 # M, 用于根据由 M个双通道模拟到数字转换器 1103输入的数 字基带信号和事先配置在自身中的幅相校正系数来获得校正后的数字 基带信号， 并输出给 M路选 1路模块 1106。
M路选 1路控制模块 1105， 用于根据本发明的切换策略， 从 M个 双通道模拟到数字转换器 1103输入的 M路数字基带信号中确定一条支 路， 产生携带有该支路号的切换控制信号， 再将切换控制信号输出给 M 路选 1路模块 1106。
M路选 1路模块 1106, 用于根据由 M路选 1路控制模块 1105输入 的切换控制信号， 从幅相校正模块 1104输入的 M路数字基带信号中选 择一路， 并输出给数字接收通道后段 1107。
数字接收通道后段 1107, 用于将 M路选 1路模块 1106输入的经过 校正的一路数字 I&Q基带进行进一步的数字处理， 获得并输出 bit流。
当接收机接收无线信号时，含模拟 I&Q解调功能的上游模拟接收通 道模块 1101先将信号形式为模拟带通信号的接收机输入信号进行放大、 模拟 I&Q解调等处理， 获得模拟基带信号， 并输出给 M个双通道固定 增益支路模块 1102;在双通道固定增益支路模块 1102中，Μ路模拟 I&Q 信号由各自的双通道固定增益支路模块经过梯级增益处理后， 被输出给 Μ个双通道模拟到数字转换器 1103; Μ个双通道模拟到数字转换器 1103 将输入的 Μ路模拟基带信号进行采样处理，得到数字基带信号， 并输出 给幅相校正模块 1104和 Μ路选 1路控制模块 1105;幅相校正模块 1104 将输入的信号进行幅相校正， 使支路间的数字基带信号在幅度和相位上 一致， 并输出给 Μ路选 1路模块 1106; Μ路选 1路控制模块 1105则根 据 Μ个双通道模拟到数字转换器 1103输入的 Μ路数字基带信号和切换 策略， 来确定幅度最大但未饱和的信号所在的支路， 并通过携带有该支 路号的切换控制信号通知给 Μ路选 1路模块 1106; Μ路选 1路模块 1106 根据由 Μ路选 1路控制模块 1105输入的切换控制信号选择一路校正后 的数字基带信号， 输出给数字接收通道后段 1107; 数字接收通道后段 1107将对 Μ路选 1路模块 1106输入的校正后的数字基带信号进行进一 步的滤波、 抽取、 解调等数字处理， 得到并输出 bit流。
在实际应用中，接收机也可以不包括含模拟 I&Q解调功能的上游模 拟接收通道模块 1101 , 而是将 M个双通道固定增益支路模块 1102替换 为 M个含模拟 I&Q解调功能的固定增益支路模块， 本发明方案也可以 实现。 - — - - 应用本实施例， 可以将所有幅度充分大而又不饱和的支路之间的数 字基带信号在幅度和相位上对齐， 可以实现逐点切换， 达到快速跟踪信 号变化的目的。 装置实施例二
本实施例中，接收机采用在线配置方法来配置幅相校正系数初始值， 并且在接收机工作的过程中， 根据接收机输入信号的变化， 不断地重新 计算和写入新的幅相校正系数。
如图 12所示， 本实施例中， 接收机包括： M个含模拟 I&Q解调功 能的固定增益支路模块 1201、 M个双通道模拟到数字转换器 1202、 M 个抽取滤波器模块 1203、 M个幅相校正前馈环时延补偿模块 1204、 幅 相校正模块 1205、 幅相校正系数计算模块 1206、 M路选 1路控制模块 1207、 切换前馈环时延补偿模块 1208、 M路选 1路模块 1209、 数字接 收通道后段 1210。
其中， M个含模拟 I&Q解调功能的固定增益支路模块 1201、 M个 双通道模拟到数字转换器 1202、 幅相校正模块 1205、 M路选 1路控制 模块 1207、 M路选 1路模块 1209、 数字接收通道后段 1210与装置实施 例一中对应模块的功能相似， 其区别在于： M个含模拟 I&Q解调功能 的固定增益支路模块 1201 不但可以将接收机输入信号进行梯級增益处 理， 而且可以进行模拟 I&Q解调； M路选 1路控制模块 1207还将根据 切换策略产生切换标志信号。
本实施例中， M个抽取滤波器模块 1203 , 用于对由 M个双通道模 拟到数字转换器 1202输入的数字基带信号作进一步的抽取处理， 并分 别输出给 M个幅相校正前馈环时延补偿模块 1204、 幅相校正系数计算 模块 1206和 M路选 1路控制模块 1207。 .
M个幅相校正前馈环时延补偿模块 1204, 用于将由 M个抽取滤波 器模块 1203 输入的数字基带信号进行时延补偿， 并输出给幅相校正模 块 1205。
幅相校正系数计算模块 1206，用于根据由 M个抽取滤波器模块 1203 输入的数字基带信号进行幅相校正系数的计算，并根据 M路选 1路控制 模块 1207输入的切换标志信号， 将计算出来的幅相校正系数输出给幅 相校正模块 1205。
在实际应用中，幅相校正系数计算模块 1206还可以根据由幅相校正 模块 1205输入的经过幅相校正的数字基带信号进行幅相校正系数的计 算， 并根据 M路选 1路控制模块 1207输入的切换标志信号， 将计算出 来的幅相校正系数输出给幅相校正模块 1205, 即构成一个反馈环。 需要 注意的是， 如果幅相校正系数计算模块 1206根据由幅相校正模块 1205 输入的数字基带信号进行幅相校正系数的计算时， 由于此时的数字基带 信号已经经过了幅相校正， 所以在计算新的幅相校正系数时， 需要去除 原来幅相校正系数的影响。
切换前馈环时延补偿模块 1208, 用于将 M路选 1路控制模块 1207 输入的切换控制信号进行时延补偿， 并输出给 M路选 1路模块 1209。
本实施例中， 当接收机接收无线信号时 , 接收机输入信号首先输入 给 M个含模拟 I&Q解调功能的固定增益支路模块 1201 , 进行梯级增益 处理和模拟 I&Q解调等处理， 获得模拟基带信号， 再输出给 M个模拟 到数字转换器 1202; M个模拟到数字转换器 1202将输入的 M路模拟基 带信号进行釆样处理，得到数字基带信号， 并输出给 M个抽取滤波器模 块 1203; M个抽取滤波器模块 1203将信号进行抽取， 并分别输出给 M 个幅相校正前馈环时延补偿模块 1204、 幅相校正系数计算模块 1206和 M路选 1路控制模块 1207; M个幅相校正前馈环时延补偿模块 1204将 输入信号延时处理并输出给幅相校正模块 1205,幅相校正系数计算模块 1206根据 M个抽取滤波器模块 1203输入的 M路数字基带信号计算 M 个幅相校正系数； M路选 1路控制模块 1207根据切换策略确定一条支 路， 产生切换控制信号并输出给 M路选 1路模块 1208， 并根据判断是 否需要切换到新的支路而产生切换标志信号， 并将切换标志信号输出给 幅相校正系数计算模块 1206; 幅相校正系数计算模块 1206根据 M路选 1路控制模块 1207输入的切换标志信号将计算出来的 M个幅相校正系 数配置给幅相校正模块 1205; 幅相校正模块 1205根据由 M个幅相校正 前馈环时延补偿模块 1204输入的 M路数字基带信号 , 和由幅相校正系 数计算模块 1206输入的幅相校正系数进行信号作复数相乘， 使支路间 的数字基带信号在幅度和相位上一致， 即完成幅相校正，并输出给 M路 选 1路模块 1209; M路选 1路模块 1209根据由切换前馈环时延补偿模 块 1208输入的经过时延补偿的切换控制信号选择一路数字基带信号， 并输出给数字接收通道后段 1210; 数字接收通道后段 1210将由 M路选 1路模块 1209输入的一路数字基带信号作进一步的抽取、滤波和解调等 数字处理， 最后得到并输出 bit流。
本实施例中， 由于接收机各支路可能会随时间和温度发生变化， 导 致各个支路电路的相对特性不稳定， 所以采用了在线配置幅相校正系数 的方法， 则 M个含模拟 I&Q解调功能的固定增益支路模块 1201、 M个 模拟到数字转换器 1202、 幅相校正模块 1205、 幅相校正系数计算模块 1206、 M路选 1路控制模块 1207、 M路选 1路模块 1209、 数字接收通 道后段 1210是必要的， 其它模块可以根据实际情况进行取舍。
在实际应用中， 为了节省数字资源， 可以增加 M个抽取滤波器模块 1203 , 即先对需要算计的信号进行抽取， 使输入幅相校正模块 1205 和 幅相校正系数计算模块 1206等模块的信号通过率减少，. 降低模块的数 字处理量和对资源的需求。
为了在需要切换时给幅相校正模块 1205及时重新配置最新的幅相 校正系数， 使当前样点或本次计算幅相校正系数的样点可以通过幅相校 正模块 1205进行幅相校正，图 12中使用 M个幅相校正前馈环时延补偿 模块 1204来弥补幅相校正系数计算所产生的时延。 在实际应用中， 在 幅相校正系数计算所产生的时延小于幅相校正模块的时延的情况下， M 个幅相校正前馈环时延补偿模块 1204还可以位于幅相校正系数计算模 块 1206和幅相校正模块 1205之间，即 M个幅相校正前馈环时延补偿模 块 1204用于将由幅相校正系数计算模块 1206输入的 M个幅相校正系数 进行时延补偿之后， 再输出给幅相校正模块 1205。 当然， 在幅相校正系 数计算所产生的时延和幅相校正模块的时延相等的情况下， 可以不需要
M个幅相校正前馈环时延补偿模块 1204。
另外，切换前馈环时延补偿模块 1208的作用是为了保证对应于同一 个样点的切换控制信号与经过校正的 M路数字基带信号可以同时到达 M路选 1路模块。图 12中的切换前馈环时延补偿模块 1208模块位于 M 路选 1路控制模块 1207和 M路选 1路模块 1209之间， 适合于 M个幅 相校正前馈环时延补偿模块 1204和幅相校正模块 1205的处理总延时大 于 M路选 1路控制模块 1207的处理延时的假设的。
' 但在实际应用中， 如杲 M个幅相校正前馈环时延补偿模块 1204和 幅相校正模块 1205的处理总延时正好等于 M路选 1路控制模块 1207 的处理延时， 就不用进行切换前馈环时延补偿， 即不需要切换前馈环时 延补偿模块 1208。
在实际应用中， 如果 M个幅相校正前馈环时延补偿模块 1204和幅 相校正模块 1205的处理总延时小于 M路选 1路控制模块 1207的处理延 时， 切换前馈环时延补偿模块 1208就必须位于信号通道上。 由于 M个 幅相校正前馈环时延补偿模块 1204、 幅相校正模块 1205和幅相校正系 数计算模块 1206这 3个模块组成了一个前馈环， 为了不和幅相校正前 馈环的时延补偿产生耦合， 切换前馈环时延补偿模块 1208模块最好在 这个前馈环之外插入， 即连接关系可以为： M个抽取滤波器模块 1203 将抽取后的 M路数字基带信号输出给切换前馈环时延补偿模块 1208和 M路选 1路控制模块 1207;切换前馈环时延补偿模块 1208将 M个抽取 滤波器模块 1203输入的 M路数字基带信号进行时延补偿， 再输出给 M 个幅相校正前馈环时延补偿模块 1204模块， 其它模块的连接关系保持 不变。 连接关系也可以为： 幅相校正模块 1205将校正后的 M路数字基 带信号输出给切换前馈环时延补偿模块 1208; 由切换前馈环时延补偿模 块 1208进行时延补偿， 再输出给 M路选 1路模块 1209, 其它的连接关 系保持不变。 但由于经过幅相校正之后， 非同时动态的增加造成信号定 点位宽有所增加， 所以将切换前馈环时延补偿模块 1208置于 M个抽取 滤波器模块 1203模块和 M个幅相校正前馈环时延补偿模块 1204模块之 间可以节约资源。
在实际应用中， 如果各个支路电路的相对幅相特性稳定， 只需要接 收机在初始化时将计算出来的幅相校正系数一次性配置给幅相校正模 块 1205， 并且以后不再更改， 就可以没有幅相校正系数计算模块 1206。
在实际应用中， 当幅相校正系数计算模块 1206接收到 M路选 1路 控制模块 1207输入的切换标志信号时， 可以立即将最近计算出来的幅 相校正系数配置给幅相校正模块 1205,也可以只有在自上次配置幅相校 正系数之后， 幅相校正系数计算模块 1206 又计算出了新的幅相校正系 数时， 幅相校正系数计算模块 1206 才将新的幅相校正系数配置给幅相 校正模块 1205。 装置实施例三
本实施例中， 接收机采用在线配置的方法来配置幅相校正系数初始 值，可以在接收无线信号的过程中根据获得的 M路数字基带信号重新计 算幅相校正系数， 并且将新的幅相校正系数的值配置给幅相校正模块， 然后幅相校正模块将利用幅相校正系数新值来进行校正处理。
如图 13所示， 本实施例中， 接收机包括： 校正信号注入模块 1301、 M 个单通道固定增益支路模块 1302、 M 个单通道模拟到数字转换器 1303、 时延校正模块 1304、 M个抽取模块 1305、 M个幅相校正前馈环 时延补偿模块 1306、 幅相校正模块 1307、 幅相校正系数计算模块 1308、 M路选 1路控制模块 1309、 切换前馈环时延补偿模块 1310、 M路选 1 路模块 1311、 数字接收通道后段 1312。
其中， M个单通道固定增益支路模块 1302、 M个单通道模拟到数字 转换器 1303、 M个幅相校正前馈环时延补偿模块 1306、 幅相校正模块 1307、 幅相校正系数计算模块 1308、 M路选 1路控制模块 1309、 切换 前馈环时延补偿模块 1310、 M路选 1路模块 1311、 数字接收通道后段 1312与装置实施二所对应的模块相似，其主要区别在于： M个抽取模块 1305用于将输入的 M路数字基带信号进行抽取而不再进行滤波处理； M个单通道固定增益支路模块 1302不含模拟 I&Q解调功能； M个单通 道模拟到数字转换器 1303每个只有一路 ADC。
另外， 在本实施例中， 时延校正模块 1304 包括数字下变频模块 1304S! , M个低通滤波器模块 1304S2、 时延校正系数计算模块 1304S3、 滤波器系数计算模块 1304S4; 时延校正模块 1304用于根据由 M个模拟 到数字转换器 1303输入的数字带通信号进行数字 I&Q解调处理和时延 校正处理，得到在时间完全一致的数字基带信号， 并输出给 M个抽取模 块 1305。 -. . - - 实际上， 数字下变频模块
Figure imgf000026_0001
M个低通滤波器模块 1304S2就 是图 Ί中的数字 I&Q解调部分 703 , 是多支路校正前处理模块 401中的 一部分， 而本实施例中利用了数字 I&Q解调部分 703进行时延校正， 为 了名称上的统一， 这里也可以将数字 I&Q解调部分 703、 时延校正系数 计算模块 1304S3和滤波器系数计算模块 1304S4统称为时延校正模块 1304。 本实施例中， 时延校正模块 1304可以实现时延校正的原理为：数字 下变频模块 1304S!将来自 M个单通道模拟到数字转换器 1303的数字带 通信号的频语搬移到中心频率为 0频率的位置，并输出 M个低通滤波器 模块 1304S2; M个低通滤波器模块 1304S2对输入的信号进行低通滤波 处理，以滤除数字镜像和其它干扰信号，根据滤波器系数进行时延校正， 得到 IV [路数字基带信号，输出给 M个抽取模块 1305和时延校正系数计 算模块 1304S3; 时延校正系数计算模块 1304S3根据 M个低通滤波器模 块 1304S2输入的 M路数字基带信号信号计算 M路信号的时延校正系数， 并将时延校正系数输出给滤波器系数计算模块 1304S4, 滤波器系数计.算 模块 1304S4根据输入的时延校正系数计算滤波器系数， 再配置给 M个 低通滤波器模块 1304S2。
本文获取数字 I&Q信号的叙述是基于先数字下变频再低通滤波的 顺序的。在实际应用中，获取数字 I&Q信号可以使用先单边带通滤波再 数字下变频的顺序。 即 M个单通道模拟到数字转换器 1303可以将数字 带通信号先输出给 M个单边带通滤波器模块， 经过 M个单边带通滤波 器模块进行单边带通滤波和时延校正之后， 再输出给数字下变频模块 1304S 单边带通滤波为复数滤波器， 是基于负采样频率之半到正采样 频率之半之间的频率范围内的 Nyquist带宽的， 可以根据信号调制和收 发^字与模拟本振设置的不同情况， 只保留正频率轴或^频率轴上的信 号谱。 不管是信号频傳位于正频率轴还是负频率轴， 只要是将信号频谱 搬移到 0频率， 就统一称为下变频。 在使用先单边带通滤波再数字下变 频的顺序中， 由于滤波器形式和处理顺序的改变， 进行时延校正的滤波 器系数也要相应改变。
在实际应用中， 如果接收机多支路的电路特性比较稳定， 也可以与 配置幅相校正系数初始值一样， 采用离线配置的方法来配置滤波器系数 初始值。 也就是说， 在实际应用中， 可以不包括时延校正系数计算模块
1304S3和滤波器系数计算模块 1304S4, 而是将时延校正系数事先保存在 M个低通滤波器中。 比如： 可以使用 EPROM和 FLASH等非挥发性器 件固化在低通滤波器中， 也可以在上电和复位时一次性写入低通滤波 器。
另外， 校正信号注入模块 1301 , 用于在接收机初始化或空闲时产生 用于校正的信号， 并输出给 M个固定增益支路模块 1302。
图 14和图 15显示了校正信号注入模块 1301内部框图。 如图 14所 示， 校正信号注入模块 1301 包括开关模块 1401 和校正信号产生模块 1402。 其中， 开关模块 1401 用于将从天线等传感器接收的接收机输入 信号和校正信号产生模块 1402产生的校正信号输出给 M个固定增益支 路模块 1302。 当然， 开关模块 1401需要分时传输上述的两种信号， 在 有接收机输入信号时必须输出接收机输入信号 , 在接收机初始化时或接 收机空闲时可以输出校正信号用于校正系数的计算。 在实际应用中， 开 关模块 1401可以用电子开关来实现， 而校正信号产生模块 1402则可以 用振荡器来实现。 至于开关模块如何分时传输不同的信号， 则可以由接 收机中的系统时序信号来控制， 比较容易实现， 此处不再赘述。
如图 15所示， 校正信号注入模块 1301也可以包括开关模块 1501 和校正信号转换模块 1502, 图 14与图 15相似， 其区-别主要在于： 如果- 在实际应用中， 接收机是与发射机并存的 , 那么校正信号可以不由振荡 器自身产生， 而是由发射机在发射信号时将要发射的信号输入给校正信 号转换模块 1502, 校正信号转换模块 1502再将由发射机输入的信号转 换为可以用于校正的信号。
本实施例中， 由于需要进行时延校正和幅相校正， 所以， M个单通 道固定增益支路模块 1302、 M个单通道模拟到数字转换器 1303、 数字 下变频模块 1304S M个低通滤波器模块 1304S2、 幅相校正模块 1307、 M路选 1路控制模块 1309、 M路选 1路模块 1311、 数字接收通道后段 1312是必须的， 而其它的模块都可以根据实际情况任意选择。 当然， 在 实际应用中，接收机还可以包括不含模拟 I&Q解调功能的上游模拟接收 通道模块， 其功能与连接关系与装置实施例一中的相应的模块类似， 只 是不含模拟 I&Q解调功能， 即校正信号注入模块 1301的开关模块 1401 的输入来自不含模拟 I&Q解调功能的上游模拟接收通道模块和校正信 号产生模块 1402或校正信号转换模块 1502, 此处不再赘述。 装置实施例四
如图 16所示, 本实施例中， 接收机包括： 校正信号注入模块 1601、 M个含模拟 I&Q解调功能的固定增益支路模块 1602、 M个欢通道模拟 到数字转换器 1603、 时延校正模块 1604、 M个抽取模块 1605、 M个幅 相校正前馈环时延补偿模块 1606、 幅相校正模块 1607、 幅相校正系数 计算模块 1608、 M路选 1路控制模块 1609、 切换前馈环时延补偿模块 1610、 M路选 1路模块 1611、 数字接收通道后段 1612。
本实施例与装置实施例三相似， 其区别在于： 由于本实施例的固定 增益支路模块是含模拟 I&Q解调功能的固定增益支路模块， 即 M个含 模拟 I&Q解调功能的固定增益支路模块 1602, 所以在本实施例中不包 括数字 I&Q解调部分； 由于本实施例无法利用数字 I&Q解调部分的低 通滤波器进行时延校正，所以需要在接收机中增加 M个低通滤波器模块 1604Si, 时延校正系数计算模块 1604S2、 滤波器系数计算模块 1604S3。 其中， 与装置实施例三相同， 时延校正系数计算模块 1604S2和滤波器系 数计算模块 1604S3可以根据实际情况任意选择。
实际应用中， 还可以在 M个双通道模拟到数字转换器 1603和时延 校正模块 1604之间增加一个直流与 I&Q平衡校正模块， 用于去除电路 误差， 这里所述的电路误差包括由电路引入的 I路和 Q路信号中的直流 误差， 以及 I路和 Q路之间的幅度和相位误差。
本实施例其它模块的功能和连接关系与装置实施例三相似， 此处不 再伴细叙述。
总之， 在实际应用中， 多支路校正前处理模块 401中通过哪个部分 实现 I&Q解调；多支路校正与切换模块 402中的幅相校正系数初始值是 采用离线配置方法， 还是采用在线配置方法， 即是否包括幅相校正系数 计算模块； 固定增益支路模块是采用并行式或是阶梯式的； 是否需要对 信号进行抽取； 是否需要在接收机工作过程中进行时延补偿； 是否需要 对幅相校正前的信号进行时延校正； 时延校正系数是采用离线配置方 法， 还是采用在线配置方法， 即是否包括时延校正系数计算模块和滤波 器系数计算模块； 是否包括直流与 I&Q平衡校正模块； 是否包括校正信 号注入模块等都与实际设计接收机相关， 可以^ ^据实际情况产生不同的 组合， 这里就不再——列举这些情况的组合所能组成的装置结构。
应用本发明实施例方案， 可以将模拟带通信号形式的接收机输入信 号处理为在时间、 幅度、 相位上都对齐的数字基带信号， 然后根据切换 策略选择一路输出。 由于本发明将信号的时间、 幅度、 相位都经过了校 正， 所以当根据切换策略需要从当前的-一条支路切换到另外一条支路 时， 就可以逐点切换， 即切换的时间粒度小于数字基带信号两个样点之 间的时间距离， 可以达到快速跟踪信号变化的目的， 从而增加了非同时 动态范围， 提高了接收机的性能。 针对本发明提供的装置，本发明还提供了一种实现接收无线信号的 方法，其核心思想是：接收机将接收机输入信号处理为 M路数字基带信 号以后，先将 M路数字基带信号进行幅度和相位校正，再根据切换策略 选择一路输出， 最后进行数字处理获得 bit流。
图 17是本发明.实施例实现接收无线信号方法的流程图。如图 17所 示， 本发明实施例实现接收无线信号方法包括以下步骤：
步骤 1701 : 多支路校正前处理模块将接收机输入信号转换为 M路 数字基带信号， 并输出给多支路校正与切换模块。
多支路校正前处理模块一般通过梯级增益处理、 基带解调、 数字采 样等过程， 可以将信号形式为模拟带通信号的接收机输入信号转换为数 字基带信号。
步骤 1702: 多支路校正与切换模块将获得的 M路数字基带信号进 行幅度和相位校正， 并根据切换策略选择一路数字基带信号输出给数字 接收通道后段。
步骤 1703:数字接收通道后段对输入的一路数字基带信号作进一步 的数字处理， 输出 bit流。
本发明实施例中，在支路输出信号幅度比较大而又不饱和的情况下， 可以认为电路是线性的， 可以用传输函数来描述。 每一条支路的传输函 数的形式为：
A(y |A(/)lexp (/))， 其中， /表示信号频率， 表示相位， i表示支路所对应的支路号， l≤i≤M。
另外， 在实际应用中， 可以认为：
1 ) |H,( )h A|^( )| ' Α > 0 , Ρ,.表示支路的幅度响应值， 可以随支 路号 而不同， 但是较短时间内可以认为是基本不变的；
2 ) , { ) = 2 ι + Ψι , r,.和 (Pi分别为支路的时延响应值和相位响应值， 可能随支路号 Z '而不同， 但是较短时间内可以认为是基本不变的； 3 ) |H(/)|在系统频带内是平坦的， 即使有一些不平坦也不需要进行 带内均衡。
从以上的传输函数形式可以知道接收机输入信号通过 M条支路后 的信号的差异体现在 M个时延特性值 r、 M个幅度特性值 A和 M个相 位特性值 上， 其中 i=l~M。 但是， 在实际应用中， 如果接收机支路之 间不存在时延误差， 或者时延误差可以忽略的情况下， 则接收机输入信 号通过 M条支路后的信号的差异就可以只体现在 M个幅度特性值 Ρί和 Μ个相位特性值 上， 这正在本发明需要进行幅相校正的原因。 也就是 说，如果将经过多支路校正前处理模块获得的 M路数字基带信号进行幅 度和相位校正， 使所有支路中幅度充分大而又未饱和的信号在幅度和相 位上保持一致，就可以在从 M路选 1路输出信号时达到逐点切换，快速 跟踪信号变化。
在本发明实施例中， 多支路校正前处理方法可以有以下几种方法：
( 1 )参见图 5， 含模拟 I&Q解调功能的上游模拟接收通道模块将 模拟带通信号进行放大、 混频和模拟 I&Q解调等处理，将接收机输入信 号转换为模拟基带信号，并输出给 M个双通道固定增益支路模块； M个 双通道固定增益支路模块将模拟基带信号通过 M条支路进行梯级增益 处理， 再输出给 M个双通道模拟到数字转换器; M个双通道模拟到数 字转换—器对模拟基带信号进行采样处理， 获得数字基带信号。
( 2 )参见图 6, M个含模拟 I&Q解调功能的固定增益支路模块首 先将模拟带通信号通过 M条含模拟 I&Q解调功能的支路进行梯级增益 处理， 获得 M路模拟基带信号， 并输出给 M个双通道模拟到数字转换 器； M个双通道模拟到数字转换器对模拟基带信号进行采样处理， 获 得数字基带信号。 ( 3 )参见图 7， M个单通道固定增益支路模块首先将模拟带通信号 通过 M条支路进行梯级增益处理， 并输出给 M个单通道模拟到数字转 换器； M个单通道模拟到数字转换器对模拟带通信号进行采样处理， 获 得 M路数字带通信号， 并输出给数字 I&Q解调部分； 数字 I&Q解调部 分将 M路数字带通信号进行数字 I&Q解调处理， 获得数字基带信号。
当然， 在上述第 2种和第 3种方法中， 本发明在进行梯级增益处理 之前， 还可以首先将接收机输入信号进行放大和混频等处理。
这里， 接收机输入的信号为模拟带通信号， 为实信号。 接收机进行 I&Q解调也就是将实信号变换为复信号， 是一个必要的步驟。 需要注意 的是，本发明所述的 I&Q解调中的"解调"二字并不是通常意义上的恢复 调制前的星座图上的信号符号， 而是指先将带通信号的载波中心频率搬 移到 0频率的位置， 然后进行低通滤波处理， 以滤除镜像和其它干扰信 号， 获得 I&Q信号的过程。 这里的 0频率即 0 Hz。 如果在模拟信号处 理阶段进行频率搬移和模拟低通滤波， 就为模拟 I&Q解调； 如果在数字 信号处理阶段进行频率搬移和数字低通滤波， 则为数字 I&Q解调。
对于多载波接收机， 即接收机输入信号含有多个载波， 需要在数字 接收通道后段模块中， 将接收到的数字基带信号进行进一步下变频处 理，即将每一个载波的中心频率分别 移到 0频率的位置，再进行滤波、 抽取处理， 获得对应于多个载波的炎路基带信号， 最后经过解调得到多 路 bit流。
对于单载波接收机，即接收机输入信号只有一个载波,那么经过 I&Q 解调以后， 已经可以获得唯一的基带信号了， 就无需在数字接收通道后 段模块进行下变频处理， 而只需要进行滤波、 抽取处理， 然后经过解调 得到一路 bit流。
由于数字基带信号的模值从形状上反映了接收机输入信号的包络的 形状， 所以数字基带信号也常常被称为复包络。 本发明下述的样点、 数 字基带信号或复包络的含义是一样的。 其中， 样点是数字基带信号的每 一个采样点 , 而样点的功率就是该样点所在复包络的功率。 本发明实施例中， 多支路校正与切换模块将 M路数字基带信号进 行幅度和相位校正， 其关键是需要给幅相校正模块配置幅相校正系数。 配置幅相 正系数的方式一般分为两种： 一种是离线配置方式， 另夕 I、一 种是在线配置方式。 但'不管采用哪种方式， 幅相校正系数的计算过程是 类似的。
为了更好地理解本发明实施例， 下面对幅相校正系数的计算方法进 行详细的描述：
假设本发明实施例的接收机共 M条支路， M条支路的增益分别为 G GM , 其中， 第 1条支路的增益最高， 第 2条支路的增益次之， 依此 类推， 第 M条支路的增益最小。 另夕卜， 规定第 1条支路和第 2条支路为 第 1对相邻支路对， 其增益差， 即(^ - G2 , 为 ； 第 2条支路和第 3 条支路为第 2对相邻支路， 其增益差为 AG2 ; 依此类推， 第 M-1条支路 和第 M条支路为第 M - 1对相邻支路对， 其增益差为 M M—X。
另夕卜，校正前的数字基带信号可以表示为 («) , xk (n) = ik (n) + jqk (n) , ζ·»和^ »为[- U)范围的定点数' 即复包络幅度 满足 | (»)|≤1。 这 里 k表示第 k条支路， n表示第 n号样点， 并且假设样点为经过了抽取 率为 ?的抽取之后的， 即样点间隔为 ?rs。 如果将 ¾(/7)的功率定义为 101og10 j¾ (n)|2 ) dBFS, 则当 卜 1时， 复包络功率则为 0 dBFS。
从上述的定义中可以很容易地知道， 如果某支路信号校正前的功率 为 O dBFS, 则表示该条支路为临界饱和。 但在实际应用中， 为了防止包 絡失真而导致 ADC饱和，一般会为每一条支路分别设置包络回退^ ¾ , 当复包络功率大于- SC¾ dBFS时就可以认为该支路已经饱和。所以， 当 本发明利用切换策略选择输出第 n号样点的支路时， 就可以从所有第 n 号样点功率小于或等于- BCEk dBFS 的支路中选择一条信号幅度最大或 增益最大的支路， 并将其作为输出第 n号样点的支路。
本发明实施例中， 计算幅相校正系数的方法包括以下步骤： 步骤 1: 各相邻支路对对输入样点进行筛选， 确定将用于进行相对 幅相校正计算的样点。
由于本发明实施例有 M条支路，同一输入信号经过多支路校正前处 理模块 401处理后的同一个样点在幅度和相位上不同， 如果能计算出 M 条支路上同一个样点之间幅度和相位的差异 , 那么就可以对各条支路在 幅度和相位进行不同的补偿，使补偿后的 M条支路上的数字基带信号在 幅度和相位上保持一致， 从而达到校正的目的。
但是， 从每对相邻支路对来说， 并不是每一个样点都适合用来进行 该相邻支路对的相对幅相校正计算。 比如在某个样点上， 某相邻支路对 中的一个支路的 A C 已经饱和， 明显该支路的输出信号不能反映该支 路增益的真实大小， 所以该样点不应该用于计算该支路对相对幅相校正 系数。 所以， 本发明实施例为每一对相邻支路对设置了幅相校正窗口， 幅相校正窗口位于接近 ADC满刻度而又不致饱和的地方。 规定只有落 在幅相校正窗口中的信号样点才被选中来进行该相邻支路对的相对幅 相校正计算， 这称为幅相校正信号的筛选， 其筛选条件可以用以下公式 表示：
WAP,k≤PM〈-
Figure imgf000035_0001
-ΨΑΡ -AGk≤ΡΜ( ) <-ΒΟΕ, -AGk
其中， l≤k≤M-l , AP表示幅相校正， 表示第 k条支路的包络 回退值， [- ^ - w^-BCi^)表示第 k对相邻支路对的高增益支路的幅 相校正窗口， [-BCEk - W^ - G. -BCE, 表示第 k对相邻支路对的 低增益支路的幅相校正窗口。 A表示第 k对相邻支路对幅相校正窗口 宽度， 最小可以取得接近 0, 最大可以取为无穷大。 当^^取值为 无穷大时， 只要第 k支路不饱和， 样点就将落在第 k对相邻支路对幅相 校正窗口内。 表示第 k条支路的第 n号样点的功率大小， Pi+1(«)表 示第 k条支路的第 n + 1号样点的功率大小， 表示第 k对相邻支路对 的增益差。 从以上公式可以知道， 在第 k对相邻支路对中， 只有在第 k 条支路上的第 n号样点的功率值在- 3C¾ - ^^和 - SC¾之间， 同时， 第 k + 1条支路上的第 n号样点的功率值在- Δ(¾和-^ ¾ - Δ<5 之间时， 第 η号样点才能作为进行第 k对相邻支路对相对幅相校正计算 的样点。
' 在实际应用中， 如果某样点落在多个相邻支路对的幅相校正窗口之 中， 则可以同时作为多个相邻支路对之间相对幅相校正计算的样点。
步骤 2: 根据各相邻支路对中高增益支路的上次功率值迭代和以及 高增益支路的本次样点功率值来计算高增益支路的本次功率值迭代和， 根据相邻支路对中低增益支路的上次功率值迭代和以及低增益支路的 本次样点功率来计算低增益支路的本次功率值迭代和， 根据相邻支路对 的上次互相关值迭代和以及本次样点互相关值来计算相邻支路对本次 互相关值迭代和。
假设; ^( ^)表示进行第 k对相邻支路对本次幅相校正系数计算时 的样点号， 即第 n号样点落在第 k对相邻支路对的幅相校正窗口中， 并 且第 n号样点是第 / 次落入第 k对相邻支路对的幅相校正窗口中； 假 设 Pk,H JAP,, )和 Pk,H - 1)分别为相邻支路对中高增益支路第 次和第 AP,k 1次功率值迭代和，即高增益支路的本次功率值迭代和以及高增益 支路的上次功率值迭代和； Pk,L (l^ )和 Pk,L l^k - 1)分别表示相邻支路对的 低增益支路的第^ 次和第 - 1次功率值迭代和， 即低增益支路的本 次功率值迭代和以及上次功率值迭代和； (l^ )和 Rk (l^ - 1)分别表示 相邻支路对第 次和第 - 1次的互相关值迭代和， 即相邻支路对的 本次样点互相关值迭代和以及上次互相关值迭代和。
高增益支路的功率值迭代和、 低增益支路的功率值迭代和以及相邻 支路对的互相关值迭代和的初始值设置为 0, 即上电或者复位之后， Pk,H W、 ^(0)和 ?^(0)的值为 0。
高增益支路的本次功率值迭代和、 低增益支路的本次功率值迭代和
Pk,H APJC )
Figure imgf000037_0001
QAP -
P L APJ ) = (1 _ aAP,k ^APJ iUAP (^AP,k )) + aAP,lc QAPJC ^lc,L AP,k
RAP AP,/ ) = (1一 AP,k QAPJC ))Xk (NAP (^AP,k ))ΧΜ (NAP (^AP,k )) + AAP,k H,k )^AP,k (^AP,k 其中' 表示第 k对相邻支路对的 "滤波上次值权重， 筒称 α - 系数， 表示第 号样点的信号值， 表 的共轭， | (/^(/^))|2表示高增益支路的本次样点功率值，
|¾+,(^(^;,))|2 表 示 低 增 益 支 路 的 本 次 样 点 功 率 值 ， 表示相邻支路对的本次互相关值。 的取 值与第 k对相邻支路对的电路特性相关， 一般在电路特性基本不变的时 间尺度上取值近似为 1 , 以形成相干累加的效果； 而在电路特性发生较 大变化的时间尺度上的取值近似为 0, 以去除上次电路特性对当前计算 值的影响。
在 实 际 应 用 中 ， 可 以 设 aAP,ku =
Ui( AA )-"APU TS) , 其中' ^^是与第 k对相邻支路对电 路特性有关的量， 为样点之间的时间差值， 一般非常小， 接近于 0。 从" ^Ο^) = (^^)Λ(('½^^)- "^O^- 公式中可以知道， 当第 k 对相邻支路对电路特性基本不变时， 相邻两次落在第 k对相邻支路对的 幅相校正窗口样点的时间间隔应该不大， 即 (l^ )― nAP (l^ - l))RTS的 值仍然非常小， 则
Figure imgf000038_0001
1但是非 常接近 1的数。 而如果第 k对相邻支路对电路特性变化较大时， 相邻两 次落在第 k对相邻支路对的幅相校正窗口样点的时间间隔应该比较大， 即 "AP(JAP -"APU TS 的 值 比 较 大 ， 则 (^)Λ(('^(^)-^(^ - 是一个接近于 0的正数。
在实际应用中， 由于将 直接用于 α滤波进行计算比较复 杂' 则可以生成一个" U- "(/^ - 1)到 ^ ^) -" ^ (！ k -1))RTS) 的转换表。 1)的值可以利用计数器来得到， 即计数器 每隔 ?rs就加 1, 在需要计算新的功率累计值时， 根据计数器记录的
^( )-^(^-i) 从 转 换 表 中 直 接 得 到
Figure imgf000038_0002
ΑΡΛ - ) , 并直接用于计算新的功率累计值， 然 后将计数器清零。
当然， 在实际应用中， 如果第 k对相邻支路对可以保证在电路幅相 特性基本不变的时间尺度上都有足够多的幅相校正信号样点， 则可以将 事先设置为一个小于 1且接近于 1的值， 从而减少计算量。 步骤 3: 根据相邻支路对的高增益支路的本次功率值迭代和、 低增 益支路的本次功率值迭代和， 以及相邻支路对的本次相关累计值来计算 相邻支路对的相对幅相校正系数。
相邻支路对的相对幅相校正系数可以由以下公式表示：
' AP,k lAP,k
Figure imgf000039_0001
其中， 表示第 k对相邻支路对的相对幅相校正系数，。^ 表示第 k对相邻支路对之间的幅度差异， 表示第 k对相邻支路对 之间的相位差异。根据前面的 Pk,U 、 和^^ (^ Λ)的计算公式， 可以知道^ ½2表示了第 k对相邻支路对高增益支路相对于低增益支 路的功率倍数， 的复角度表示了第 k对相邻支路对高增益支路 相对于低增益支路的相位提前量。 由于功率之比为幅度之比的平方， 所 rk,L lAP,k
以将 乘到高增益支路信号上之后，高低增益支路的输出信号 的幅度就相同了。 低增益 支路的输出信号 即第 k
Figure imgf000039_0002
对相邻支路对之间的幅度差异可以根据高增益支路和低增益支路的功 率累计值计算得到， 而 ( )= ( 即第 k对相邻支路对之 间的相位差异可以根据互相关功率累计值及其共轭计算得到。
步骤 4: 根据所有相邻支路之间的相对幅相校正系数获得全体幅相 校正系数。
为了计算全体幅相校正系数， 需要事先将某一条支路确定为参考支 路， 参考支路确定之后就是固定的， 每次计算全体幅相校正系数都要使 用这个支路作为参考支路。 每次计算全体幅相校正系数时， 参考支路的 幅相校正系数都为 1, 保持不变。 其余支路都以该参考支路为标准来重 新计算， 得到新的幅相校正系数。 假设将第 APREF条支路设置为参考支路， 1<APREF<M, 全体幅 相校正系数的计算则可以用以下公式表示：
APREF-1
CAP,k = TlrAP ， k = \~ APREF -1
i=k
CAP,APREF二 1 k-l 1
= Y[——， k = APREF + 1〜M
i=APREF rAP,i
其中， 7 ，,.表示第 i对相邻支路对的相对幅相校正系数， 1≤ i≤M-l。 当 k≤APREF- 1时， 第 k条支路的幅相校正系数为第 k对到第 APREF
APREF-l
-1对相邻支路对的相对幅相校正系数的连乘积， 即^ Λ= [rAPi； 当 k
= APREF 时， 第 k 条支路的幅相校正系数为 1, 即 ^ ^=1; 当 k>APREF+l, 时， 第 k条支路的幅相校正系数为第 APREF对到第 k-1
…一― Jt-l 1 对相邻支路对的相对幅相校正系数的连乘积的倒数， 即^4 = Π _^。
' i=APREF r AP 也就是说， 当第 APREF条支路为参考支路时， 只有第 APREF条支路的 信号在幅相校正前后维持不变， 而其余所有支路的经过幅相校正之后的 信号将向参考支路靠拢。 在实际应用中， 当某样点落入多个相邻支路对的幅相校正窗口中 时， 可以先只计算相对幅相校正系数， 等到处理完所有的有样点落入多 个相邻支路对幅相校正窗口的情况之后， 才统一进行全体幅相校正系数 的计算。 比如： 当第 n号样点分别落入第 2对相邻支路对和第 3对相邻 支路对的幅相校正窗口中时， 首先根据第 2对相邻支路对的情况执行步 骤 2 ~步驟 3， 再根据第 3对相邻支路对的情况执行步骤 2〜步骤 3 , 最 后进行全体幅相校正系数的计算， 得到全体支路的幅相校正系数 。
在实际应用中， 接收机的各个支路之间可能具有时延误差， 在时延 误差超过一定限度之后， 需要在幅相校正前对数字基带信号进行时延校 正。
本发明实施例中， 时延校正的关键在于计算滤波器系数， 滤波器系 数的计算方法包括以下步骤：
步骤 1 : 相邻支路对对数字基带信号的样点进行筛选， 确定进行时 延校正计算的样点。
与幅相校正系数的计算不一样的是， 为了提高时延校正的精度， 一 般使用的样点是抽取之前的， 即样点间隔为 rs。
与幅相校正系数的计算一样， 在进行时延校正系数中， 并不是任何 一个样点都适合用来进行计算时延校正系数。 增益过大会使信号饱和， 导致失真， 过小则会受到噪声的影响， 也就是说， 增益过大或者过小都 会降低校正精度。 同样， 本发明为每一对相邻支路对设置了时延校正窗 口， 并规定只有落在时延校正窗口中的信号样点才被选中来进行该相邻 支路对的相对时延校正计算。 各相邻支路对需要对输入的信号样点进行 判别， 只有满足判别条件的信号样点才能用来进行时延校正计算。 该判 別条件可以用以下公式表示： -BCEk-WT>k≤Pk{n)<-BCEk
-BCEk-WT>k≤Pk{n-\)<-BCEk
-BCEk-W ≤Pk(n-L)<-BCEk
' - BCEk - WT,k - AGk≤ PM (") < -BCEk - AGk
- BCEk - WT,k - AGk≤ Pk+l (" - 1) < -BCEk - AGk
- BCEk - WT,k - AGk < Pk+1 (n-L)< -BCEk - AGk 其中， l≤k≤M-l， SC¾表示第 k对相邻支路对的包络回退值， _-BCEk _WT,k,-BCEk)表示第 k对相邻支路对的高增益支路的时延校正窗 口， [-BCEk -WT,k -AGk -BCEk - Δ<¾)表示第 k对相邻支路对的低增益支路 的时延校正窗口。 其中 ff^表示第 k对相邻支路对时延校正窗口宽度， 最小可以取得接近 0,最大可以取为无穷大。 当^，.取值为无穷大时， 相当于只要第 k支路不饱和就落在第 k对相邻支路对时延校正窗口内 了。 表示第 k条支路的第 n号样点的功率大小， ΡΑ.(«—1)表示第 k条 支路的第 n-1号样点的功率大小， 依次类推； 同理， 表示第 k+ 1 条支路的第 n号样点的功率大小， Ρ ("— 1)表示第 k + 1条支路的第 n - 1 号样点的功率大小， 并依次类推。 也就是说， 只有当第 k条支路上第 n 号样点至第 n-L号样点同时落入第 k对相邻支路对的高增益支路的时延 校正窗口中，而且第 k+ 1条支路上的第 n号样点至第 n-L号样点也同时 落入第 k对相邻支路对的低增益支路的时延校正窗口中时， 这 2L+2个 样点才用来作为计算第 k对相邻支路对之间的时延校正系数的样点。
在实际应用中， 时延校正窗口也可以用其它方法来设定， 只要能够 筛选到适合用来进行时延校正计算的样点即可。 比如： 时延校正窗口还 可以设置为： -BCEk -W7,k≤Pk(n)<-BCEk
- BCEk - W, - Gk≤ PM (n-L)< -BCEk - AGk
一 BCEk― WT,k― AG,≤ PM (n-L + l)< -BCEk― AGk
' - BCEk - W - AGk < Pk+1 (n) < -BCEk - AGk
- BCEk - WT>k - AGk≤ PM (n + l)< -BCEk - AGk
- BCEk - WT>k - AGk≤ P,+1 (n + L)< -BCEk - AGk 即： 只有当第 k条支路上第 n号样点落入第 k对相邻支路对的高增 益支路的时延校正窗口中， 第 k+1条支路上的第 n-L号样点至第 n+L 号样点落入第 k对相邻支路对的低增益支路的时延校正窗口中时， 这 2L+2个样点值才用来计算时延校正。当然，如果选择样点的方法不一样， 计算相邻支路对各样点之间相关功率也会有相应的差异， 但其原理是相 似的。
步骤 2: 根据相邻支路对的上次时延互相关值迭代和以及本次时延 互相关值计算相邻支路对本次时延互相关值迭代和。
由于步骤 1 筛选出来的共有 2L + 2个样点， 其中， 第 k条支路有 L+1个样点， 第 k+1条支路也有对应的 L+1样点。 所以， 如果将第 k条 支路上所述的 L+1样点分别与第 k+1条支路上所述的 L+1样点进行互相 关计算， 则可以得到 2L+1个不同的互相关值迭代和。
第 k对相邻支路对之间的 2L+ 1个互相关累计值的初 ^隹， 即上电 或复位之后的值， 都设置为 0, 即：
RTA°-L =… = ^ (0,-1) = RTTK(0,0) = RT>K(0,l) =… = RTIK(0,L) = 0
相邻支路对之间的 2L + 1个互相关值迭代和的计算可以由以下的迭 代公式表示为：
RT,k r,k , = (1 - cT,k (TC ))Pr,k r,k , d) + "T,k ( ,k RT,k (lr,k - 1> d)
d = -L-L + 1,...,-1,0,1,...Z— 1，L 其中， T表示时延校正， d表示时延差， 表示第 k对相邻支路对 互相关计算的次数， RT,k(!T,k,d)表示第 k对相邻支路对之间时延为 d的第 次或本次互相关值， ?r,fc(/r,f 1, 表示相邻支路对之间时延为 d 的第 lTi -l次或上次互相关值， pT,k {lTJc , d)表示相邻支路对的本次互相关值， 表示第 k对支路对 α滤波上次值权重， 简称为 系数。 系数的 含义与幅相校正系数计算中的 系数含义相似， 也可以采取类似的处理 方法， 此处不再赘述。 从以上的公式可以知道， 相邻支路对的上次互相 关值迭代和以及本次互相关值的加权平均值即为本次相邻支路对的互 相关值迭代和。
其中， 相邻支路对的本次互相关值可以表示为：
- ,...-2-l
' '
Figure imgf000044_0001
0X...,L-l,L
表示本次相邻时延校正系数计算使用的样点号。 当 - …,- 2,-1时， ("r(ri)+i *+10 (/rA))表示第 k条支路上的第 n+d号 样点与第 k+1条支路上第 n号样点之间的互相关值；当 d = 0,l,..., - 1 时， 表示第 k条支路上的第 n号样点与第 k+1条支路 上第 n - d号样点之间的互相关值。
在实际应用中， 相邻支路对的本次互相关值还可以表示为:
1
Γ , , , ,∑ ¾ ( ,k ) - i+d)xk*+1 (n(lTk ) - i), d = -Ζ,...-2-l
Pr,k QT， = 1 L-d
τ , Λ ,∑ ¾ (n{lTk ) - i)xk*+l (n(!TJc )-i-d),d = 0,1,..., L— 1,L 这里计算相邻支路对的本次互相关功率的方法与前一种方法基本 类似， 所不同的是： 后一种方法比前一种方法有更好的精度, 但是复杂 度更高。 因为前一种方法是将第 k条支路上的某一个样点与第 k+ 1条 支路上的某一个样点进行互相关计算， 而后一种方法是将第 k条支路上 的多个样点与第 k + 1 条支路上的多个样点之间进行互相关计算， 再将 计算出来的值进行平均， 作为相邻支路对之间的互相关值。 例如： 当 d=-L+2 且 L≥2 时 ， 本 次 互 相 关 值 可 以 表 示 为
-∑ ¾ «iT,k ) - i - L + 2)¾*+I (n(lTJc )-?) ,也就是说，第 k支路上的第 n-L+2号、 第 n-L+l号、 第 n-L号分别与第 k+1条支路上的第 n号、 第 n - 1号、 第 n - 2号样点分别进行互相关函数计算， 再将其平均值作为该相邻支 路对时延为 -L+2时的本次互相关值。
在实际应用中， 还可能存在其它计算相邻支路对之间互相关值的形 式， 只要可以表示相邻支路对之间互相关的关系即可， 此处不再——列 举。
步骤 3: 根据相邻支路对本次时延互相关值迭代和获得相邻支路对 之间的本次时延残差。
这里， 第 k对相邻支路对之间的时延残差是指第 k条支路上的信号 落后于第 k + 1条支路上的信号的时间。 第 k对相邻支路对之间的时延 残差 可以用下式计算：
Figure imgf000045_0001
其中， 表示第 k对相邻支路对第 次即本次时延为 d的互 相关值， Re{ }表示取实部运算。 例如： 某相邻支路对的高增益支路和低 增益支路各筛选出 4个样点， 对应为 4个时刻， 高 4氐增益支路的同号样 点对应相同时刻。 如果只有相邻支路对之间时延值为 2的相关函数计算 值存在， 其余各样点通过相关函数计算所得的值均为 0 , 则 也就是说， 高增益支路的第 3个样点和低增益支
Figure imgf000046_0001
路的第 1个样点最相关， 则可以认为高增益支路的第 3个样点和低增益 支路的第 1个样点在分为多支路前其实为同一个样点的可能性最大， 只 是由于相邻支路对之间存在时延差异， 使高增益支路的信号落后了低增 益支路的信号时延值为 2的时间。 实际上， rfc可以为整数， 但是大多数 情况下不是整数， 而且可能为正数、 负数或 0。
步骤 4: 根据相邻支路对之间的本次时延残差和上次相对时延校正 系数确定相邻支路之间的本次相对时延校正系数。
时延残差 r4其实就是相邻支路对之间本次相对时延校正系数， 但经 过多次时延校正计算，相邻支路对之间存在第 lTJc - 1次或上次相对时延校 正系数。 如果将相邻支路对之间的本次相对时延残差叠加到相邻支路对 之间的上次相对时延校正系数上， 就可以很容易得到相邻支路本次相对 时延校正系数。相邻支路本次相对时延校正系数 ( ）可以用下式计算： rT,k (ητ ) = rr,k (ητ _ 1) _ Ti
其中， 表示第 k对相邻支路对上次相对时延校正系数， ( )表示第 k对相邻支路对本次相对时延校正系数。上面的式子是说， 如果在将第 k支路延时 ( - 1)个样点的情况下其输出信号落后第 k+1 支路 个样点， 应该将其延时调整为 ( - 1) - ^个样点， 才能和第 k+1 支路信号在时间上对齐。 需要注意的是， 这里 和本发明中其它公式中 ητ (1Τ )含义不同， nT表示相对时延校正系数的更新次数， 而 nT T l )表示 与 对应的样点号。
根据步骤 4中的分析可以知道， 如果只考虑第 k支路和第 k+1支路 间的时延关系， 将第 k支路信号再延时 个样点而第 k+1支路信号 不动， 就可以和 k+1支路信号对齐了。 在实际应用中， 可以为整 数， 但是大多数情况下不是整数， 而且可能为正数、 负数或 0。
步骤 5: 根据相邻支路对之间的本次相对时延校正系数获得全体时 延校正系数。
当某相邻支路对计算出新的相对时延校正系数之后，为了将 M条支 路的信号在时间上对齐， 需要事先设定一条参考支路和时延目标值 τ 并以参考支路为准， 重新计算 M条支路的时延校正系数， 即全 体时延校正系数。 这里， 时延目标值是指用于时延校正的低通滤波器的 群时延要求。
假设将第 TREF条支路作为参考支路， 将参考支路的群时延设定为 τ ， 则参考支路的时延校正系数始终保持为 0, 而其它的支路则向参 考支路靠拢。 M路时延校正系数可以表示为：
TREF - I
cT k = J rT ， k = l TREF— l
= 0
1
cT k = - rT ， k = TR£F + i
' i=TREF ' 需要注意的是， 这里的 k并不表示第 k对相邻支路对， 而是表示第 k条支路。 当 : = 1 ~ TREF - 1时， 第 k条支路的时延校正系数就是从自身 支路所在的相邻支路对到参考支路所在的相邻支路对相对校正系数之 和。 比如： 接收机共 5条支路， 第 3条支路为参考支路， 第 1条和第 2 条支路为第 1对相邻支路对， 并依此类推。 那么， 如果第 1对相邻支路 对的相对时延校正系数为 0.1 , 第 2对相邻支路对的相对时延校正系数 为 0.2， 则第 1支路相对于参考支路的时延校正系数为 0.3， 第 2条支路 相对于参考支路的时延校正系数为 0.2。 当 & = r?EE + l ~ M时， 其方法与 此类似， 此处不再赘述。
步骤 6:根据全体时延校正系数和时延目标值获得全体滤波器系数。 从步驟 5可以知道， 参考支路的低通滤波器群时延设置为 ， 为 了能够将 M条支路的信号在时间上对齐，则应该使第 k支路的滤波器系 数对应的群时延为 r„。^ + Cr,A , 其中， k=l〜M, 然后再将滤波器系数配置 给 M个低通滤波器。
在实际应用中， 如果相邻支路对之间的时延残差非常小， 或者说未 超过事先设定的时延门限值， 则可以不计算时延校正系数。 即使需要计 算时延校正系数， 虽然相邻支路对的信号并没有在时间上完全对齐， 但 只要不影响系统性能，'可以定时或不定时地计算时延校正系数， 而不需 要频繁地进行时延校正。
当接收机输入信号经过幅相校正之后， 需要根据切换策略选择一路 输出信号。 在实际应用中， M路选 1路控制模块根据切换策略来选择输 出数字基带信号支路的方法很多， 比如可以采用以下的方法实现：
步驟 XI： M路选 1路控制模块根据校正前数字基带信号确定 1路 增益最大但未饱和的支路， 将其作为候补被选中支路。
如果存在包络回退， M路选 1路控制模块判断支路是否已经饱和的 条件并不是判断复包络功率是否达到 0dBFS， 而是判断是否达到 -5CE,dBFS, 如果达到， 则判断为已经饱和， 否则， 就判断为未饱和。
步骤 X2: M路选 1路控制模块判断前一次样点是否由候补被选中 支路的相邻低增益支路输出， 而且本次样点在候补被选中支路中的功率 不低于迟滞低门限， 如果是， 则将候补被选中支路的相邻低增益支路作 为输出本次样点的被选中支路； 否则， 将候补被选中支路作为输出本次 样点的被选中支路。 在相邻支路的切换中， 如果只设置- C¾ dBFS—个门限， 由于候 补被选中支路信号可能在 dBFS附近发生小幅度波动， 容易造成 在两个相邻支路之间频繁切换， 可能导致不连续， 影响解调性能。所以， 本发明中可以设置高低双门限， 即切换迟滞。也就是说，将- BCEk dBFS 设置为迟滞高门限， 将- (SC¾ + H}¾^) dBFS设置为迟滞低门限。 在已 经确定第 k条支路为不饱和的最大输出支路的时候， 如果第 k+1条支路 为输出上次样点的支路， 则当第 k 条支本次样点功率不低于 - (BCEk + HYSABk) dBFS时， 应该继续将第 k+1条支路作为本次样点的输 出支路， 否则从第 k + 1条支路切换到第 k条支路。 方法实施例一
图 11显示了本实施例中接收机的基本结构示意图。 参见图 11 , 本 实施例采用离线配置幅相校正系数的方法, 即在接收机开始工作之前， 先计算出 M条支路的幅相校正系数初始值，再将其配置给幅相校正模块 1104, 并且在接收机工作期间不再更改。 这包括两种情况， 一种是在将 接收机上电之前就将校正系数配置在接收机中， 这种情况下配置的系数 是掉电或者复位也不失去信息的； 另一种是在接收机每次复位之后一次 性的写到接收机中， 不掉电或者不复位就不失去信息， 但是掉电或者复 位之后信息会失去， 所有每次上电或者复位之后都要做一次性写入的操 作。
图 18 显示了本实施例中计算幅相校正初始值方法的流程图。 如图 18所示， 计算幅相校正初始值方法包括以下步骤：
步骤 1801 : 将各相邻支路对中高增益支路的上次功率值迭代和、 低 增益支路的上次功率值迭代和、 上次互相关值迭代和均设置为 0。
在实际应用中， 还可以先为各相邻支路对设置相对幅相校正系数初 始值， 再根据相对幅相校正系数初值计算得到全体幅相校正系数， 并配 置给幅相校正模块。然后以此为基础，开始幅相校正系数的初始化过程， 即开始计算真的幅相校正系数初始值。
步骤 1802: 各相邻支路对根据各自的幅相校正窗口对通过多支路校 正前处理模块处理后获得的样点进行筛选， 确定用来进行本次相对幅相 校正计算的样点。
步骤 1803:各相邻支路对根据自身高增益支路的上次功率值迭代和 以及落入自身幅相校正窗口的本次样点功率值计算自身高增益支路的 本次功率值迭代和， 根据自身低增益支路的上次功率值迭代和以及本次 样点功率值计算自身低增益支路的本次功率值迭代和， 才艮据相邻支路对 的上次互相关值迭代和以及本次样点互相关值计算相邻支路对的本次 互相关值的迭代和。
本实施例中， 步骤 1802和步骤 1803与本发明中所述的幅相校正系 数计算方法中的步骤 1和步骤 2相似， 此处不再赘述。
步骤 1804: 各相邻支路对判断样点落入自身幅相校正窗口的次数是 否达到预设值， 如果达到， 则执行步骤 1805; 否则， 返回步骤 1802。
在幅相校正系数计算方法中 , 利用 来记录第 k对相邻支路对有 样点落入的次数。 如果要得到理想的全体幅相校正系数， 就需要每一对 相邻支路对都有相当多的样点落入幅相校正窗口。 至于每一对相邻支路 对中多少次有样点落入幅相校正窗口， 则需要根据实际的情况预先设 置， 即需要确定一个样点落入幅相校正窗口的次数的预设值。 当所有相 邻支路对的样点落入幅相校正窗口次数达到预设值以后， 才继续进行步 骤 1805; 否则， 各相邻支路对继续等待合适的样点。
这里， 需要注意的是， 各相邻支路对的^、 Ρ, ΛΙ^) ^ 和 ^^(Zw)在上电或者复位之后的初始值为 0, 但每次有某个样点落入某 相邻支路对的幅相校正窗口中， ^^就增加 1，相应地 ^w(^)、 ρυ 和 AP,,, )就将被更新， 而且作为上次功率值迭代和来计算下一次有样 点落入时的新的 /^(/^)、 ^(/_^)和 值。 也就是说， 在幅相 校正系数初始值的过程中， Pk,H( k P (/^)和 , 的值将不会 清。。
实际上， 除非下一次复位' P H AP,) ^ (^)和^^ 4)的值以及 I k的值都不会被清零， 在工作期开始后会将初始化得到的这些值作为 初值。
步骤 1805: 各相邻支路对根据自身高增益支路的本次功率值迭代 和、 低增益支路的本次功率值迭代和， 以及相邻支路对的本次相关值迭 代和来计算自身相邻支路对的相对幅相校正系数。
在实际应用中， 各个相邻支路对可以同时根据信号样点计算相对幅 相校正系数， 即输入信号并不针对某一个相邻支路对， 而是在各个支路 的动态范围之间变化， 而各个相邻支路对同时进行步骤 1802〜步骤 1805, 直到完成所有的相邻支路对的相对幅相校正系数计算； 各个相邻 支路对也可以分时计算相对幅相校正系数， 也就是说， 将输入信号的功 率控制到刚好落入某一个相邻支路对的幅相校正窗口中， 等该相邻支路 对的相对幅相校正系数计算完成之后， 再将输入信号的功率控制到刚好 落入另一个相邻支路对的幅相校正窗口中， 计算另外一个相邻支路对的 相对幅相校正系数， 并重复此过程， 直到完成所有的相邻支路对的相对 幅相校正系数计算。
步骤 1806: 根据所有相邻支路对之间的相对幅相校正系数获得 M 个幅相校正系数。 本实施例中， 步驟 1805和步骤 1806与幅相校正系数计算方法中的 步骤 3和步裸 4相同， 此处不再赘述。
步骤 1807: 将 M个幅相校正系数配置给幅相校正模块。
当将幅相校正系数初始值配置给幅相校正模块以后， 接收机就可以 从天线接收无线信号了， 并且在之后都不更改。 这里， 所述的将全体幅 相校正系数配置给幅相校正模块其实就是将全体幅相校正系数写入幅 相校正模块内的 M个幅相校正系数对应的寄存器中。
本实施例中假设使用离线配置方式， 如果接收机有校正信号注入模 块， 那么用于离线配置幅相校正系数初始值的输入信号就可以是校正信 号， 或者可以直接从天线输入端注入适合于用作校正的信号； 如果接收 机没有校正信号注入模块， 那么用于离线配置幅相校正系数初始值的输 入信号可以是直接从天线输入端注入适合于用作校正的信号。
当然， 在实际应用中， 如果采用在线配置幅相校正系数初始值， 则 输入信号就可以是接收机输入信号或者校正信号。
本实施例中， 当为接收机配置了幅相校正系数初值之后， 就可以开 始接收无线信号， 并将其处理为 bit流输出。
图 19显示了本实施例实现接收无线信号方法的流程图。 如图 19所 示， 本实施例实现接收无线信号的方法包括以下步骤：
步骤 1901: _含模拟 I&Q解调功能的上游模拟接收通道模块将接收 机输入信号进行放大和模拟 I&Q解调等处理，获得模拟基带信号， 并输 出给 M个双通道固定增益支路模块。
在实际应用中，含模拟 I&Q解调功能的上游模拟接收通道模块还可 能对接收机输入信号进行混频和滤波等处理。
步骤 1902: M个双通道固定增益支路模块将输入的模拟基带信号进 行梯级增益处理， 并输出给 M个双通道模拟到数字转换器。 步驟 1903: M个双通道模拟到数字转换器将 M路模拟基带信号进 行釆样处理， 获得 M路数字基带信号并分别输出给 M个幅相校正乘法 器和 M路选 1路控制模块。
步骤 1904: M个幅相校正乘法器根据事先保存的幅相校正系数， 将 输入的 M路数字基带信号进行幅相校正处理， 并输出给 M路选 1路模 块； M路选 1路控制模块根据切换策略选择输出当前样点的支路， 并通 过切换控制信号将支路号通知给 M路选 1路模块。
本步骤中， 输入给 M个幅相校正乘法器的 M个幅相校正系数就是 本实施例中事先通过离线配置的方式配置给幅相校正模块 1104的 M个 幅相校正系数初始值。
步骤 1905: M路选 1路模块根据切换控制信号从经过幅相校正后的 M路数字基带信号中选择一路输出给数字接收通道后段。
步骤 1906: 数字接收通道后段对输入的数字基带信号进行进一步的 数字处理， 并输出 bit流。 方法实施例二
图 12显示了本实施例中接收机的基本结构示意图。 参见图 12， 本 实施例采用在线配置幅相校正系数的方法， 即接收机上电复位时， 幅相 校正系数计算模块计算出 M条支路的幅相校正系数初始值，将其配置给 幅相校正模块 1205。 之后， 幅相校正系数计算模块继续计算 M条支路 新的幅相校正系数， 并将新的幅相校正系数重新配置给幅相校正模块 1205。
至于 M条支路的幅相校正系数初始值的计算和配置过程与方法实 施例一中的方法相似， 此处不再赘述。
图 20显示了本实施例实现接收无线信号方法的流程图。 如图 20所 示， 当幅相校正模块配置了幅相校正系数初始值之后， 本实施例实现接 收无线信号方法包括以下步骤：
步骤 2001 : 含模拟 I&Q解调功能的固定增益支路模块将接收机输 入信号进行梯级增益处理和模拟 I&Q解调处理， 获得 M路模拟基带信 号， 并输出给 M个双通道模拟到数字转换器。
步骤 2002: M个双通道模拟到数字转换器将模拟基带信号进行采样 处理， 获得并输出数字基带信号给 M个抽取滤波器模块。
步棟 2003: M个抽取滤波器模块将输入的数字基带信号进行低通滤 波和抽取处理， 并输出给幅相校正前馈环时延补偿模块、 幅相校正系数 计算模块和 M路选 1路控制模块。
步骤 2004: M路选 1路控制模块根据切换策略确定输出本次样点的 支路号， 产生携带有该支路号信息的切换控制信号和表示是否发生切换 的切换标志信号 , 并将切换控制信号输出给切换前馈环时延补偿模块， 将切换标志信号输出给幅相校正系数计算模块。
本步驟中， M路选 1路控制模块根据切换策略可以知道输出本次样 点支路号和输出上次样点的支路号是否相同， 并由此产生切换控制信号 和切换标志信号。如果 M路选 1路控制模块发现应该输出 n号样点的支 路与输出 n-1号样点的支路相同， 则切换控制信号中的支路号仍然与输 出 n-1号样点的支路号相同， 切换标志信号指示当前样点不需要切换； 否则， 切换控制信号中的支路号将为新的支路号， 切换标志信号指示当 前样点需要切换。 比如： 可以将切换标志信号设计为一个 lbit的信号。 如果当前样点需要切换， 则切换标志信号为 1; 否则， 切换标志信号为 0。
步骤 2005: 幅相校正系数计算模块进行校正信号的筛选和计算， 并 根据切换标志信号和幅相校正系数最新值判断是否将计算出来的幅相 校正系数最新值配置给幅相校正模块， 如果是， 则将幅相校正系数最新 值配置给幅相校正模块； 否则， 不作配置。
幅相校正系数计算模块计算新的幅相校正系数的方法与计算幅相 校正系数初始值的方法基本相似， 只是每次有合适的样点落入校正窗口 时都直接根据已经存在的上次功率值迭代和以及本次样点功率值计算 新的幅相校正系数。 计算幅相校正系数最新值方法的步驟为：
Yl、 幅相校正系数计算模块通过各相邻支路对的幅相校正窗口， 对 输入样点进行筛选， 确定用来进行本次相对幅相校正计算的样点;
Υ2、各相邻支路对根据自身高增益支路的上次功率值迭代和以及落 入自身幅相校正窗口的本次样点功率计算自身高增益支路的本次功率 值迭代和， 根据自身低增益支路的上次功率值迭代和以及本次样点功率 值计算自身低增益支路的本次功率值迭代和， 根据相邻支路对的上次互 相关值迭代和以及本次样点互相关值计算本次相邻支路对的互相关值 迭代和；
Υ3、 各相邻支路对根据自身高增益支路的本次功率值迭代和、低增 益支路的本次功率值迭代和 , 以及相邻支路对的本次相关值迭代和来计 算自身相邻支路对的相对幅相校正系数;
Υ4、幅相校正系数计算模块根据所有相邻支路对的相对幅相校正系 数获得全体幅相校 iE系数最新值。 ― _ . 在实际应用中， 输入幅相校正系数计算模块的信号可以是未经过幅 相校正的 M路数字基带信号， 也可以是已经经过幅相校正的 M路数字 基带信号。 不管是经过幅相校正前的信号， 还是幅相校正后的信号， 幅 相校正系数计算的方法都基本相似 , 其区别在于： 如果是幅相校正后信 号的样点， 则需要在计算之前去除原来幅相校正系数的影响， 即先将经 过幅相校正的 M路数字基带信号除以原来的幅相校正系数，恢复为经过 幅相校正之前的 M路数字基带信号， 然后再进行幅相校正系数计算； 或 者直接用已经经过幅相校正的 M路数字基带信号的样点进行计算，最后 将计算出来的幅相校正系数乘以原来的幅相校正系数， 获得真正的幅相 校正系数的最新值。
本步骤中， 所述幅相校正系数计算模块判断是否需要将幅相校正系 数最新值配置给幅相校正模块的方法为： 当幅相校正系数计算模块接收 到 M路选 1路控制模块输入的当前样点的切换标志信号时，幅相校正系 数计算模块根据切换标志信号判断是否当前样点是否有切换， 如果有切 换， 幅相校正系数计算模块再判断在上一次给幅相校正模块配置过幅相 校正系数后是否计算过新的幅相校正系数， 如果有， 则将幅相校正系数 最新值配置给幅相校正模块。 相反地， 如果切换标志信号指示当前样点 不需要切换， 或者幅相校正系数计算模块在上一次给幅相校正模块配置 过幅相校正系数后还没有计算过新的幅相校正系数 , 则幅相校正系数就 不需要更新。
在实际应用中，如果 M路选 1路控制模块向幅相校正系数计算模块 发送的切换标志信号指示当前样点需要切换， 那么， 不管是否计算出新 的幅相校正系数， 幅相校正系数计算模块也可以向幅相校正模块配置幅 相校正系数。 该幅相校正系数有可能是在上次配置给幅相校正模块之后 新计算出来的幅相系数最新值， 也可能就是上次的幅相校正系数， -即只 是将原来的系数值重新配置了一次， 并不会改变幅相校正模块幅相校正 系数的值。
另外， 在实际应用中， M路选 1路控制模块也可以定时将幅相校正 系数新值配置给 M个幅相校正乘法器，而不管是否需要从一条支路切换 到另外一条支路。
步骤 2006:幅相校正前馈环时延补偿模块将经过时延补偿处理的 M 路数字基带信号输出给幅相校正乘法器。
本实施例中， 幅相校正前馈环时延补偿模块、 幅相校正系数计算模 块、 M路选 1路控制模块其实是同时对输入的数字基带信号进行处理。 比如： 当前处理的样点为 n号样点， 幅相校正系数计算模块根据 n号样 点计算幅相校正系数， M路选 1路控制模块根据切换策略确定输出当前 样点的支路， 并产生切换控制信号和切换标志信号。 如果需要从一条支 路切换到另夕 1、一个支路， M路选 1路控制模块则向幅相校正系数计算模 块发送的切换标志信号会指示当前样点需要切换， 而且幅相校正系数计 算模块在上一次给幅相校正模块配置过幅相校正系数后计算过新的幅 相校正系数， 则幅相校正系数计算模块立即将计算出来的新的幅相校正 系数配置给幅相校正模块。 与此同时， n号样点在经过幅相校正前馈环 时延补偿模块后，在幅相校正系数配置的同时输出给 M个幅相校正乘法 器， M个幅相校正乘法器就根据新配置的幅相校正系数来对 n号样点进 行幅度和相位校正， 再输出给 M路选 1路模块。
步骤 2007: M个幅相校正乘法器根据幅相校正系数最新值对输入的 M路数字基带信号进行幅度和相位校正， 再输出给 M路选 1路模块。
本实施例中， M个幅相校正乘法器将才艮据最新配置给幅相校正模块 中的幅相校正系数对 M路数字基带信号进行校正，也就是说，在第一次 在线计算出幅相校正系数新值之前， M个幅相校正乘法器是根据幅相校 正初始值进行校正的。 之后， 都是根据步骤 2005 配置给幅相校正模块 的幅相校正系数最新值来进行校正的。
步驟 2008: M路选 1路模块根据通过切换前馈环时延补偿模块进行 时延补偿的切换控制信号，从输入的经过校正的 M路数字基带信号中选 择 1路输出给数字接收通道后段。
步骤 2009: 数字接收通道后段将接收到的数字基带信号进行进一步 的数字处理， 输出 bit流。 方法实施例三
图 13显示了本实施例中接收机的基本结构示意图。 参见图 13 , 本 实施中的接收机与方法实施例二中所应用的接收机基本相似， 其区别在 于： 本实施例的各支路具有时延误差， 需要利用时延校正模块对信号进 行时延校正。 另夕卜，本实施例中在处理模拟信号中不含有模拟 I&Q解调 功能， 而是由数字 I&Q解调部分来进行 I&Q解调处理。 本实施例中的 时延校正是利用了数字 I&Q解调部分中的 M个低通滤波器模快来实现， 即将数字 I&Q解调'部分、时延校正系数计算模块和滤波器系数计算模块 构成了时延校正模块。 当然，在实际应用也可以不利用数字 I&Q解调部 分中的 M个低通滤波器模快来实现时延校正， 而是另外增加 M个低通 滤波器模快来实现时延校正。
本实施例中， 当接收机需要进行初始化时， 需要先将校正信号注入 模块中开关打到触点 2, 利用校正信号注入模块产生的校正信号进行幅 相校正系数计算和滤波器系数计算， 并将计算出来的幅相校正系数初始 值和滤波器系数初始值分别配置给幅相校正模块和 M个低通滤波器，然 后再将校正信号注入模块中开关打到触点 1，准备从天线接收输入信号。
本实施例中幅相校正系数初始值的计算方法与方法实施例一中的幅 相校正系数初始值的计算方法相同， 此处不再赘述。
图 21显示了本实施例进行滤波器系数初始值计算方法的流程图。如 图 21所示， 本实施例进行滤波器系数初始值计算方法包括以下步驟： 步骤 2101: 根据各相邻支路对事先设置的相对时延校正系数初值， 获得全体时延校正系数， 再根据全体时延校正系数获得全体滤波器系 数， 并分别配置给 M个低通滤波器。 步骤 2102: 将各相邻支路对的所有上次互相关值的迭代和和上次相 对时延校正系数设置为 0。
步骤 2103: 各相邻支路对通过各自的时延校正窗口， 对输入信号经 过多支路校正前处理模块处理得到的样点进行筛选， 确定用来进行本次 时延校正计算的样点。
步骤 2104: 各相邻支路对根据各自的上次时延互相关位迭代和以及 本次时延互相关值计算本次时延互相关值迭代和。
步骤 2105: 各相邻支路对根据各自的本次时延互相关值迭代和分别 获得各相邻支路对的本次时延残差， 并根据自身本次时延残差和上次相 对时延校正系数确定各相邻支路对的本次相对时延校正系数。
步骤 2106: 各相邻支路对判断样点落入时延校正窗口的次数是否达 到预设值， 如果达到， 则执行步骤 2107; 否则， 返回步骤 2103。
与计算幅相校正系数初值时一样， 只有大量样点落入时延校正窗口 后计算出来的时延校正系数才比较可靠。 所以， 这里预先设置了落入校 正窗口的次数， 至于该预设值的大小则根据实际情况确定。
本实施例中， 所有的相邻支路对可以同时根据输入信号进行相对时 延校正系数的计算， 即同时执行步骤 2102〜步骤 2106， 只有所有的相 邻支路对都有足够的样点落入校正窗口中， 计算出所有相邻支路对的相 对时延校正系数以后， 才开始执行步骤 2107。 在实际应用中， 也可以先 将校正信号的功率控制在某一个相邻支路对的时延校正窗口中， 集中对 该相邻支路对进行相对时延校正系数的计算， 再依次计算其它的相邻支 路对， 然后才开始执行步骤 2107。
步骤 2107: 各个相邻支路根据本次相对时延校正系数获得全体时延 校正系数， 并根据全体时延校正系数和事先设置的时延目标值获得滤波 器系数初始值， 并分别配置给 M个低通滤波器。 与计算幅相校正系数初始值一样， 在实际应用中， 计算滤波器系数 初始值的输入信号可以是离线配置滤波器系数初始值的输入信号， 还可 以是接收机输入信号， 其应用环境与方法实施一中所述的计算幅相校正 系数初始值相同， 此处不再赘述。
本实施例中， 当接收机配置了幅相校正系数初始值和滤波器系数初 始值之后， 接收机就可以开始工作， 接收无线信号， 输出 bit流。
图 22显示了本实施例实现接收无线信号方法的流程图。 如图 22所 示， 本实施例实现接收无线信号的方法包括以下步骤：
步骤 2201 : 校正信号注入模块将接收机输入信号传输给 M个单通 道固定增益支路模块， M个单通道固定增益支路模块将接收机输入信号 进行梯级增益处理， 并输出给 M个单通道模拟到数字转换器。
步骤 2202: M个单通道模拟到数字转换器和数字下变频部分将信号 分別进行釆样处理和下变频处理， 获得数字 I&Q信号， 并输出给 M个 低通滤波器模块。
步骤 2203: M个低通滤波器模块将数字 I&Q信号进行低通滤波， 并根据滤波器系数进行时延校正，获得数字基带信号，再输出给 M个抽 取模块和时延校正系数计算模块； 时延校正系数计算模块根据输入的数 字基带信号计算时延校正系数， 并将新的时延校正系数发送给滤波器系 数计算模块计算滤波器系数新值，— 并配置给 M个低通滤波器模块。 . 本步驟 2203的目的是计算新的滤波器系数,其方法与计算滤波器系 数初始值的方法相似， 其区别在于， 计算滤波器系数新值时， 将直接在 滤波器系数初始值基础上开始进行， 而且也无需判断样点落入时延校正 窗口的次数是否达到预设值。 计算滤波器系数新值的方法包括以下步 骤：
Ή1、 时延校正系数计算模块通过各相邻支路对的时延校正窗口， 对 输入的样点进行筛选， 确定用来进行本次时延校正计算的本次样点；
H2、时延校正系数计算模块根据各相邻支路对的上次时延互相关值 迭代和以及本次时延互相关值计算各相邻支路对的本次时延互相关值 迭代和；
H3、时延校正系数计算模块根据各相邻支路对的互相关值迭代和分 别获得各相邻支路对的本次时延残差， 并根据本次时延残差和上次相对 时延校正系数确定各相邻支路对的本次相对时延校正系数；
H4、时延校正系数计算模块根据各相邻支路对本次相对时延校正系 数获得全体时延校正系数， 并将全体时延校正系数发送给滤波器系数计 算模块；
H5、滤波器系数计算模块根据全体时延校正系数和事先设置的时延 目标值获得滤波器系数最新值。
步骤 2204〜步驟 2211与方法实施例二中的步骤 2003 ~步骤 2009 相似， 只是步骤 2205 不再进行滤波处理， 只进行抽取处理即可， 此处 不再赘述。
在实际应用中，如果接收机的结构如图 16所示，其接收无线信号的 方法与本实施例相似， 其区别仅仅在于接收机输入信号先在模拟信号处 理阶段中进行了 I&Q解调， 再进行数字采样， 得到数字基带信号， 然后 利用专门的时延校正模块进行时延校正。 由于其方法与本实施例类似， - 此处不再赘述。
另夕卜， 如果接收机中包括直流与 I&Q平衡校正模块， 则需要将从多 支路校正前处理模块中输出的数字基带信号先进行直流与 I&Q平衡校 正处理， 去除由电路引入的误差， 即去除电路引入的 I路和 Q路信号中 的直流误差， 以及 I路 &Q路之间的幅度和相位的误差。 然后， 再进行 时延校正和幅相校正等处理过程。 应用本发明实施例方案， 可以在各个支路上各自将信号形式为模拟 带通信号的接收机输入信号先转换为数字基带信号， 再经过幅相校正， 将各支路间的数字基带信号在幅度和相位上对齐。 如果接收机的支路有 不可忽略的时延误差 , 则需要在幅相校正之前将数字基带信号先进行时 延校正， 使各支路的信号样点在时间对齐。 之后， 再进行幅相校正， 将 数字基带信号在幅度和相位上对齐。这样，本发明就可以实现逐点切换， 达到提高解调性能、 增加非同时动态范围的目的。
在实际应用中， 多支路校正前处理中如何获取数字基带信号； 幅相 校正系数初始值是采用离线配置方法， 还是采用在线配置方法； 是否需 要对信号进行抽取； 是否需要在接收机工作过程中进行时延补偿； 是否 需要对幅相校正前的信号进行时延校正； 时延校正系数是采用离线配置 方法， 还是采用在线配置方法； 是否进行直流与 I&Q平衡校正处理； 是 否利用校正信号进行时延和幅相的校正等都与实际情况相关， 可以产生 不同的组合， 这里就不再——列举这些情况的组合所能组成接受无线信 号的方法。
综上所述， 以上仅为本发明的较佳实施例而已， 并非用于限定本发 明的保护范围。 凡在本发明的精神和原则之内， 所作的任何修改、 等同 替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权利要求书
1、一种接收机，至少包括多支路校正前处理模块和数字接收通道后 段， 其特征在于， 该接收机进一步包括：
多支路校正与切换模块， 用于将由多支路校正前处理模块输入的 M 路数字基带信号进行幅度和相位校正， 并根据切换策略选择一路输出给 数字接收通道后段。
2、 根据权利要求 1 所述的接收机， 其特征在于， 所述多支路校正 与切换模块包括：
幅相校正模块，用于根据由多支路校正前处理模块输入的 M路数字 基带信号和自身中的幅相校正系数来获得校正后的 M路数字基带信号， 并输出给 M路选 1路模块；
M路选 1路控制模块，用于根据由多支路校正前处理模块输入的 M 路数字基带信号和切换策略产生携带有支路号信息的切换控制信号， 并 将切换控制信号输出给 M路选 1路模块;
M路选 1路模块， 用于 居由 M路选 1路控制模块输入的切换控 制信号，从幅相校正模块输入的 M路数字基带信号中选择一路， 并输出 给数字接收通道后段。
3、 根据权利要求 2所述的接收机， 其特征在于，·所述多支路校正 与切换模块进一步包括：
幅相校正系数计算模块， 用于将由多支路校正前处理模块或幅相校 正模块输入的 M路数字基带信号进行幅相校正系数的计算， 并根据 M 路选 1路控制模块输入的切换标志信号将计算出来的幅相校正系数输出 给幅相校正模块；
所述 M路选 1路控制模块进一步用于：根据由多支路校正前处理模 块输入的 M路数字基带信号和切换策略产生切换标志信号，并输出给幅 相校正系数计算模块。
4、 根据权利要求 3 所述的接收机， 其特征在于， 所述多支路校正 与切换模块进一步包括：
M个幅相校正前馈环时延补偿模块， 用于将由多支路校正前处理 模块输入的 M路数字基带信号进行时延补偿， 并输出给幅相校正模块； 或者， 用于将由幅相校正系数计算模块输入的幅相校正系数进行时 延补偿， 并输出给幅相校正模块。
5、 根据权利要求 2所述的接收机， 其特征在于， 所述多支路校正 与切换模块进一步包括：
切换前馈环时延补偿模块，用于将由 M路选 1路控制模块输入的切 换控制信号进行时延补偿， 并输出给 M路选 1路模块;
或者，用于将由多支路校正前处理模块输入的 M路数字基带信号进 行时延补偿， 并输出给幅相校正模块；
或者，用于将由幅相校正模块输入的经过幅相校正的 M路数字基带 信号进行时延补偿， 并输出给 M路选 1路模块。
6、 根据权利要求 2所述的接收机， 其特征在于， 所述接收机进一 步包括：
抽取滤波器，用于将由多支路校正.前处理模块输入的 M路数字基带 信号进行低通滤波和抽取处理， 并输出给幅相校正模块。
7、 根据权利要求 1 所述的接收机， 其特征在于， 所述多支路校正 前处理模块至少包括：
含模拟 I&Q解调功能的上游模拟接收通道模块，用于将接收机输入 信号进行含模拟 I&Q解调功能的上游模拟接收处理， 获得模拟基带信 号， 再输出给 M个双通道固定增益支路模块； M个双通道固定增益支路模块， 用于将由含模拟 I&Q解调功能的 上游模拟接收通道模块输入的 M路模拟基带信号进行梯级增益处理，并 输出给 M个双通道模拟到数字转换器；
M个双通道模拟到数字转换器， 用于将由 M个汉通道固定增益支 路模块输入的模拟基带信号进行釆样处理， 转换为数字基带信号， 并输 出给多支路校正与切换模块。
8、 根据权利要求 1 所述的接收机， 其特征在于， 所述多支路校正 前处理模块至少包括：
M个含模拟 I&Q解调功能的固定增益支路模块， 用于将接收机输 入信号进行梯级增益处理和模拟 I&Q解调处理，获得模拟基带信号， 并 输出给 M个双通道模拟到数字转换器；
M个双通道模拟到数字转换器， 用于将从 M个含模拟 I&Q解调功 能的固定增益支路模块输入的模拟基带信号进行采样处理， 转换为数字 基带信号， 并输出给多支路校正与切换模块。
9、 根据权利要求 8 所述的接收机， 其特征在于， 所述多支路校正 前处理模块进一步包括：
不含模拟 I&Q解调功能的上游模拟接收通道模块，用于将接收机输 入信号进行不含模拟 I&Q解调功能的上游模拟接收处理， 并输出给 M 个含模拟 I&Q解调功能的固定增益支路模块。 _
10、 根据权利要求 7至 9任一项所述的接收机， 其特征在于， 该接 收机进一步包括：
时延校正模块，用于根据由 M个双通道模拟到数字转换器输入的 M 路数字基带信号进行时延校正处理， 并输出给多支路校正与切换模块。
11、 根据权利要求 10 所述的接收机， 其特征在于， 所述时延校正 模块包括： M个低通滤波器模块， 用于根据由滤波器系数计算模块输入的滤波 器系数，将由 M个双通道模拟到数字转换器输入的数字基 '带信号进行低 通滤波和时延处理， 并输出给多支路校正与切换模块和时延校正系数计 算模块；
时延校正系数计算模块，用于根据由 M个低通滤波器模块输入的数 字基带信号计算时延校正系数， 并将时延校正系数输出给滤波器系数计 算模块；
滤波器系数计算模块， 根据由时延校正系数计算模块输入的时延校 正系数得到滤波器系数， 并输出给 M个低通滤波器模块。
12、 根据权利要求 11 所述的接收机， 其特征在于， 所述时延校正 模块进一步包括：
M个直流与 I&Q平衡校正模块， 用于将由 M个双通道模拟到数字 转换器输入的数字基带信号进行直流与 I&9平衡校正处理，并输出给 M 个低通滤波器模块。
13、 根据权利要求 11 所述的接收机， 其特征在于， 该接收机进一 步包括：
M个抽取模块， 用于将由 M个低通滤波器模块输入的 M路数字基 带信号进行抽取处理， 并输出给多支路校正与切换模块。
14、 根据权利要求 1所述的接收机， 其特征在于 -, .所述多支路校正 前处理模块至少包括：
M个单通道固定增益支路模块， 用于将接收机输入信号进行梯级增 益处理， 并输出给 M个单通道模拟到数字转换器；
M个单通道模拟到数字转换器， 用于将由 M个单通道固定增益支 路模块输入的模拟带通信号进行釆样处理， 转换为数字带通信号， 并输 出给数字 I&Q解调部分； 数字 I&Q解调部分， 用于将由 M个单通道模拟到数字转换器输入 的数字带通信号进行数字 I&Q解调处理和低通滤波处理，获得数字基带 信号， 并输出给多支路校正与切换模块。
15、 根据权利要求 14所述的接收机， 其特征在于， 所述多支路校 正前处理模块进一步包括：
不含模拟 I&Q解调功能的上游模拟接收通道模块，用于将接收机输 入信号进行不含模拟 I&Q解调功能的上游模拟接收处理， 并输出给 M 个单通道固定增益支路模块。
16、 根据权利要求 14或 15所述的接收机， 其特征在于， 该接收机 进一步包括：
M个抽取模块， 用于将由数字 I&Q解调部分输入的 M路数字基带 信号进行抽取处理， 并输出给多支路校正与切换模块。
17、 根据权利要求 16所述的接收机， 其特征在于， 所述数字 I&Q 解调部分包括：
数字下变频模块，用于将由 M个单通道模拟到数字转换器输入的数 字带通信号进行下变频处理， 获得数字 I&Q信号， 并输出给 M个低通 滤波器模块；
M 个低通滤波器模块， 用于将由数字下变频模块输入的数字 I&Q 信号进行低通滤波处理， _获得数字基带信号， 并输出给„多支路校正与切 换模块；
或者， 所述数字 I&Q解调部分包括：
M个单边带通滤波器模块， 用于将由 M个单通道模拟到数字转换 器输入的数字带通信号进行单边带通滤波处理， 并输出给数字下变频模 块；
数字下变频模块，用于将由 M个单边带通滤波器模块输入的数字带 通信号进行下变频处理， 获得数字基带信号， 并输出给多支路校正与切 换模块。
18、 根据权利要求 17所述的接收机， 其特征在于， 所述数字 I&Q 解调部分进一步包括：
时延校正系数计算模块，用于根据由 M个低通滤波器模块输入的数 字基带信号计算时延校正系数， 并将时延校正系数输出给滤波器系数计 算模块；
滤波器系数计算模块， 用于根据由时延校正系数计算模块输入的时 延校正系数得到滤波器系数， 并输出给所述 M个低通滤波器模块。
19、 根据权利要求 1所述的接收机， 其特征在于， 该接收机进一步 包括：
校正信号注入模块， 用于将接收机输入信号或自身产生的校正信号 输出给多支路校正前处理模块。
20、 根据权利要求 19所述的接收机， 其特征在于， 所述校正信号 注入模块包括：
开关模块， 用于将接收机输入信号或校正信号产生模块生成的校正 信号输出给多支路校正前处理模块；
校正信号产生模块， 用于生成校正信号， 并输出给开关模块。
21、 根据权利要求 19所述的接收机， 其特征在于， 所述校正信号 注入模块包括：
开关模块， 用于将接收机输入信号或校正信号转换模块生成的校正 信号输出给多支路校正前处理模块；
校正信号转换模块， 用于将来自发射机的信号转换为校正信号， 并 输出给开关模块。
22、 一种无线信号接收方法， 其特征在于， 该方法包括以下步骤: A、 将接收机的输入信号经过多支路校正前处理， 获得 M路未经过 幅相校正的数字基带信号；
B、 对未经过幅相校正的 M路数字基带信号进行幅度和相位校正， 再根据切换策略选择一路幅相校正后的数字基带信号；
C、 将所选择的数字基带信号进行数字处理， 获得比特流。
23、 根据权利要求 22所述的方法， 所述步骤 B为：
根据获得的 M个幅相校正系数分别将未经过幅相校正的 M路数字 基带信号进行幅度和相位校正， 再根据产生的切换控制信号从幅相校正 后的 M路数字基带信号中选择一路；
所述切换控制信号产生的方法为： 根据切换策略从未经过幅相校正 的 M路数字基带信号中确定一路作为被选中支路，产生携带有被选中支 路所对应支路号的切换控制信号。
24、 根据权利要求 23所述的方法， 其特征在于， 所述 M个幅相校 正系数的获取方法为：根据幅相校正系数计算方法获得 M个幅相校正系 数。
25、 根据权利要求 24所述的方法， 其特征在于，
步驟 B所述对未经过幅相校正的 M路数字基带信号进行幅度和相 位校正之前， 步骤 B进一步包括： 将未经过幅相校正的 M路数字基带 信号进行幅相校正前馈环时延补偿； 或者， _ .
步驟 B所述获得 M个幅相校正系数之后， 步骤 B进一步包括： 将 获得的 M个幅相校正系数进行幅相校正前馈环时延补偿。
26、 根据权利要求 24所述的方法， 其特征在于，
步骤 B所述产生切换控制信号之后，所述切换控制信号产生的方法 进一步包括： 将产生的切换控制信号进行切换前馈环时延补偿；
步骤 B所述将未经过幅相校正的 M路数字基带信号进行幅度和相 位校正之前， 步骤 B进一步包括： 将未经过幅相校正的 M路数字基带 信号进行切换前馈环时延补偿；
步骤 B所述进行幅度和相位校正和从幅相校正后的 M路数字基带 信号中选择一路之间进一步包括：将经过幅相校正的 M路数字基带信号 进行切换前馈环时延补偿。
27、 根据权利要求 24至 26任一项所述的方法， 其特征在于， 所述 幅相校正系数计算方法为：
XI、 各相邻支路对通过自身幅相校正窗口， 对输入信号经过多支路 校正前处理或幅相校正处理后获得的样点进行筛选， 确定用来进行本次 相对幅相校正系数计算的样点；
X2、各相邻支路对根据自身高增益支路上次功率值迭代和以及落入 自身幅相校正窗口的高增益支路本次样点功率值计算自身高增益支路 的本次功率值迭代和， 根据自身低增益支路的上次功率值迭代和以及低 增益支路本次样点功率值计算自身低增益支路的本次功率值迭代和， 根 值计算相邻支路对的本次互相关值迭代和;
X3、 各相邻支路对根据自身高增益支路的本次功率值迭代和、低增 益支路的本次功率值迭代和， 以及相邻支路对的本次互相关值迭代和计 算各相邻支路对自身的相对幅相校正系数； _
X4、 根据所有相邻支路对的相对幅相校正系数获得 M个幅相校正 系数。
28、 根据权利要求 27所述的方法， 其特征在于， 所述幅相校正系 数为幅相校正初始值；
步驟 XI所述输入信号为： 用于离线配置幅相校正系数初始值的输 入信号或接收机输入信号； 所述步骤 X2和步驟 X3之间进一步包括：
各相邻支路对判断样点落入自身幅相校正窗口的次数是否达到预 设值， 如果是， 则执行步骤 X3; 否则， 返回步骤 XI。
29、 根据权利要求 27所述的方法， 其特征在于， 所述幅相校正系 数为幅相校正系数最新值；
步骤 XI所述输入信号为： 校正信号或接收机输入信号；
步骤 B所述产生切换控制信号之后进一步包括：根据被选中支路情 况产生切换标志信号，并根据切换标志信号将计算出来的 M个幅相校正 系数最新值配置为当前的 M个幅相校正系数。
30、 根据权利要求 22所述的方法， 其特征在于， 所述切换策略为： S 1、从进行幅度和相位校正前的 M路数字基带信号中确定一路增益 最大但未饱和的支路， 将其作为候补被选中支路；
S2、判断上次 M路选一路模块的输出样点是否由候补被选中支路的 相邻低增益支路输出， 而且本次样点在候补被选中支路中的功率不低于 迟滞低门限， 如果是， 则将候补被选中支路的相邻低增益支路作为输出 本次样点的被选中支路; 否则， 将候补被选中支路作为输出本次样点的 被选中支路。
31、 根据权利要求 22所述的方法， 其特征在于， 所述步骤 A和步 骤 B之间进一步包括： _ . _ „ - 对经过多支路校正前处理后获得的未经过幅相校正的 M路数字基 带信号进行低通滤波和抽取处理。
32、 根据权利要求 22所述的方法， 其特征在于， 所述步骤 A包括： AX1、将接收机输入信号进行含模拟 I&Q解调功能的上游模拟接收 处理， 获得 M路模拟基带信号；
AX2、 将 M路模拟基带信号进行梯级增益处理， 再进行采样处理， 获得未经过幅相校正的 M路数字基带信号。
33、 根据权利要求 22所述的方法， 其特征在于， 所述步骤 A包括: AY1、 将接收机输入信号进行梯级增益处理和模拟 I&Q解调处理， 获得 M路模拟基带信号；
AY2、 将 M路模拟基带信号进行采样处理， 获得未经过幅相校正的 M路数字基带信号。
34、 根据权利要求 33所述的方法， 其特征在于， 步骤 AY1所述将 接收机输入信号进行梯级增益处理之前进一步包括：
将接收机输入信号进行不含模拟 I&Q解调功能的上游模拟接收处 理， 获得处理后的模拟带通信号。
35、 根据权利要求 32至 34任一项所述的方法， 其特征在于， 所述 步骤 A和步骤 B之间进一步包括：
根据获得的滤波器系数对未经过幅相校正的 M路数字基带信号进 行时延校正处理。
36、 根据权利要求 22所述的方法， 其特征在于， 所述步骤 A包括： AZ1、 将接收机输入信号进行梯级增益处理， 获得处理后的 M路模 拟带通信号；
AZ2、 将 M路模拟带通信号进行采样处理, 获得 M路数字带通信 号； ― 一
AZ3、 将 M路数字带通信号进行数字 I&Q解调处理和低通滤波处 理， 获得未经过幅相校正的 M路数字基带信号。
37、 根据权利要求 36所述的方法， 其特征在于， 步據 A1所述将接 收机输入信号进行梯级增益处理之前进一步包括：
将接收机输入信号进行不含模拟 I&Q解调功能的上游模拟接收处 理， 获得处理后的模拟带通信号。
38、 根据权利要求 36所述的方法， 其特征在于， 步骤 AZ3所述低 通滤波处理和获得未经过幅相校正的数字基带信号之间进一步包括： 根 据获得的滤波器系数对 M路数字信号进行时延校正处理。
39、 根据权利要求 35或 38所述的方法， 其特征在于， 所述滤波器 系数的获取方法为： 根据滤波器系数计算方法获得滤波器系数；
所述滤波器系数计算方法为：
Yl、 各相邻支路对通过各自的时延校正窗口， 对输入信号经过多支 路校正前处理得到的样点进行筛选， 确定用来进行本次时延校正计算的 样点；
Υ2、各相邻支路对根据各自的上次时延互相关值迭代和以及本次时 延互相关功率值， 计算各相邻支路对本次时延互相关值迭代和；
Υ3、各相邻支路对根据各自的本次时延互相关值迭代和获得各相邻 支路对的本次时延残差 , 并根据自身本次时延残差和上次相对时延校正 系数确定各相邻支路对的本次相对时延校正系数；
Υ4、各个相邻支路根据本次相对时延校正系数获得全体时延校正系 数， 并根据全体时延校正系数和事先设置的时延目标值获得滤波器系 数。
40、 根据权利要求 39所述的方法， 其特征在于， 所述滤波器系数 为滤波器系数初始值或滤波器系数最新值。 .
41、 根据权利要求 40所述的方法， 其特征在于， 如果滤波器系数 为滤波器系数初始值， 则步骤 Y1所述输入信号为： 用于离线配置滤波 器系数初始值的输入信号或接收机输入信号； ..
所述步骤 Υ3和步骤 Υ4之间进一步包括：
各相邻支路对判断样点落入时延校正窗口的次数是否达到预设值， 如果达到， 则执行步骤 Υ4; 否则， 返回步骤 Yl。
42、 根据权利要求 40 所述的方法， 其特征在于， 如果滤波器系数 为滤波器系数最新值， 则步骤 Y1所述输入信号为： 校正信号或接收机 输入信号。
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