Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
  • H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N25/713—Transfer or readout registers; Split readout registers or multiple readout registers

Definitions

• the invention relates generally to the field of charge-coupled devices and, more particularly, to improving the charge transfer electric field in a CCD operating in a half resolution mode.
• Fig. 1 shows a prior art charge coupled device (CCD) operable in two modes.
• the first mode is a full-resolution image read out mode and the second mode is a half-resolution double speed read out mode.
• the double speed read out mode two adjacent charge packets are summed together and are transferred two times faster than in full resolution mode.
• Fig. 1 a pseudo-2-phase CCD is shown with every other gate pair connected to timing signal Hl .
• the gate pairs between Hl alternate between timing signals H2 and H3.
• Fig. 2 shows the timing signals for the full-resolution read out of Fig. 1.
• H2 and H3 are clocked the same and with the opposite phase of Hl. This timing causes the charge packets in the CCD to be advanced by two gate pairs for each clock cycle.
• Fig. 3 shows the transfer of charge in the half-resolution double speed read out mode and Fig. 4 shows the timing signals for Fig. 3.
• Hl is held at a constant DC voltage.
• H2 and H3 are now clocked with opposite phase.
• the amplitude of the clock signals H2 and H3 is double the full-resolution mode amplitude shown in Fig. 2.
• This double speed timing advances the charge packets four gate pairs in one clock cycle, twice as far as the full-resolution mode.
• the double speed timing mode also sums together two adjacent charge packets to reduce the resolution by one half.
• One deficiency of the charge transfer shown in Fig. 3 is the voltage potential steps are small and the distance the charge travels is long. Consequently, it is desirable to increase the voltage between adjacent gate pairs to increase the . electric field strength in the CCD. An increased electric field will improve the charge transfer efficiency.
• the method resides in a charge coupled device having a plurality of non-adjacent, first gate electrode pairs; a plurality of second gate electrode pairs placed in every second space between the first gate electrode pairs; a plurality of third gate electrode pairs placed in the spaces between the first gate electrode pairs not occupied by the second gate electrode pairs; wherein, in a full resolution mode, the first gate electrode pairs are clocked substantially 180 degrees out of phase with respect to the second and third gate electrode pairs and the second and third gate electrode pairs are clocked substantially equally; wherein, in a half resolution, double speed mode, the second and third gate electrode pairs are clocked substantially 180 degrees out of phase with respect to each other and substantially 50% duty cycle and the first gate electrode pairs are clocked with 25% or less duty cycle and 90 degrees out of phase with respect to the second gate electrode pairs.
• the present invention has the following advantages of increasing the voltage between adjacent gate pairs to increase the electric field strength in the CCD. An increased electric field will improve the charge transfer efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
• Fig. 1 is prior art showing full resolution CCD charge transfer
• Fig. 2 is the prior art timing diagram for Fig. 1
• Fig. 3 is prior art showing half resolution double speed CCD charge transfer
• Fig. 4 is the prior art timing diagram for Fig. 3;
• Fig. 5 is a charge transfer in a half resolution double speed CCD with increased electric field for improved charge transfer efficiency;
• Fig. 6 is the timing diagram for Fig. 5;
• Fig. 7 is a charge transfer for the full resolution mode
• Fig. 8 is the timing diagram for Fig. 7;
• Fig. 9 is the invention implemented with a true-2-phase CCD; and Fig. 10 is a digital camera using an image sensor employing a half resolution double speed CCD with increased electric field for improved charge transfer efficiency.
• Fig. 5 shows an image sensor CCD 10 with improved half resolution double speed mode charge transfer efficiency. It consists of three gate pairs Hl , H2, and H3. Every other gate pair is connected to timing signal Hl . The gate pairs between Hl alternate between timing signals H2 and H3. The timing signals for Fig. 5 are shown in Fig. 6.
• the CCD timing signals H2 and H3 are clocked 180 degrees or substantially 180 degrees out of phase with respect to each other and with double the amplitude of timing signal Hl .
• the H2 and H3 timing signals have a 50% duty cycle.
• timing signal Hl is clocked with less than a 50% duty cycle and 90 degrees out of phase from timing signal H2. This sets up the situation in Fig.
• Fig. 7 shows the charge transfer when the CCD is clocked in foil- resolution read out mode.
• the timing diagram for Fig. 7 is shown in Fig. 8.
• H2 and H3 are clocked in phase with respect to each other and with half the amplitude of the half resolution double speed mode.
• the Hl timing signal is clocked 180 degrees out of phase or substantially 180 degrees out of phase with respect to H2 or H3.
• the amplitude of the timing signals can be the same as the half resolution double speed mode or they can be set to one half amplitude (as shown in Fig. 8).
• Fig. 10 illustrates a digital camera 20 having the CCD image sensor 10 disposed therein for illustrating a typical commercial embodiment to which the ordinary consumer is accustomed.

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Transforming Light Signals Into Electric Signals (AREA)
• Solid State Image Pick-Up Elements (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (2)

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ID=38705158

Family Applications (1)

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Family Cites Families (12)

• 2006
  • 2006-05-19 US US11/437,536 patent/US7643078B2/en not_active Expired - Fee Related
• 2007
  • 2007-05-07 JP JP2009510975A patent/JP4768067B2/ja not_active Expired - Fee Related
  • 2007-05-07 EP EP07809046A patent/EP2022254B1/en not_active Not-in-force
  • 2007-05-07 WO PCT/US2007/011017 patent/WO2007136539A2/en not_active Ceased
  • 2007-05-18 TW TW096117813A patent/TW200803486A/zh unknown

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