WO2007136010A1 - ディジタル信号分波装置及び合波装置 - Google Patents
ディジタル信号分波装置及び合波装置 Download PDFInfo
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- WO2007136010A1 WO2007136010A1 PCT/JP2007/060268 JP2007060268W WO2007136010A1 WO 2007136010 A1 WO2007136010 A1 WO 2007136010A1 JP 2007060268 W JP2007060268 W JP 2007060268W WO 2007136010 A1 WO2007136010 A1 WO 2007136010A1
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- 238000005070 sampling Methods 0.000 claims abstract description 44
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- 239000011159 matrix material Substances 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 35
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J1/00—Frequency-division multiplex systems
- H04J1/02—Details
- H04J1/08—Arrangements for combining channels
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0248—Filters characterised by a particular frequency response or filtering method
- H03H17/0264—Filter sets with mutual related characteristics
- H03H17/0266—Filter banks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0294—Variable filters; Programmable filters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J1/00—Frequency-division multiplex systems
- H04J1/02—Details
- H04J1/04—Frequency-transposition arrangements
- H04J1/05—Frequency-transposition arrangements using digital techniques
Definitions
- the present invention relates to a digital signal demultiplexing device that separates a plurality of frequency-multiplexed signals by digital signal processing, and a digital signal multiplexing device that frequency-multiplexes a plurality of signals by digital signal processing.
- FIG. 1 is a configuration diagram of a digital signal demultiplexing device described in Patent Document 1, and shows a case where a maximum of eight signals are demultiplexed and output.
- the digital signal demultiplexer connects 1-input 2-output 2-demultiplex filter banks 81-87 in a dendritic manner. More specifically, the second-stage second demultiplexing filter bank 82 and 83 are connected to the first-stage second demultiplexing filter bank 81, and the second-stage second demultiplexing filter bank 82 is connected to the second-stage second demultiplexing filter bank 82.
- the demultiplexing filter banks 84 and 85 are connected, and the second demultiplexing filter bank 86 and 87 are connected to the second demultiplexing filter bank 83.
- each of the two demultiplexing filter banks includes a low-pass filter and a high-pass filter that limit the bandwidth of the input signal, and outputs and high-pass filters of the low-pass filter. It consists of a down sampler connected to each output of the side pass filter.
- the downsampler has a function of thinning out every other sample value of the input signal, that is, downsampling the sampling frequency to 1Z2.
- the frequency characteristics of the low-pass filters of the two demultiplexing filter banks 81, 82, 84 and 86 are the filter A of FIG.
- the frequency characteristics of the high-pass filter is filter B in Fig. 4, and the frequency characteristics of the low-pass filters in the two-divided filter banks 83, 85, and 87 are filter C in Fig. 4, which is also the high-pass filter.
- the frequency characteristic of the filter is filter D in Fig. 4.
- a two-demultiplexing filter bank consisting of filters A and B is connected after filter A or the same, and a two-demultiplexing filter bank consisting of filters C and D is connected after filter B or D. is doing. Note that the frequency characteristics of each filter shown in Fig. 4 are normalized by the sampling frequency fs of the input signal to the 2nd-order filter bank.
- Each of the two demultiplexing filter banks divides the input signal into two on the frequency axis by the low-pass filter and the high-pass filter, and down-samples and outputs each of the divided signals.
- the digital signal demultiplexing device shown in FIG. 1 performs demultiplexing processing by connecting these two demultiplexing filter banks in a dendritic manner by a predetermined number of stages.
- the predetermined number of stages is log N for the maximum number N to be demultiplexed.
- FIG. 5 is a diagram showing the frequency bands of signals that can be processed by the digital signal demultiplexer that demultiplexes up to eight signals shown in FIG. It corresponds to the signal name shown in. Note that the sampling frequency Fs in FIG. 5 is the sampling frequency of the input signal to the first-stage second-division filter bank 81.
- FIG. 2 is a configuration diagram of the digital signal multiplexing device described in Patent Document 1, and shows a case where up to eight signals are multiplexed and output.
- the digital signal multiplexer has a 2-input 1-output 2-multiplex filter bank 91-97 connected in a dendritic manner. More specifically, the first-stage 2-multiplex filter banks 91 and 92 are connected to the second-stage 2-multiplex filter bank 95 via the selector 98, and the first-stage 2-multiplex filter banks 93 and 94 are connected. Are connected to the second-stage 2-multiplex filter bank 96 via the selector 98, and the second-stage 2-multiplex filter bank 95 and 96 are connected to the second-stage 2-multiplex filter bank 97 via the selector 98. Connected to.
- each 2-multiplex filter bank is provided for each of two input signals, and by interpolating a sample value of 0 between each sample value of the input signal, the sampling frequency
- An up-sampling unit that converts the output signal of one up-sampling unit, a low-pass filter that limits the bandwidth of the output signal of one up-sampling unit, a high-pass filter that limits the bandwidth of the output signal of the other up-sampling unit, The output signal of the side-pass filter and the high-pass filter And an adder for adding and outputting the output signals.
- the frequency characteristics of the low-pass filters of the two-multiplex filter banks 91, 93, 95, and 97 are the filter A of FIG.
- the frequency characteristics of the pass filter are filter B in Fig. 4, and the frequency characteristics of the low-pass filters in the two-multiplex filter banks 92, 94, and 96 are filter C in Fig. 4, which is also the frequency of the high-pass filter.
- the characteristic is filter D in Fig. 4.
- a 2-multiplex filter bank composed of filters A and B is connected in front of filter A or the same, and a 2-complex filter bank composed of filters C and D is connected in front of filter B or D. is doing. Note that the frequency characteristics of each filter shown in FIG. 4 are normalized by the sampling frequency fs of the output signal of the 2-multiplex filter bank.
- Each two-multiplex filter bank up-samples two input signals to twice the sampling frequency, respectively, and generates unnecessary harmonic components using a low-pass filter and a high-pass filter, respectively. Remove and output frequency-multiplexed so that they are adjacent in frequency.
- the digital signal multiplexer shown in FIG. 2 performs the multiplexing process by connecting each of these two multiplexing filter banks in a toothed manner for a predetermined number of stages.
- the predetermined number of stages is log N for the maximum number N to be combined.
- the selector 98 connected to the output selects the frequency multiplexed signal output by the two multiplexing filter bank and one signal having the same bandwidth as the frequency multiplexed signal.
- the output of the selector 98 is the next. This is the input signal for the two-stage multiplexing filter bank.
- FIG. 5 is a diagram showing the frequency band of signals that can be processed by the digital signal multiplexer that multiplexes up to eight signals shown in FIG. 2 and the frequency positional relationship thereof, and the signal names are shown in FIG. It corresponds to the signal name shown in. Note that the sampling frequency Fs in FIG. 5 is the sampling frequency of the output signal of the 2-multiplex filter bank 97 in the last stage.
- Patent Document 1 Patent No. 3299952
- the filter banks of the conventional digital signal demultiplexing device and digital signal multiplexing device shown in FIGS. 1 and 2 use the filters A and B shown in FIG.
- the force that can be divided into those using filter C and filter D in any of these cases cannot process signals in the frequency band that crosses the boundary. For this reason, depending on the band of the signal and the frequency position in the frequency multiplex signal, what can be processed and what cannot be processed are generated.
- FIG. 6A uses the signals S41, S32 and S22 of FIG. 5, and FIG. 6B uses the signals S31, S43 to S46 and S34 of FIG.
- This is a combination that can be processed by a digital signal demultiplexer and a digital signal multiplexer according to the prior art.
- the signal groups shown in FIG. 6C and FIG. 6D are combinations that cannot be processed by the conventional digital signal demultiplexer and digital signal multiplexer. In this way, the signal that crosses the passband boundary between the low-pass filter and the high-pass filter in the 2-multiplex filter bank has a loss in the frequency spectrum.
- the present invention removes the restriction on the processable signal described above, and allows a digital signal demultiplexing device and a digital signal multiplexing to flexibly select a signal bandwidth to be used and a frequency position in a frequency multiplexed signal.
- An object is to provide an apparatus.
- a digital signal demultiplexing device that solves the above-described problem and outputs a received signal having a plurality of signal powers that are arbitrarily frequency-multiplexed and demultiplexed.
- the digital signal demultiplexing apparatus includes a multi-stage unit demultiplexing filter bank including one or more filters for filtering an input signal and a down sammbler for down-sampling the output signal of each filter and outputting it. And a frequency conversion 'decimator means for receiving at least one of the received signal and the output signal of each unit branch filter bank.
- the digital signal multiplexing device includes one or more up-samplers that up-sample and output an input signal, and a filter that removes unnecessary components from the output signal of each up-sampler and outputs the unit signal.
- a combination filter bank means including a multi-stage connection of wave filter banks, and a frequency conversion interpolator means for outputting at least one signal to be added to one of the output signals of the unit combination filter bank.
- Frequency conversion 'Interpolator means is a combination of one or more interpolator means connected in series and a frequency conversion means that shifts and outputs the frequency of the signal output by the last interpolator means.
- the interpolator means includes an up-sampler that up-samples the input signal and outputs the up-sampler. And a filter for outputting to remove unwanted signal components of the force signal, Ru.
- the digital signal demultiplexing apparatus can use a signal straddling the boundary of the frequency band fixedly divided by the demultiplexing filter bank means by shifting the frequency in the frequency converting means.
- the amount of frequency shift in the frequency conversion means is determined based on the pass band of the decimator means connected to the subsequent stage. More specifically, the frequency shift amount in the frequency conversion means is determined based on the pass band of the decimator means and the frequency position of the signal to be separated among the signals included in the input signal. In this way, by providing the frequency conversion / decimator means corresponding to the signal straddling the boundary, it becomes possible to process a signal of an arbitrary frequency and band.
- the demultiplexing filter bank means demultiplexes other signals, and it is not necessary to provide frequency conversion / decimator means for each signal, so that the circuit scale can be reduced.
- the digital signal multiplexing device can be used by shifting the frequency of the signal straddling the fixed frequency band boundary in the multiplexing filter bank means in the frequency conversion means. Yes.
- the amount of frequency shift in the frequency conversion means is determined based on the pass band of the interpolator means connected to the previous stage. More specifically, frequency conversion The amount of frequency shift in the means is determined based on the passband of the interpolator means connected to the previous stage and the frequency position in the frequency multiplexed signal of the signal filtered by the filter.
- the multiplexing filter bank means multiplexes and it is not necessary to provide a frequency conversion interpolator means for each signal, so the circuit scale can be reduced.
- FIG. 1 is a block diagram of a conventional digital signal demultiplexing device.
- FIG. 2 is a block diagram of a conventional digital signal multiplexer.
- FIG. 3A is a configuration diagram of a two-demultiplexing filter bank.
- FIG. 3B is a configuration diagram of a two-multiplex filter bank.
- FIG. 4 is a diagram showing frequency characteristics of filters used in the two-band filter bank and the two-band filter bank.
- FIG. 5 is a diagram showing the frequency band relationship of each signal in a digital signal demultiplexing device and a digital signal multiplexing device for processing a maximum of eight signals according to the prior art.
- FIG. 6A is a diagram for explaining signals that can be processed in a digital signal demultiplexer and a digital signal multiplexer that perform a maximum of eight signal processes according to the prior art.
- FIG. 6B is a diagram for explaining signals that can be processed and signals that cannot be processed in a digital signal demultiplexer and a digital signal multiplexer that process up to eight signals according to the prior art.
- FIG. 6C is a diagram for explaining signals that cannot be processed in a digital signal demultiplexer and a digital signal multiplexer that process a maximum of eight signals according to the prior art.
- FIG. 6D is a diagram for explaining signals that cannot be processed in the digital signal demultiplexer and the digital signal multiplexer that process a maximum of eight signals according to the prior art.
- FIG. 7 is a block diagram of a digital signal branching device in an embodiment of the present invention.
- FIG. 8 is a configuration diagram of a demultiplexing filter bank unit.
- FIG. 9A is a configuration diagram of a frequency conversion decimator unit.
- FIG. 9B is a block diagram of a decimator.
- FIG. 10 is a block diagram of a digital signal multiplexing device in an embodiment of the present invention.
- FIG. 11 is a configuration diagram of a multiplexing filter bank unit.
- FIG. 12A is a configuration diagram of a frequency conversion interpolator unit.
- FIG. 12B is a configuration diagram of an interpolator.
- FIG. 13 is a diagram showing a relationship between signals usable in the digital signal demultiplexing device and the digital signal multiplexing device in the embodiment of the present invention.
- FIG. 14A is a block diagram of another embodiment of a digital signal branching device.
- FIG. 14B is a block diagram of a band-variable two-demultiplexing filter bank.
- FIG. 15A is a block diagram of another embodiment of a digital signal multiplexer.
- FIG. 15B is a block diagram of a band-variable two-multiplex filter bank.
- FIG. 7 is a block diagram of a digital signal branching device in the embodiment of the present invention.
- the digital signal demultiplexing device of this embodiment includes a demultiplexing filter bank unit 1, a frequency conversion / decimator unit 2, and a switch matrix unit 3.
- FIG. 8 is a configuration diagram of the demultiplexing filter bank unit 1 of FIG.
- the demultiplexing filter bank unit 1 is configured by connecting multi-stage branching filter banks 11 to 17 having one input and two outputs in a dendritic manner.
- the second-stage demultiplexing filter banks 12 and 13 are connected to the first-stage second demultiplexing filter bank 11, and the second-stage demultiplexing filter bank 12 is connected to the second-stage demultiplexing filter bank 12.
- Wave filter banks 14 and 15 are connected, and the second-stage demultiplexing filter bank 16 and 17 are connected to the second-stage diplexing filter bank 13.
- each of the two demultiplexing filter banks includes a low-pass filter and a high-pass filter that limit the bandwidth of the input signal, and outputs and high-pass filters of the low-pass filter. It consists of a down sampler connected to each output of the side pass filter.
- the downsampler has a function of thinning out every other sample value of the input signal, that is, downsampling the sampling frequency to 1Z2.
- the frequency characteristics of the low-pass filters of the two-divided filter banks 11, 12, 14, and 16 are as follows.
- the filter is the filter A in Fig. 4
- the frequency characteristics of the high-pass filter is the filter B in Fig. 4.
- the frequency characteristics of the low-pass filters in the two-band filter banks 13, 15, and 17 are
- the frequency characteristic of the high-pass filter is filter D in Fig. 4.
- filters A and B are used for the first-stage two-demultiplexing filter bank, and thereafter, a two-demultiplexing filter bank composed of filters A and B is used as the filter B or D after the filter A or C.
- the second half of the filter bank consisting of filters C and D is sequentially connected to the subsequent stage.
- the frequency characteristics of each filter shown in Fig. 4 are specified so that the passband is within the range of 0 to fs, which is normalized by the sampling frequency fs of the input signal to the two-band filter bank. is there.
- the second demultiplexing filter bank 11 filters the input signal S11 to the demultiplexing filter bank unit 1 by using a low-pass filter and a high-pass filter having different pass bands, respectively. Two different signals are extracted, and each extracted signal is down-sampled and output as signals S21 and S22. Thereafter, similarly, the second branch filter bank unit 12 inputs the signal S21 and outputs signals S31 and 32, and the second branch filter bank unit 13 inputs the signal S22 and outputs signals S33 and 34. . Further, the two-divided filter banks 14, 15, 16 and 17 receive the signals S31, S32, S33 and S34, and receive the signals S41 and S42, S43 and S44, S45 and S46, S47 and S48, respectively. Output.
- the demultiplexing filter bank unit 1 of the digital signal demultiplexing device divides the frequency multiplexed signal into fixed frequency bands and outputs signals included in the respective frequency bands. As long as these are sequentially performed in a multi-stage configuration, the configuration is not limited to the above-described configuration.
- the demultiplexing filter bank unit 1 is a multi-stage unit demultiplexing filter bank having one or more filters and a down sampler that down-samples and outputs the output signal of each filter. OK.
- the above two demultiplexing filter bank is an example of a unit demultiplexing filter bank.
- FIG. 9A is a configuration diagram of the frequency conversion / decimator unit 2. According to Figure 9A, frequency conversion
- the decimator unit 2 includes frequency conversions 21 to 23 and decimators 24 to 27. As shown in FIG. 9B, each decimator includes a low-pass filter 201 for limiting the bandwidth of the input signal and a downsampler 202. Downsampler 202 is the input signal sampler. 4 has a function of decimating every other value, that is, down-sampling the sampling frequency to 1Z2. As the low-pass filter 201, the filter A force in FIG. Here, the sampling frequency fs is the sampling frequency of the decimator input signal.
- t time
- f the frequency difference between the output signal and the input signal, that is, the frequency shift amount
- ⁇ is an arbitrary phase.
- the decimator 24 band-limits the output signal of the frequency converter 21, down-samples it, and outputs a signal S23.
- Decimator 25 receives signal S23 and outputs signal S35.
- the decimator 26 receives the output signal of the frequency shift ⁇ 22 as an input and outputs a signal S36, and the decimator 27 receives the output signal of the frequency shift 23 and outputs a signal S37.
- FIG. 13 shows the relationship between the frequency band of each signal described above and the frequency position of the frequency multiplexed signal.
- the sampling frequency Fs is the sampling frequency of the input signal to the two-divided filter bank 11. .
- the frequency shift amount of the signal S11 at the frequency converter 21 is the amount indicated by the dotted arrow on the left side of the signal S23 when the signal S23 is used, and the signal shift amount when the signal S35 is used. This is the amount indicated by the dotted arrow on the left side of S35.
- the amount of frequency shift of signal S21 at frequency variation ⁇ 22 is the amount indicated by the dotted arrow on the left side of signal S36
- the amount of frequency shift of signal S22 at frequency converter 23 is The amount indicated by the dotted arrow on the left side of the signal S37.
- the filter A of FIG. 4 is used for the low-pass filter 201 of the decimators 24, 25, and 26, and the filter C of FIG. 4 is used for the low-pass filter 201 of the decimator 27.
- the filter A in Fig. 4 can be used. In other words, each frequency change The frequency shift amount is determined by the frequency characteristics of the low-pass filter used in the decimator connected in series in the subsequent stage.
- the frequency shift amount in each frequency converter is the frequency characteristic of the low-pass filter used in the decimator connected in series in the subsequent stage and the signal included in the input signal. It is determined by the frequency position of the signal to be separated. Of the signals included in the input signal, the signal power to be separated is shifted so that the frequency of the input signal is within the passband of the decimator.
- the same decimator low-pass filter with the same frequency characteristics, for example, any one of the signals S35 to S37.
- only two circuits with frequency variation and decimator power can be prepared, so that the circuit scale can be reduced.
- the number of decimators connected in series after the frequency converter depends on the number of stages in the demultiplexing filter bank unit 1 of the input signal and the number of stages in the demultiplexing filter bank unit 1 corresponding to the output signal band. The difference. In other words, when outputting S35, which is a signal in the band corresponding to S31 to S34, which is the third stage input, from the signal S11, which is the first stage input of the demultiplexing filter bank unit 1, 3 to 1 is output. Connect the two decimators with the drawn values in series.
- the switch matrix unit 3 outputs the signals S 11, S 21 to S 22, S 31 to S 34 and S 41 to S 48 output from the demultiplexing filter bank unit 1, and the frequency conversion “decimator input S”.
- these signals are used to guide the actual signal to be used to the specified output port of the digital signal demultiplexer, and are provided to change the thread alignment of the signal to be used as necessary. It is done.
- FIG. 10 is a block diagram of a digital signal multiplexer in the embodiment of the present invention.
- the digital signal multiplexer includes a multiplexing filter bank unit 4, a frequency conversion / interpolator unit 5, and a switch matrix unit 3.
- FIG. 11 is a configuration diagram of the multiplexing filter bank unit 4 of FIG.
- the multiplex filter bank unit 4 is configured by connecting two multiplex filter banks 41 to 47 having two inputs and one output in a multi-stage manner. More specifically, the first-stage 2-multiplex filter banks 41 and 42 are connected to the 2-stage 2-multiplex filter bank 45 via the selector 48, and the first-stage 2-multiplex filter banks 43 and 44 are connected. Then, it is connected to the second-stage 2-multiplex filter bank 46 via the selector 48.
- the output of the second-stage 2-multiplex filter bank 45 is connected to the selector 481, the output of the selector 481 is connected to the adder 491, and the output of the adder 491 is connected to one input of the 2-multiplex filter bank 47.
- the output of the second multiplex filter bank 46 in the second stage is connected to the selector 482, the output of the selector 482 is connected to the adder 492, and the output of the adder 492 is connected to the other of the two multiplex filter bank 47. Input.
- the output of the 2-multiplex filter bank 47 is connected to the selector 483, the output of the selector 483 is connected to the adder 493, and the output power of the adder 493 becomes the output of the digital signal multiplexer.
- each 2-multiplex filter bank is provided for each of the two input signals, and by interpolating a sample value of 0 between each sample value of the input signal, the sampling frequency
- An up-sampling unit that converts the output signal of one up-sampler, a low-pass filter that limits the bandwidth of the output signal of one up-sampling device, a high-pass filter that limits the bandwidth of the output signal of the other up-sampling device, It consists of an adder that adds and outputs the output signal of the side-pass filter and the output signal of the high-pass filter.
- the frequency characteristics of the low-pass filters in the two-multiplex filter banks 41, 43, 45, and 47 are the filter A in FIG. 4, and the frequency characteristics of the high-pass filters are also in FIG.
- Filter B is the frequency response of the low-pass filter in the 2 multiplexing filter banks 42, 44 and 46 Is the filter C of FIG. 4, and the frequency characteristic of the high-pass filter is the filter D of FIG.
- filters A and B are used for the final two-combining filter bank 47, and a two-combining filter bank composed of filters A and B is used in front of filter A or C.
- two multiplex filter banks consisting of filters C and D are sequentially connected. Note that the frequency characteristics of each filter shown in Fig. 4 are specified so that the passband is within the range of 0 to fs, normalized by the sampling frequency fs of the output signal of the 2-multiplex filter bank.
- Each two-multiplex filter bank up-samples two input signals to twice the sampling frequency, and removes unnecessary harmonic components of the up-sampled signal with each filter.
- the signal after removing the harmonic components is synthesized, that is, frequency-multiplexed and output.
- the 2-multiplex filter banks 41, 42, 43, and 44 receive the digital signals S41 and S42, S43 and S44, S45 and S46, S47 and S48, respectively, and frequency multiplex them to the selector 48. Output.
- the 2-multiplex filter bank 45 includes the output signal or signal S31 of the 2-multiplex filter bank 41 selected by one selector 48 and the 2-multiplex filter bank 42 selected by the other selector 48. Output signal or signal S32 as input, frequency-multiplexed and output.
- the 2-multiplex filter bank 46 includes the output signal or signal S33 of the 2-multiplex filter bank 43 selected by one selector 48 and the 2-multiplex filter bank 44 selected by the other selector 48. The output signal or signal S34 is input, and frequency-multiplexed and output.
- the Calo arithmetic unit 491 adds the output signal or signal S21 of the 2-multiplex filter bank 45 selected by the selector 481 and a signal S51 from the frequency conversion interpolator unit 5 described later, and the Calo arithmetic unit 492 Then, the output signal or signal S22 of the 2-multiplex filter bank 46 selected by the selector 482 and the signal S52 from the frequency conversion interpolator unit 5 described later are added.
- the 2-multiplex filter bank 47 receives the output signals of the adders 491 and 492, and outputs the multiplexed signals.
- the selector 483 selects the output signal or the signal S11 of the 2-multiplex filter bank 47 and outputs the selected signal to the adder 493.
- the adder 493 adds the signal from the selector 483 and the frequency conversion interpolator. Signal S61 from section 5 is added to the output signal of the digital signal multiplexer. Generate.
- the multiplexing filter bank unit 4 of the digital signal multiplexing device in the embodiment of the present invention outputs a plurality of input signals in a predetermined band as frequency multiplexed signals arranged in a fixed frequency band.
- the configuration is not limited to the above-described configuration.
- the multiplexing filter bank unit 4 includes unit multiplexing having one or more up-samplers that up-sample and output an input signal and a filter that removes unnecessary components from the output signal of each up-sampler and outputs them.
- a configuration in which filter banks are connected in multiple stages may be used.
- the 2-multiplex filter bank is an example of such a unital filter bank.
- FIG. 12A is a configuration diagram of the frequency conversion / interpolator unit 5.
- the frequency conversion / interpolator unit 5 includes interpolators 51 to 54, frequency converters 55 to 57, and a selector 58.
- each interpolator passes only the necessary signal components from the upsampler 501 and the output signal including the image components generated as a result of the upsampling by the upsampler 501, and generates unnecessary signals.
- a low-pass filter 502 that removes components.
- the up-sampler 501 has a function of converting the sampling frequency to double by interpolating a sample value of 0 between each sample value of the input signal.
- the low-pass filter 502 is shown in FIG. Use one of filters A through D.
- the sampling frequency fs is the sampling frequency of the output signal of the interpolator.
- the frequency converters 55 to 57 shift and output the frequency of the input signal.
- Interpolator 51 up-samples signal S35, and then removes harmonic components.
- Selector 58 selects and outputs signal S23 or the output signal of interpolator 51.
- Interpolator 54 After upsampling the output signal, the harmonic component is removed, and the frequency converter 55 converts the frequency of the output signal of the interpolator 54 and outputs a signal S61.
- interpolator 52 up-samples signal S36 and then removes harmonic components, frequency converter 56 frequency-converts the output signal of interpolator 52 and outputs signal S51, and interpolator 53 Upsampling signal S37 After that, the harmonic component is removed, and the frequency converter 57 converts the frequency of the output signal of the interpolator 52 and outputs a signal S52.
- FIG. 13 shows the frequency position and frequency band of each signal described above in the frequency multiplexed signal output by the digital signal multiplexing value, and the sampling frequency Fs is located in the final stage. 2 Sampling frequency of the output signal of the multiplexing filter bank 47.
- the frequency shift amount in the frequency converter 55 is the amount indicated by the dotted arrow on the left side of the signal S23 when the signal S23 is used, and on the left side of the signal S35 when the signal S35 is used. This is the amount indicated by a dotted arrow.
- the frequency shift amount at the frequency converter 56 is the amount indicated by the dotted arrow on the left side of the signal S36
- the frequency shift amount at the frequency converter 57 is the dotted line on the left side of the signal S37. This is the amount indicated by the arrow.
- These frequency shifts mean shifting to the right side, that is, to the high frequency side by an amount corresponding to each dotted arrow.
- the filter A in FIG. 4 is used for the low-pass filter 201 of the interpolators 51, 52 and 54, and the filter C in FIG. 4 is used for the low-pass filter 502 of the interpolator 53.
- the low pass filter 502 of the interpolator 53 is used.
- filter A in Fig. 4 can be used. In other words, the amount of frequency shift at each frequency change is determined by the frequency characteristics of the low-pass filter used in the interpolator that is connected in series in the preceding stage.
- the amount of frequency shift in each frequency converter depends on the frequency characteristics of the low-pass filter used in the interpolator connected in series in the preceding stage and the low-pass filter. It is determined by the frequency position within the frequency multiplexed signal of the waved signal. The frequency is shifted so that the signal filtered by the low-pass filter becomes the desired frequency position in the frequency multiplexed signal.
- the circuit for outputting the signal S61 from the signal S23 or S35 is shared by changing the frequency shift amount in the frequency converter.
- the circuit composed of frequency change ⁇ 55 and interpolators 51 and 54 is dedicated to signal S35, and another circuit dedicated to signal S23 is provided.
- the configuration may be selected.
- the switch matrix unit 3 inputs a maximum of eight input signals to the digital signal multiplexing device to the predetermined input of the multiplexing filter bank unit 4 and the Z or frequency conversion interpolator unit 5. It is for guiding.
- the processing circuit consisting of one or more interpolators and one frequency converter can be selected according to the combination of signals used. It is. For example, when only two waves shown in FIG. 6D are used in a fixed manner, the processing circuits starting with the two-frequency demultiplexing filter banks 13 and 15 to 17 in FIG. 8 and the frequency shifts ⁇ 22 and 23 in FIG. Processing circuits starting with interpolators 52 and 53 in Figure 12A are not required.
- the switch matrix unit 3 is for flexibly changing the yarn alignment of the signals to be used, and can be omitted if the signals to be used are fixed and need not be changed.
- FIG. 14A is a block diagram of another embodiment of the digital signal demultiplexing device.
- the digital signal demultiplexer includes a band-variable demultiplexing filter bank 61, a memory 62, a frequency converter 63, a decimator 64, a serial-parallel converter 65, and a time-division operation control unit. 6 and 6.
- the band-variable duplex filter bank 61 includes a variable low-pass filter 601, a variable high-pass filter 602, and downsamplers 603 and 604.
- variable low-pass filter 601 can switch between the filter A and the filter C in Fig. 4 based on the control from the time-division operation control unit 66, and the variable high-pass filter 602 Based on the control from the split operation control unit 66, the filter B or the filter D in FIG. 4 can be switched.
- These switching of the passbands can be realized by various known methods such as switching between two types of filters prepared in advance or changing the tap coefficient of the digital filter.
- the down samplers 603 and 604 have a function of thinning out every other sample value of the input signal, that is, down-sampling the sampling frequency to 1Z2, and the frequency converter 63 includes the time-division operation control unit 66
- the decimator 64 has the function of performing frequency conversion of the input signal based on the control, and is the same as FIG. 9B.
- the present embodiment is characterized in that the same processing as the processing in FIGS. 8, 9A, and 9B is executed in a time division manner by using the memory 62.
- FIG. the input signal S11 is stored in the memory 62, and the band-variable second demultiplexing filter bank 61 is configured in the same manner as the second demultiplexing filter bank 11 in FIG. S21 and S22 are stored in the memory 62 in the same manner.
- the band-variable second demultiplexing filter bank 61 is configured in the same manner as the second demultiplexing filter bank 12 in FIG. 8, and then the signal S21 is read from the memory 62.
- the processed signals S31 and S32 are stored in the memory 62. Further, when the signal S35 is used, the frequency shift amount of the frequency shift 63 is set as shown in FIG. 13, and the signal S35 is read from the memory 62 for processing, and then the decimator 64 is sent via the memory 62. Perform the process twice.
- the time-division operation control unit 66 controls each unit for the time-division processing, and the serial-parallel change 65 sequentially reads out each signal stored in the memory 62 and outputs it.
- FIG. 14A it is possible to use two or more forces, each of which has only one band-variable duplex filter bank 61, frequency converter 63, and decimator 64.
- FIG. 15A is a block diagram in another embodiment of the digital signal multiplexing device.
- the digital signal multiplexer includes a parallel-serial converter 71, a band-variable two-multiplex filter bank 72, a memory 73, an interpolator 74, a frequency converter 75, and a time-division operation controller 76.
- the band-variable two-multiplex filter bank 72 includes upsamplers 701 and 702, a variable low-pass filter 703, a variable high-pass filter 704, and a calorimeter 705. It is out. [0064] Similar to the variable low-pass filter 601 in Fig.
- variable low-pass filter 703 can switch the filter A or filter C in Fig. 4 based on the control from the time-division operation control unit 76.
- variable high-pass filter 704 can switch the filter B or the filter D in FIG. 4 based on the control from the time division operation control unit 76.
- the up-samplers 701 and 702 have a function of converting the sampling frequency to 2 times by interpolating a sample value of 0 between each sample value of the input digital signal. Based on the control of the time division operation control unit 76, the input signal is converted into a signal having a predetermined frequency, and the interpolator 74 is the same as FIG. 12B.
- the same processing as that in FIGS. 11, 12A, and 12B is executed in a time-sharing manner by using the memory 73. It is said. That is, the input digital signals S41 and S42 are stored in the memory 73, and the band variable two-multiplex filter bank 72 is configured in the same manner as the two-multiplex filter bank 41 in FIG. 11 to multiplex the digital signals S41 and S42.
- the output signal is stored in the memory 73.
- the signal S36 is processed by the interpolator 74 and stored in the memory 73. Then, the frequency shift amount of the frequency change ⁇ 75 is set as shown in FIG.
- the signal processed by the interpolator 74 is read from the memory 73 and frequency conversion is performed.
- a plurality of input signals are converted into serial data and stored in the memory 73, and the time division operation control unit 76 controls each unit for the time division processing.
- the time division operation control unit 76 controls each unit for the time division processing.
- FIG. 15A it is possible to use two or more forces, each having only one band-variable two-multiplex filter bank 72, interpolator 74, and frequency converter 75.
- digital signal demultiplexing and Z or multiplexing are processed in a time-sharing manner, so that the digital signal demultiplexing and Z or multiplexing can be performed and used with a small circuit configuration. It can respond flexibly to changes in signal combinations.
- a digital signal demultiplexing device that demultiplexes and outputs a reception signal composed of a plurality of frequency-multiplexed signals.
- the digital signal demultiplexer includes one or more filters that filter the input signal and the output of each filter.
- a demultiplexing filter bank means including a configuration in which unit demultiplexing filter banks each having a down sampler that down-samples and outputs a force signal are connected in multiple stages; and a received signal and an output signal of each unit demultiplexing filter bank Frequency conversion 'decimator means having at least one input, and the frequency conversion' decimator means shifts the frequency of the input signal and outputs the frequency conversion means for each input signal, and each frequency conversion means Decimator means connected in series to one or more outputs, the decimator means includes a filter for limiting the bandwidth of the input signal and a downsambler for downsampling and outputting the output signal of the filter.
- the digital signal demultiplexing device may further include a switch matrix unit that selects and outputs one or more output signals from each unit demultiplexing filter bank and each decimator means.
- the switch matrix means can flexibly change the band and frequency arrangement of the signal used.
- the frequency shift amount in the frequency conversion means may be variable.
- the configuration of the frequency conversion interpolator means can be simplified.
- the digital signal demultiplexing device at least one of the frequency conversion means, the decimator means, and the unit demultiplexing filter bank is subjected to time division processing using a memory that stores input / output signals of each means. It may be realized. By realizing each means by time-division processing using a memory, the circuit scale can be further reduced.
- the frequency converting means is one of the plurality of signals included in the received signal that cannot pass through the pass band of the demultiplexing filter bank means. It is also possible to shift the frequency so that it falls within the passband of the decimator means connected in series!
- the unit demultiplexing filter bank down-samples and outputs one or two filters for filtering the input signal and the output signal of each filter. It may be a 2nd demultiplexer filter bank equipped with a down samba
- the sampling frequency of the input signal is set to fs.
- the bank includes a first two-demultiplexing filter bank with a first filter and / or a second filter, and a second two-demultiplexing filter bank with a third filter and / or a fourth filter.
- the down-sampled signal filtered by the first filter or the third filter is sent to the first de-multiplex filter bank.
- the signal is filtered by the second filter or the fourth filter and the down-sampled signal is connected to the second half-band filter bank.
- Plastic is also preferred that the sampling frequency to 1 Z2.
- a digital signal multiplexer that frequency-multiplexes and outputs a plurality of input signals.
- the digital signal multiplexing apparatus includes unit multiplexing that includes one or more up-samplers that up-sample and output an input signal, and a filter that removes unnecessary components from the output signal of each up-sampler for output.
- a filter bank means including a configuration in which filter banks are connected in multiple stages, and a frequency conversion interpolator means for outputting at least one signal to be added to any of the output signals of the unit filter bank
- the frequency conversion 'interpolator means includes a combination of one or more interpolator means connected in series and a frequency conversion means for shifting and outputting the frequency of the signal output from the last interpolator means by the number of output signals.
- the interpolator means includes an upsampler that upsamples and outputs the input signal, and an output from the upsampler. And a filter for outputting to remove unwanted signal components of the signal.
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Abstract
Description
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US12/296,758 US7936742B2 (en) | 2006-05-19 | 2007-05-18 | Digital signal demultiplexing device and multiplexing device |
CA2649007A CA2649007C (en) | 2006-05-19 | 2007-05-18 | Digital signal demultiplexing apparatus and multiplexing apparatus |
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JP2006-140361 | 2006-05-19 | ||
JP2006140361A JP2007312200A (ja) | 2006-05-19 | 2006-05-19 | ディジタル信号分波装置及び合波装置 |
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US (1) | US7936742B2 (ja) |
JP (1) | JP2007312200A (ja) |
CA (1) | CA2649007C (ja) |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2008050766A1 (fr) * | 2006-10-24 | 2008-05-02 | Nippon Telegraph And Telephone Corporation | Dispositif de démultiplexage de signal numérique et dispositif de multiplexage de signaux numériques |
WO2010064485A1 (ja) * | 2008-12-01 | 2010-06-10 | 三菱電機株式会社 | 分波装置、合波装置、通信装置および中継衛星 |
WO2011065287A1 (ja) * | 2009-11-30 | 2011-06-03 | 三菱電機株式会社 | 分波装置、合波装置および中継装置 |
WO2012026417A1 (ja) * | 2010-08-25 | 2012-03-01 | 三菱電機株式会社 | 分波装置、合波装置および中継装置 |
Families Citing this family (4)
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KR20090058948A (ko) * | 2007-12-05 | 2009-06-10 | 한국전자통신연구원 | 혼성신호 다중화를 이용한 광 다이플렉서 모듈 및 그 방법 |
CA2843833C (en) | 2011-09-26 | 2016-06-14 | Nippon Telegraph And Telephone Corporation | Communication system, transmitter apparatus and receiver apparatus |
JP5889145B2 (ja) * | 2012-09-05 | 2016-03-22 | 三菱電機株式会社 | 分波装置、合波装置および中継装置 |
JP6745973B2 (ja) * | 2017-03-06 | 2020-08-26 | 三菱電機株式会社 | 分波回路、合波回路、およびチャネライザ中継器 |
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JP2008109258A (ja) * | 2006-10-24 | 2008-05-08 | Nippon Telegr & Teleph Corp <Ntt> | ディジタル信号分波装置及びディジタル信号合波装置 |
WO2008050766A1 (fr) * | 2006-10-24 | 2008-05-02 | Nippon Telegraph And Telephone Corporation | Dispositif de démultiplexage de signal numérique et dispositif de multiplexage de signaux numériques |
US8036100B2 (en) | 2006-10-24 | 2011-10-11 | Nippon Telegraph And Telephone Corporation | Digital signal demultiplexing apparatus and digital signal multiplexing apparatus |
US8611204B2 (en) | 2006-10-24 | 2013-12-17 | Nippon Telegraph And Telephone Corporation | Digital signal multiplexing apparatus |
US8675628B2 (en) | 2008-12-01 | 2014-03-18 | Mitsubishi Electric Corporation | Demultiplexing apparatus, multiplexing apparatus, communication apparatus, and relay satellite |
WO2010064485A1 (ja) * | 2008-12-01 | 2010-06-10 | 三菱電機株式会社 | 分波装置、合波装置、通信装置および中継衛星 |
EP2372931A4 (en) * | 2008-12-01 | 2017-08-02 | Mitsubishi Electric Corporation | Multiplexer, demultiplexer, communication device, and relay satellite |
JP5106641B2 (ja) * | 2008-12-01 | 2012-12-26 | 三菱電機株式会社 | 分波装置、合波装置、通信装置および中継衛星 |
WO2011065287A1 (ja) * | 2009-11-30 | 2011-06-03 | 三菱電機株式会社 | 分波装置、合波装置および中継装置 |
US8731123B2 (en) | 2009-11-30 | 2014-05-20 | Mitsubishi Electric Corporation | Demultiplexing device, multiplexing device, and relay device |
JP5575149B2 (ja) * | 2009-11-30 | 2014-08-20 | 三菱電機株式会社 | 分波装置、合波装置および中継装置 |
JP5579273B2 (ja) * | 2010-08-25 | 2014-08-27 | 三菱電機株式会社 | 分波装置、合波装置および中継装置 |
US9136933B2 (en) | 2010-08-25 | 2015-09-15 | Mitsubishi Electric Corporation | Demultiplexing apparatus, multiplexing apparatus, and relay apparatus |
WO2012026417A1 (ja) * | 2010-08-25 | 2012-03-01 | 三菱電機株式会社 | 分波装置、合波装置および中継装置 |
Also Published As
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US20090304031A1 (en) | 2009-12-10 |
CA2649007C (en) | 2012-03-13 |
US7936742B2 (en) | 2011-05-03 |
CA2649007A1 (en) | 2007-11-29 |
JP2007312200A (ja) | 2007-11-29 |
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