WO2007087660A1 - Élément de carte de circuits imprimés dans lequel est noyé au moins un composant, et procédé pour noyer au moins un composant dans un élément de carte de circuits imprimés - Google Patents

Élément de carte de circuits imprimés dans lequel est noyé au moins un composant, et procédé pour noyer au moins un composant dans un élément de carte de circuits imprimés Download PDF

Info

Publication number
WO2007087660A1
WO2007087660A1 PCT/AT2007/000045 AT2007000045W WO2007087660A1 WO 2007087660 A1 WO2007087660 A1 WO 2007087660A1 AT 2007000045 W AT2007000045 W AT 2007000045W WO 2007087660 A1 WO2007087660 A1 WO 2007087660A1
Authority
WO
WIPO (PCT)
Prior art keywords
component
adhesive
adhesive film
circuit board
printed circuit
Prior art date
Application number
PCT/AT2007/000045
Other languages
German (de)
English (en)
Inventor
Arno Kriechbaum
Wolfgang Bauer
Johannes Stahr
Sabine Liebfahrt
Original Assignee
At & S Austria Technologie & Systemtechnik Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & S Austria Technologie & Systemtechnik Aktiengesellschaft filed Critical At & S Austria Technologie & Systemtechnik Aktiengesellschaft
Priority to AT07701291T priority Critical patent/ATE541314T1/de
Priority to CA002650700A priority patent/CA2650700A1/fr
Priority to EP07701291A priority patent/EP2027600B1/fr
Priority to EP10177700.1A priority patent/EP2259311B1/fr
Priority to US12/162,016 priority patent/US20110051384A1/en
Publication of WO2007087660A1 publication Critical patent/WO2007087660A1/fr

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401Structure
    • H01L2224/2402Laminated, e.g. MCM-L type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405Shape
    • H01L2224/24051Conformal with the semiconductor or solid-state device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436Lamination of a preform, e.g. foil, sheet or layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • H01L2224/82035Reshaping, e.g. forming vias by heating means
    • H01L2224/82039Reshaping, e.g. forming vias by heating means using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12033Gunn diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0191Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Definitions

  • Printed circuit board element with at least one embedded component and method for embedding at least one component in a printed circuit board element
  • the invention relates to a printed circuit board element with at least one embedded between a base and a cover layer, prefabricated electrical or electronic component, in particular a chip.
  • the invention relates to a method for embedding at least one electrical or electronic component, in particular a chip (semiconductor device), in a printed circuit board element, wherein the component is adhered to a pad, after which a cover layer is attached by pressing over the pad together with the component ,
  • a chip semiconductor device
  • a substrate layer for example, by injection molding or pressing, is attached to the adhesive layer and formed around the chip, so that finally the chip between this substrate and the connection layer, through which the chip is contacted, is embedded.
  • a similar application of chips to substrates by means of an adhesive layer is disclosed in DE 4 433 833 A, EP 611 129 A and US 5 564 181 A. This technology is expensive, with the surface applied adhesive layer as an additional layer, which is also present outside of the chips, disturbing. - -
  • the invention provides a printed circuit board element or a method as defined in the independent claims before.
  • Advantageous embodiments and further developments are specified in the subclaims. , __ T2007 / 000045
  • Klebef ⁇ lienab songs are used to attach the components to the respective documents by gluing.
  • These sections are separated from prefabricated, in particular band-shaped, preferably in roll form adhesive films, such as by cutting or punching, and they have a predetermined uniform thickness, for example in the order of 10 microns to 15 microns, preferably having a thickness of about 12 .mu.m.
  • These adhesive films or tapes are in particular thermosetting, wherein the adhesive, for example, after separate attachment of the respective section on the substrate by infrared radiation precured and finally, after attachment of the device, in a final oven can be completely cured.
  • the adhesive sheet sections are separated substantially with the dimensions of the components, e.g.
  • the adhesive film sections are pressed during positioning after positioning and, if appropriate, also pre-cured to a certain extent by using a heated tool.
  • a heated tool One possibility may further be that the adhesive film portions are applied to the backing and pressed, the backing being heated from the opposite side so as to cure the adhesive sheet portions to a limited extent, i. precure, where appropriate, the components are heated.
  • pre-curing is to adhere the adhesive film portion to the substrate sufficiently firmly, but the adhesive film portion should still remain sufficiently tacky to subsequently adhere the respective component by pressing.
  • the particular tape-shaped adhesive films may have a conventional structure, such as a structure with a carrier film which is coated on both sides with an adhesive, which in turn can be attached over these adhesive layers cover films. Another possibility is to omit the carrier film and only one adhesive layer, for example, also between two cover sheets to provide.
  • the carrier film allows for an increase in stability, and may be made of polyimide, for example consist.
  • polyimide for example consist.
  • polyethylene films or polyethylene terephthalate films (PE films or PET films) can be used as cover films.
  • a per se conventional polymeric adhesive such as low modulus of elasticity, preferably in combination with an epoxy resin and fillers used.
  • a modified polyimide may be used in combination with epoxy resin.
  • the procedure is preferably such that the one, lower cover film, e.g. a PE film is peeled off before mounting the adhesive sheet portion on the base so as to adhere the adhesive sheet portion to the base, and that the other upper cover sheet, e.g. a PET film is pulled off just before attaching the device, so as to protect the adhesive layer until then.
  • the one, lower cover film e.g. a PE film
  • the other upper cover sheet e.g. a PET film
  • An advantageous possibility is also to install the adhesive film sections in advance on the component at its side to be joined to the substrate and thus to tack the respective component together with the adhesive film section together on the substrate.
  • the pad together with glued component is expediently introduced into an oven and, for example, heated to a temperature of 130 0 C to 150 0 C or 170 0 C. It may also be advantageous to carry out this complete curing of the adhesive in a reactive or inert atmosphere, in particular in a nitrogen atmosphere.
  • a resin-copper cover layer can be applied over the base with component by pressing, such as a so-called RCC film (RCC - Resin Coated Copper foil - resin-coated copper foil). , and after that can contact holes through 7 000045
  • Fig. 1 shows schematically a cross-section through a part of a multilayer printed circuit board element with an embedded component, e.g. a thinned chip;
  • FIGS. 2A to 2E show, in schematic partial cross-sections, successive steps in the production of such a printed circuit board element with the embedding of a component
  • FIG. 3 is a diagrammatic view of side-by-side different possibilities for mounting a component on a base of a printed circuit board element
  • FIG. 3A shows a schematic section through an embodiment of an adhesive film section
  • FIG. 4A to 4C show an advantageous possibility of applying a wide tape-shaped adhesive sheet material on a chip wafer (FIG. 4A) and dividing the wafer together with adhesive film into chips having adhesive sheet sections (FIG. 4B) and attaching the chips together with the adhesive sheet sections fixed thereto on a substrate or pad of a printed circuit board element ( Figure 4C); and
  • FIG. 5A to 5D show a modified embodiment of the method for mounting chips (or generally devices) on a substrate using adhesive sheet sections, the sections being cut off in advance from an adhesive tape, either by means of a cutting tool (FIG. 5A). or by means of a punching tool (Fig. 5D), then separately mounted on the backing (Fig. 5B), and finally the chips are adhered to these adhesive sheet portions (Fig. 5C).
  • FIG. 1 schematically shows a part of a printed circuit board element 1 which contains an embedded electrical component in the form of a thinned chip 2.
  • passive components such as resistors, capacitors, ESD (Electro Static Discharge - electrostatic discharge ) -Guide elements, laser diodes, photodiodes, etc.
  • These are discrete components, wherein preferably the thickness of these components - either from the outset, by the manufacturing process, such as in capacitors, or by subsequent back thinning, about 50 ⁇ m to 70 ⁇ m.
  • Such thin components can be used in embedding, e.g. for protection against moisture or mechanical stress, be securely enclosed by the resin, in which case a corresponding dielectric thickness is present over the component and a flat surface is achieved. This is important on the one hand for laser drilling processes, but also for other processes that require a flat surface.
  • the device or the chip 2 is by means of a portion 3 of a tape-shaped adhesive film, hereafter called adhesive film section 3, on a base 4, for example a conventional FR4 base material (resin core, in particular with conductor layer) or substrate, as in the printed circuit board technology in conventional Way is used, glued.
  • adhesive film section 3 a tape-shaped adhesive film, hereafter called adhesive film section 3, on a base 4, for example a conventional FR4 base material (resin core, in particular with conductor layer) or substrate, as in the printed circuit board technology in conventional Way is used, glued.
  • the circuit board element 1 can accordingly on the pad 4 in a conventional manner a conductor 5, for example in the form of a structured Cu layer, which leads to unspecified further electrical components in the printed circuit board element 1; Over this conductor 5 and over the chip 2, a cover layer 6 made of resin with an upper copper coating 7 is attached, which may be, for example, a conventional RCC film (Resin Coated Copper foil, ie a resin-copper foil laminate) , 2007/000045
  • this cover layer 6 further laser holes or micro-vias 8, 9 are provided for contacting the chip 2 and the conductor strip 5, which have on the side walls a galvanic metallization 10 and 11 respectively.
  • FIG. 2A shows in detail the attachment of a component or a chip 2 on such a base 4.
  • the pad 4 i. at the circuit board core, in a region 12, in advance, an exposure in the conductive coating, i. in the conductor 5, provided, and in this area 12 has already been an adhesive tape section 3 is positioned and adhered under pressing and also pre-cured to a predetermined extent, so that its liability to the pad 4 is ensured.
  • the chip 2 is now by pressing, as shown by the arrow 13, attached and glued.
  • the glued state of the chip 2 can be seen in the lower part of FIG. 2B.
  • the chip 2 further has contact areas 14, 15 at its upper side, which are later contacted via the laser bores 8 already mentioned with reference to FIG. 1 through the cover layer 6.
  • the pad 4 After attaching the adhesive tape portion 3 on the circuit board pad 4 and the chip 2 on the tape portion 3, as mentioned, the pad 4, preferably on a panel with a variety of similarly populated printed circuit board substrates placed in an oven to the adhesive completely cure. This can be done in a reactive or inert atmosphere, e.g. Nitrogen, happen.
  • a reactive or inert atmosphere e.g. Nitrogen
  • the bores 8, 9 for contacting the internal components, in particular chips 2, and conductor tracks 5 are then produced with the aid of laser beams; the result of this process step is shown in Fig. 2C.
  • an attachment of the contact points 14, 15 of the components 2 and the conductor tracks 5 in the interior of the multilayer is effected by galvanic metallization, the walls of the bores 8, 9 being covered with copper that the metallizations 10, 11 are obtained.
  • the upper copper layer 7 is patterned using a conventional photolithographic process, so that finally the printed circuit board element 1, as shown in Fig. 2E dar- is received.
  • FIG. 3 three different possibilities for a component fastening by means of adhesive film sections 3 are indicated schematically and for the sake of simplicity side by side in connection with a single substrate core as base 4.
  • an adhesive film portion 3 which consists only of adhesive material, wherein any lower and upper cover sheets have already been deducted, was positioned in advance on the base 4, pressed and pre-cured. Thereafter, a component 2, which is held by means of vacuum on the tool 17, brought computer-controlled in position and pressed according to the arrow 13 (see also Fig. 2A) on the adhesive film section 3 with the aid of a tempered stamp-suction tool 17.
  • the thin or thinned component 2 may for example have a thickness of the order of only about 50 ⁇ m, cf. the dimension D in Fig. 3, and the adhesive film portion 3 may for example have a thickness d on the order of only 8 ⁇ m to 15 ⁇ m.
  • FIG. 3 A comparable attachment of a thinned or thin component 2 by means of a tool 17 is illustrated in the middle part of FIG. 3, but here an adhesive film portion 3 is shown which has a carrier film 3a between two adhesive layers 3b, 3c, cf. otherwise Fig. 3A.
  • this adhesive film section 3 may have a lower cover film 3d and an upper cover film 3e, as illustrated in FIG. 3A, these cover films 3d, 3e being removed during the application of the adhesive film section 3 or the component 2, as shown schematically in FIG Fig. 3A is indicated.
  • the lower cover layer 3d is withdrawn, after which the adhesive film section 3 is pressed onto the circuit board pad 4 as the first.
  • the upper cover film 3e is preferably removed only immediately before the attachment of the component 2 so as to protect the upper adhesive layer 3c as long as possible.
  • a thickness between, for example, 10 .mu.m and 50 .mu.m (without cover films) may be given, while an adhesive film section with adhesive layers 3b, 3c on both sides of a carrier film 3a may well be somewhat thicker, about 12 .mu.m to 200 .mu.m thick.
  • the upper cover film can for example consist of PET and have a thickness of 50 .mu.m, whereas the lower, first deducted cover sheet of PE material and may have a thickness of 25 microns.
  • the adhesive material is a polymeric Adhesiv combination, which may also contain epoxy resin, and which may be prepared, for example, based on a modified Polyixnids or a polymer with low modulus of elasticity.
  • FIGS. 4A, 4B and 4C Such prior attachment of adhesive foil sections 3 to the components 2 is advantageously obtained when, as shown in FIGS. 4A, 4B and 4C, a correspondingly wide adhesive tape, i. tape-shaped adhesive sheet material 19 is attached to the underside of a wafer 18 containing a plurality of chips 2 or the like.
  • FIG. 4A also schematically indicates at 20 how the adhesive film material 19 is laminated to the wafer 18 after removal of any lower PE cover film with the aid of a roll.
  • the upper PET cover film which then comes to lie on the underside during the attachment according to the representation in FIG. 3 on the right side, can likewise be removed immediately or only immediately before the chips 2 are mounted on the printed circuit board substrate 4.
  • the wafer 18 is subdivided into the individual chips 2, which is indicated very schematically with the aid of a cutting tool 21. 7 000045
  • the chips 2 with the adhesive film sections 3 thus obtained directly on the underside of the chips 2 are mounted on the printed circuit board substrate 4, for which purpose the tempered suction tool 17 already explained with reference to FIG. 3 can be used.
  • the pad 4 can be heated from the underside with the aid of a heating block 22, as well as the application of the adhesive film material 19 on the wafer 18 as shown in FIG. 4A a heated block 23, which is maintained for example at a temperature of about 8O 0 C. , Can be used so as to already partially harden the adhesive material.
  • FIGS. 5A to 5D illustrate, as an alternative to FIGS. 4A to 4C, a technique in which, by means of a cutting tool 24, the individual adhesive film sections 3 are cut off from a tape-shaped adhesive film material 19, for example by means of a cutting tool 24.
  • the one cover film namely the PE cover film
  • the individual adhesive film sections 3 are cut and applied with the aid of the tool 17 to the printed circuit board substrate 4, cf.
  • Fig. 5B wherein the circuit board pad 4 can in turn rest on a heated block 22 so as to already provisionally cure the adhesive material of the adhesive film sections 3 to a certain extent.
  • a punching tool 25 can be used for punching out and directly pressing the adhesive film sections 3 onto the base 4.
  • the pad 4 can rest on a modified heating block 22 ', which is maintained for example at a temperature of 140 0 C.
  • any top PET cover sheet is peeled off from the adhesive sheet portions 3.
  • the adhesive sheet material 19 may be as in FIGS. 4A or 5A or 5D T2007 / 000045
  • this pad Before attaching the adhesive film sections 3 (or the component 2 together with the previously attached to them adhesive film sections 3) on the base 4, this pad can also be irradiated with an infrared lamp in the mounting positions and preheated, the heating time depending on the power of the infrared lamp 10th can be up to 20 seconds.
  • the force applied when the adhesive film sections 3 or the components 2 were pressed was 37N in tests.
  • the curing temperature for the adhesive of the adhesive film sections 3 was 150 0 C and 17O 0 C.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Details Of Resistors (AREA)

Abstract

La présente invention concerne un élément de carte de circuits imprimés (1) comprenant au moins un composant (2) noyé entre une couche de base (4) et une couche de recouvrement (6) et collé sur la couche de base (4) au moyen d'une section de film adhésif (3).
PCT/AT2007/000045 2006-02-02 2007-02-01 Élément de carte de circuits imprimés dans lequel est noyé au moins un composant, et procédé pour noyer au moins un composant dans un élément de carte de circuits imprimés WO2007087660A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AT07701291T ATE541314T1 (de) 2006-02-02 2007-02-01 Verfahren zum einbetten zumindest eines bauelements in einem leiterplattenelement
CA002650700A CA2650700A1 (fr) 2006-02-02 2007-02-01 Element de carte de circuits imprimes comprenant au moins un element integre, et procede d'integration
EP07701291A EP2027600B1 (fr) 2006-02-02 2007-02-01 Procédé pour noyer au moins un composant dans un élément de carte de circuits imprimés
EP10177700.1A EP2259311B1 (fr) 2006-02-02 2007-02-01 Procédé d'encastrement d'au moins un composant dans un élément de plaquettes
US12/162,016 US20110051384A1 (en) 2006-02-02 2007-02-02 Printed circuit board element having at least one component embedded therein and method for embedding at least one component in a printed circuit board element

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ATA160/2006 2006-02-02
AT0016006A AT503191B1 (de) 2006-02-02 2006-02-02 Leiterplattenelement mit wenigstens einem eingebetteten bauelement sowie verfahren zum einbetten zumindest eines bauelements in einem leiterplattenelement

Publications (1)

Publication Number Publication Date
WO2007087660A1 true WO2007087660A1 (fr) 2007-08-09

Family

ID=38110689

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AT2007/000045 WO2007087660A1 (fr) 2006-02-02 2007-02-01 Élément de carte de circuits imprimés dans lequel est noyé au moins un composant, et procédé pour noyer au moins un composant dans un élément de carte de circuits imprimés

Country Status (6)

Country Link
US (1) US20110051384A1 (fr)
EP (2) EP2027600B1 (fr)
AT (2) AT503191B1 (fr)
CA (1) CA2650700A1 (fr)
FR (1) FR2896947A1 (fr)
WO (1) WO2007087660A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009143550A1 (fr) * 2008-05-30 2009-12-03 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé pour intégrer au moins un composant électronique dans un circuit imprimé et circuit imprimé
WO2014005167A1 (fr) 2012-07-02 2014-01-09 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé permettant d'intégrer au moins un composant dans une carte de circuit imprimé
US10187997B2 (en) 2014-02-27 2019-01-22 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
US10219384B2 (en) 2013-11-27 2019-02-26 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Circuit board structure
US10779413B2 (en) 2013-12-12 2020-09-15 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method of embedding a component in a printed circuit board
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8389862B2 (en) 2008-10-07 2013-03-05 Mc10, Inc. Extremely stretchable electronics
US8097926B2 (en) 2008-10-07 2012-01-17 Mc10, Inc. Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy
JP5646492B2 (ja) 2008-10-07 2014-12-24 エムシー10 インコーポレイテッドMc10,Inc. 伸縮可能な集積回路およびセンサアレイを有する装置
US9123614B2 (en) 2008-10-07 2015-09-01 Mc10, Inc. Methods and applications of non-planar imaging arrays
WO2011041727A1 (fr) 2009-10-01 2011-04-07 Mc10, Inc. Boîtiers protecteurs avec des circuits électroniques intégrés
WO2012166686A2 (fr) 2011-05-27 2012-12-06 Mc10, Inc. Appareil électronique, optique et/ou mécanique et systèmes et procédés pour le fabriquer
US9757050B2 (en) 2011-08-05 2017-09-12 Mc10, Inc. Catheter balloon employing force sensing elements
JP6320920B2 (ja) 2011-08-05 2018-05-09 エムシーテン、インコーポレイテッド センシング素子を利用したバルーン・カテーテルの装置及び製造方法
US9226402B2 (en) 2012-06-11 2015-12-29 Mc10, Inc. Strain isolation structures for stretchable electronics
EP2866645A4 (fr) 2012-07-05 2016-03-30 Mc10 Inc Dispositif cathéter comprenant un détecteur de débit
US9295842B2 (en) 2012-07-05 2016-03-29 Mc10, Inc. Catheter or guidewire device including flow sensing and use thereof
JP2016500869A (ja) 2012-10-09 2016-01-14 エムシー10 インコーポレイテッドMc10,Inc. 衣類と一体化されたコンフォーマル電子回路
US9171794B2 (en) 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
US9706647B2 (en) 2013-05-14 2017-07-11 Mc10, Inc. Conformal electronics including nested serpentine interconnects
CA2920485A1 (fr) 2013-08-05 2015-02-12 Mc10, Inc. Capteur de temperature souple comprenant des composants electroniques conformables
CA2925387A1 (fr) 2013-10-07 2015-04-16 Mc10, Inc. Systemes de detection et d'analyse a capteurs conformes
CN105813545A (zh) 2013-11-22 2016-07-27 Mc10股份有限公司 用于感测和分析心搏的适形传感器系统
CN105874606B (zh) 2014-01-06 2021-01-12 Mc10股份有限公司 包封适形电子系统和器件及其制作和使用方法
CA2940539C (fr) 2014-03-04 2022-10-04 Mc10, Inc. Boitier d'encapsulation souple en plusieurs parties pour dispositifs electroniques
US9899330B2 (en) * 2014-10-03 2018-02-20 Mc10, Inc. Flexible electronic circuits with embedded integrated circuit die
US10297572B2 (en) 2014-10-06 2019-05-21 Mc10, Inc. Discrete flexible interconnects for modules of integrated circuits
USD781270S1 (en) 2014-10-15 2017-03-14 Mc10, Inc. Electronic device having antenna
DE102014226773A1 (de) * 2014-12-22 2016-06-23 Robert Bosch Gmbh Verfahren zum elektrischen Kontaktieren eines Bauteils und Bauteileverbund
EP3258837A4 (fr) 2015-02-20 2018-10-10 Mc10, Inc. Détection et configuration automatiques de dispositifs à porter sur soi sur la base d'un état, d'un emplacement et/ou d'une orientation sur le corps
WO2016140961A1 (fr) 2015-03-02 2016-09-09 Mc10, Inc. Capteur de transpiration
WO2017015000A1 (fr) 2015-07-17 2017-01-26 Mc10, Inc. Raidisseur conducteur, procédé de fabrication d'un raidisseur conducteur, ainsi qu'adhésif conducteur et couches d'encapsulation
US10709384B2 (en) 2015-08-19 2020-07-14 Mc10, Inc. Wearable heat flux devices and methods of use
EP4079383A3 (fr) 2015-10-01 2023-02-22 Medidata Solutions, Inc. Procédé et système permettant d'interagir avec un environnement virtuel
US10532211B2 (en) 2015-10-05 2020-01-14 Mc10, Inc. Method and system for neuromodulation and stimulation
EP3829187A1 (fr) 2016-02-22 2021-06-02 Medidata Solutions, Inc. Système, dispositifs et procédé pour l'émission de données et d'énergie sur le corps
CN108781313B (zh) 2016-02-22 2022-04-08 美谛达解决方案公司 用以贴身获取传感器信息的耦接的集线器和传感器节点的系统、装置和方法
WO2017184705A1 (fr) 2016-04-19 2017-10-26 Mc10, Inc. Procédé et système de mesure de transpiration
US10447347B2 (en) 2016-08-12 2019-10-15 Mc10, Inc. Wireless charger and high speed data off-loader
KR102454815B1 (ko) * 2018-02-21 2022-10-17 삼성전자주식회사 브라켓과 용량성 결합을 형성하고, 상기 브라켓에 배치된 복수의 회로 기판들의 접지부들과 전기적으로 연결된 도전성 부재를 포함하는 전자 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3521528A1 (de) * 1985-06-15 1986-12-18 SWF Auto-Electric GmbH, 7120 Bietigheim-Bissingen Anzeigeeinrichtung mit einer elektrooptischen zelle
DE19954941A1 (de) * 1999-11-16 2001-06-13 Fraunhofer Ges Forschung Verfahren zum Integrieren eines Chips innerhalb einer Leiterplatte
FR2857157A1 (fr) * 2003-07-01 2005-01-07 3D Plus Sa Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant
WO2005015488A1 (fr) * 2003-07-28 2005-02-17 Infineon Technologies Ag Carte a puce, module de cartes a puce, et procede de fabrication d'un module de cartes a puce

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
DE4433833A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung unter Erreichung hoher Systemausbeuten
US5564181A (en) 1995-04-18 1996-10-15 Draper Laboratory, Inc. Method of fabricating a laminated substrate assembly chips-first multichip module
DE19642488A1 (de) 1996-10-15 1998-04-16 Bernd Klose Verfahren zur Kontaktierung von Mikrochips und zur Herstellung von Mehrlagen-Dünnschichtleiterplatten, insbesondere für superflache Multichip-Modul- und Chipcard-Anwendungen
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
JP2001135653A (ja) * 1999-11-02 2001-05-18 Mitsubishi Electric Corp ダイボンディング装置及び半導体装置
JP2003097418A (ja) * 2001-07-18 2003-04-03 Denso Corp 圧電体素子の変位伝達構造
KR100415282B1 (ko) * 2002-02-06 2004-01-16 삼성전자주식회사 반도체 소자용 듀얼 다이 접착 장치
DE10343053A1 (de) * 2003-09-16 2005-04-07 Siemens Ag Elektronisches Bauelement und Anordnung mit einem elektronischen Bauelement

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3521528A1 (de) * 1985-06-15 1986-12-18 SWF Auto-Electric GmbH, 7120 Bietigheim-Bissingen Anzeigeeinrichtung mit einer elektrooptischen zelle
DE19954941A1 (de) * 1999-11-16 2001-06-13 Fraunhofer Ges Forschung Verfahren zum Integrieren eines Chips innerhalb einer Leiterplatte
FR2857157A1 (fr) * 2003-07-01 2005-01-07 3D Plus Sa Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant
WO2005015488A1 (fr) * 2003-07-28 2005-02-17 Infineon Technologies Ag Carte a puce, module de cartes a puce, et procede de fabrication d'un module de cartes a puce

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009143550A1 (fr) * 2008-05-30 2009-12-03 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé pour intégrer au moins un composant électronique dans un circuit imprimé et circuit imprimé
AT10247U3 (de) * 2008-05-30 2013-04-15 Austria Tech & System Tech Verfahren zur integration wenigstens eines elektronischen bauteils in eine leiterplatte sowie leiterplatte
JP2014090201A (ja) * 2008-05-30 2014-05-15 At & S Austria Technologie & Systemtechnik Aktiengesellschaft 少なくとも1つの電子構成部品をプリント回路基板に組み込むための方法、およびプリント回路基板
US8789271B2 (en) 2008-05-30 2014-07-29 AT & S Austria Technologies & Systemtechnik Aktiengesellschaft Method for integrating an electronic component into a printed circuit board
WO2014005167A1 (fr) 2012-07-02 2014-01-09 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé permettant d'intégrer au moins un composant dans une carte de circuit imprimé
AT513047B1 (de) * 2012-07-02 2014-01-15 Austria Tech & System Tech Verfahren zum Einbetten zumindest eines Bauteils in eine Leiterplatte
AT513047A4 (de) * 2012-07-02 2014-01-15 Austria Tech & System Tech Verfahren zum Einbetten zumindest eines Bauteils in eine Leiterplatte
US10219384B2 (en) 2013-11-27 2019-02-26 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Circuit board structure
US11172576B2 (en) 2013-11-27 2021-11-09 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for producing a printed circuit board structure
US10779413B2 (en) 2013-12-12 2020-09-15 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method of embedding a component in a printed circuit board
US10187997B2 (en) 2014-02-27 2019-01-22 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board

Also Published As

Publication number Publication date
ATE541314T1 (de) 2012-01-15
CA2650700A1 (fr) 2007-08-09
EP2027600A1 (fr) 2009-02-25
US20110051384A1 (en) 2011-03-03
AT503191A1 (de) 2007-08-15
EP2259311B1 (fr) 2018-07-25
EP2259311A2 (fr) 2010-12-08
AT503191B1 (de) 2008-07-15
FR2896947A1 (fr) 2007-08-03
EP2259311A3 (fr) 2014-01-15
EP2027600B1 (fr) 2012-01-11

Similar Documents

Publication Publication Date Title
EP2027600B1 (fr) Procédé pour noyer au moins un composant dans un élément de carte de circuits imprimés
DE112004001727B4 (de) Verfahren zur Herstellung eines elektronischen Moduls
EP2260683B1 (fr) Procédé de fabrication d'un module électronique
EP3081056A1 (fr) Procédé d'intégration d'un composant dans une carte à circuit imprimé
DE112008003532T5 (de) Verfahren zum Herstellen eines Mehrschichtverdrahtungssubstrats
EP2852970B1 (fr) Procédé de fabrication d'un module électronique
EP3231261A1 (fr) Carte de circuits imprimés à structure de couches asymétrique
EP2153707B1 (fr) Procédé de production d'un composant électronique
AT515443B1 (de) Verfahren zum Herstellen einer Leiterplatte sowie Leiterplatte
DE102016123129B4 (de) Elektronische Komponente und Verfahren
EP2421339A1 (fr) Procédé d'encastrement de composants électriques
EP2982226B1 (fr) Procédé de fabrication d'un élément de circuit imprimé
DE102008009220A1 (de) Verfahren zum Herstellen einer Leiterplatte
WO2021224204A1 (fr) Procédé de fabrication d'une carte de circuit imprimé et carte de circuit imprimé comprenant au moins un composant électronique intégré
DE202009009950U1 (de) Elektronische Baugruppe
DE102005017002A1 (de) Verfahren zur Herstellung einer räumlichen, wenigstens in einem Teilbereich gekrümmten Leiterplatte sowie nach diesem Verfahren hergestellte Leiterplatte
DE10210841B4 (de) Modul und Verfahren zur Herstellung von elektrischen Schaltungen und Modulen
EP3515157B1 (fr) Circuit électrique flexible pourvu de raccordement entre les éléments structuraux électriquement conducteurs
DE102018102734A1 (de) Flexible elektrische Schaltung mit Verbindung zwischen elektrisch leitfähigen Strukturelementen
WO2022243132A1 (fr) Procédé de fabrication d'une carte de circuit imprimé et carte de circuit imprimé comportant au moins un composant électronique intégré
DE102007015819A1 (de) Verfahren zur Herstellung einer elektronischen Baugruppe sowie elektronische Baugruppe
DE102006023168B4 (de) Herstellungsverfahren für eine elektronische Schaltung
DE102007036046A1 (de) Planares elektronisches Modul

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2650700

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 2007701291

Country of ref document: EP