EP2852970B1 - Procédé de fabrication d'un module électronique - Google Patents
Procédé de fabrication d'un module électronique Download PDFInfo
- Publication number
- EP2852970B1 EP2852970B1 EP12722392.3A EP12722392A EP2852970B1 EP 2852970 B1 EP2852970 B1 EP 2852970B1 EP 12722392 A EP12722392 A EP 12722392A EP 2852970 B1 EP2852970 B1 EP 2852970B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- film
- carrier
- adhesive
- component
- nanoparticles
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Not-in-force
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000853 adhesive Substances 0.000 claims description 57
- 230000001070 adhesive effect Effects 0.000 claims description 57
- 238000000034 method Methods 0.000 claims description 37
- 239000002105 nanoparticle Substances 0.000 claims description 31
- 238000009766 low-temperature sintering Methods 0.000 claims description 23
- 238000003475 lamination Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 17
- 238000001816 cooling Methods 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 239000004332 silver Substances 0.000 claims description 10
- 239000000945 filler Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- 229920000642 polymer Polymers 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229920000106 Liquid crystal polymer Polymers 0.000 claims description 5
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 230000002787 reinforcement Effects 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 3
- 229920001971 elastomer Polymers 0.000 claims description 2
- 239000000806 elastomer Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims 1
- 239000012815 thermoplastic material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 37
- 239000011888 foil Substances 0.000 description 8
- 239000002131 composite material Substances 0.000 description 7
- 239000004033 plastic Substances 0.000 description 7
- 239000007858 starting material Substances 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 6
- 230000000712 assembly Effects 0.000 description 5
- 238000000429 assembly Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229920001169 thermoplastic Polymers 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 239000000835 fiber Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- NOESYZHRGYRDHS-UHFFFAOYSA-N insulin Chemical compound N1C(=O)C(NC(=O)C(CCC(N)=O)NC(=O)C(CCC(O)=O)NC(=O)C(C(C)C)NC(=O)C(NC(=O)CN)C(C)CC)CSSCC(C(NC(CO)C(=O)NC(CC(C)C)C(=O)NC(CC=2C=CC(O)=CC=2)C(=O)NC(CCC(N)=O)C(=O)NC(CC(C)C)C(=O)NC(CCC(O)=O)C(=O)NC(CC(N)=O)C(=O)NC(CC=2C=CC(O)=CC=2)C(=O)NC(CSSCC(NC(=O)C(C(C)C)NC(=O)C(CC(C)C)NC(=O)C(CC=2C=CC(O)=CC=2)NC(=O)C(CC(C)C)NC(=O)C(C)NC(=O)C(CCC(O)=O)NC(=O)C(C(C)C)NC(=O)C(CC(C)C)NC(=O)C(CC=2NC=NC=2)NC(=O)C(CO)NC(=O)CNC2=O)C(=O)NCC(=O)NC(CCC(O)=O)C(=O)NC(CCCNC(N)=N)C(=O)NCC(=O)NC(CC=3C=CC=CC=3)C(=O)NC(CC=3C=CC=CC=3)C(=O)NC(CC=3C=CC(O)=CC=3)C(=O)NC(C(C)O)C(=O)N3C(CCC3)C(=O)NC(CCCCN)C(=O)NC(C)C(O)=O)C(=O)NC(CC(N)=O)C(O)=O)=O)NC(=O)C(C(C)CC)NC(=O)C(CO)NC(=O)C(C(C)O)NC(=O)C1CSSCC2NC(=O)C(CC(C)C)NC(=O)C(NC(=O)C(CCC(N)=O)NC(=O)C(CC(N)=O)NC(=O)C(NC(=O)C(N)CC=1C=CC=CC=1)C(C)C)CC1=CN=CN1 NOESYZHRGYRDHS-UHFFFAOYSA-N 0.000 description 2
- 239000013067 intermediate product Substances 0.000 description 2
- 239000004922 lacquer Substances 0.000 description 2
- 239000010985 leather Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000011253 protective coating Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229940100890 silver compound Drugs 0.000 description 2
- 150000003379 silver compounds Chemical class 0.000 description 2
- 239000004753 textile Substances 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 235000013311 vegetables Nutrition 0.000 description 2
- 239000005749 Copper compound Substances 0.000 description 1
- 240000005702 Galium aparine Species 0.000 description 1
- 102000004877 Insulin Human genes 0.000 description 1
- 108090001061 Insulin Proteins 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- QXJJQWWVWRCVQT-UHFFFAOYSA-K calcium;sodium;phosphate Chemical compound [Na+].[Ca+2].[O-]P([O-])([O-])=O QXJJQWWVWRCVQT-UHFFFAOYSA-K 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000747 cardiac effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- 150000001880 copper compounds Chemical class 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229940125396 insulin Drugs 0.000 description 1
- 239000002650 laminated plastic Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61M—DEVICES FOR INTRODUCING MEDIA INTO, OR ONTO, THE BODY; DEVICES FOR TRANSDUCING BODY MEDIA OR FOR TAKING MEDIA FROM THE BODY; DEVICES FOR PRODUCING OR ENDING SLEEP OR STUPOR
- A61M5/00—Devices for bringing media into the body in a subcutaneous, intra-vascular or intramuscular way; Accessories therefor, e.g. filling or cleaning devices, arm-rests
- A61M5/14—Infusion devices, e.g. infusing by gravity; Blood infusion; Accessories therefor
- A61M5/142—Pressure infusion, e.g. using pumps
- A61M5/14244—Pressure infusion, e.g. using pumps adapted to be carried by the patient, e.g. portable on the body
- A61M5/14276—Pressure infusion, e.g. using pumps adapted to be carried by the patient, e.g. portable on the body specially adapted for implantation
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
- B32B37/144—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers using layers with different mechanical or chemical conditions or properties, e.g. layers with different thermal shrinkage, layers under tension during bonding
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B38/00—Ancillary operations in connection with laminating processes
- B32B38/10—Removing layers, or parts of layers, mechanically or chemically
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R25/00—Deaf-aid sets, i.e. electro-acoustic or electro-mechanical hearing aids; Electric tinnitus maskers providing an auditory perception
- H04R25/60—Mounting or interconnection of hearing aid parts, e.g. inside tips, housings or to ossicles
- H04R25/604—Mounting or interconnection of hearing aid parts, e.g. inside tips, housings or to ossicles of acoustic or vibrational transducers
- H04R25/606—Mounting or interconnection of hearing aid parts, e.g. inside tips, housings or to ossicles of acoustic or vibrational transducers acting directly on the eardrum, the ossicles or the skull, e.g. mastoid, tooth, maxillary or mandibular bone, or mechanically stimulating the cochlea, e.g. at the oval window
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61M—DEVICES FOR INTRODUCING MEDIA INTO, OR ONTO, THE BODY; DEVICES FOR TRANSDUCING BODY MEDIA OR FOR TAKING MEDIA FROM THE BODY; DEVICES FOR PRODUCING OR ENDING SLEEP OR STUPOR
- A61M2205/00—General characteristics of the apparatus
- A61M2205/02—General characteristics of the apparatus characterised by a particular materials
- A61M2205/0244—Micromachined materials, e.g. made from silicon wafers, microelectromechanical systems [MEMS] or comprising nanotechnology
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/362—Heart stimulators
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/372—Arrangements in connection with the implantation of stimulators
- A61N1/375—Constructional arrangements, e.g. casings
- A61N1/37512—Pacemakers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2305/00—Condition, form or state of the layers or laminate
- B32B2305/80—Sintered
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
- B32B2307/202—Conductive
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
- F04C2270/00—Control; Monitoring or safety arrangements
- F04C2270/04—Force
- F04C2270/042—Force radial
- F04C2270/0421—Controlled or regulated
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13344—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13347—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13355—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/27312—Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/27318—Manufacturing methods by local deposition of the material of the layer connector in liquid form by dispensing droplets
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29344—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29347—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29355—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2224/29388—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29499—Shape or distribution of the fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/8184—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
- H01L2224/83204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83439—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83874—Ultraviolet [UV] curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
- H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15798—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20104—Temperature range 100 C=<T<150 C, 373.15 K =< T < 423.15K
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20106—Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20107—Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
Definitions
- the invention relates to a method for producing an electronic assembly.
- Such a method is known from DE 10 2008 009 220 A1 and from DE 10 2010 014 579 A1 .
- the pamphlet DE 10 2011 000 530 A1 discloses a method of manufacturing a semiconductor device.
- a paste is applied to a metal foil and a semiconductor chip is pressed into this paste.
- the pamphlet JP2008141007 discloses a method of making a multilayer substrate.
- An electronic component is arranged between several resin films in order to protect it from damage and to make electrical contact.
- the pamphlet DE 10 2008 040 488 A1 discloses an electronic assembly and a method for its manufacture.
- the object of the present invention is to specify an improved method and an improved electronic assembly.
- Embodiments of the invention are particularly advantageous since the lamination and the low-temperature sintering can take place essentially simultaneously in the same process step. This is made possible on the one hand by the use of nanoparticles, which enable low-temperature sintering in a temperature range that is also suitable for laminating the film, and on the other hand by the prior fixing of the at least one electrical component on the surface of the electrically conductive film. This fixation ensures that the electrical component is in the right place when the carrier for the subsequent lamination is applied to the film and the components in the room, and that the component cannot slip.
- An “electrical component” is understood here to mean in particular housed and unhoused electronic components, such as integrated semiconductor chips, for example so-called bare chips (“bare chip” or “bare die”), as well as discrete electrical or electronic components, such as capacitors.
- Such an electrical component usually has one side on which one or more electrical contact points are provided for making electrical contact with the component.
- This side of the component is also referred to as the "active side" of the component.
- the electrical contact points are designed as so-called contact pads.
- the carrier can be pre-impregnated fibers (that is, a so-called prepreg), which is understood here to be an uncured thermoset plastic matrix.
- the carrier can be a liquid crystal polymer (LCP), which is particularly advantageous for the production of biocompatible implants, or another carrier material.
- an electrically conductive film is used as the starting material, the surface of which is coated with nanoparticles.
- the at least one electrical component is then fixed on the surface of the electrically conductive film by an adhesive that is applied outside the electrical contact points of the component.
- the adhesive is preferably a non-conductive adhesive, that is to say a so-called non-conducting adhesive (NCA) or a non-conducting paste (NCP). If, for example, the electrical component is a bare die that is surrounded by a passivation layer outside the electrical contact points, the adhesive connection is established between the passivation layer and the surface of the electrically conductive film with the aid of this adhesive.
- an electrically conductive film is used as the starting material, the surface of which does not have to be coated with nanoparticles.
- an adhesive that contains the nanoparticles is used.
- the adhesive is applied to the at least one electrical contact point of the electrical component in order to fix the electrical component on the surface of the electrically conductive film.
- the carrier is then applied in order to laminate the film with the carrier and at the same time to carry out the low-temperature sintering.
- the nanoparticles contained in the adhesive bond sinter here.
- the low-temperature sintering is carried out as "pressureless” low-temperature sintering.
- pressureless is understood to mean that the low-temperature sintering is not carried out at the high pressures of, for example, 200 bar, ie 2000 kPa, which are usually to be used, but at a significantly lower pressure, as is also used for lamination, that is to say at a pressure of, for example, 15-20 bar. i.e. 1500-2000 kPa.
- Corresponding adhesives or pastes which contain nanoparticles for such a pressureless low-temperature sintering are known per se from the prior art, such as from DE 10 2008 039 828 A1 , and are commercially available from Heraeus under the trade name mAgic Adhesive or mAgic Paste.
- connection produced in this way is particularly mechanically stable and has good electrical contact properties due to the covalent bonds of the nanoparticles, which lead to a low contact resistance.
- the size of the nanoparticles is selected so that they are chemically relatively inert at room temperature, so that at There is no spontaneous sintering at room temperature.
- the size of the nanoparticles is selected to be sufficiently small so that in the temperature range required for lamination the reactivity of the nanoparticles is already increased compared to macroscopic particles to such an extent that covalent chemical bonds are formed between the nanoparticles, so that they sinter together .
- the adhesive can be an LCP.
- the carrier is also formed by an LCP, in particular with regard to the thermal load capacity and the long-term stability of the resulting electronic assembly, which is particularly advantageous for applications in the medical field, in particular for implants.
- the invention relates to a method for producing an electronic assembly, in which, prior to the lamination of the film with the carrier, the at least one component arranged on the electrically conductive film is enveloped with a filler material made of a polymer Encasing the low-temperature sintering takes place.
- a filler material made of a polymer Encasing the low-temperature sintering takes place.
- the invention relates to an electronic assembly which has been produced using a method according to the invention.
- it can be an implant, such as an electronics module for an insulin pump, a cardiac pacemaker or an implantable hearing aid.
- the film is advantageously provided by providing individual, cut-to-size film sections or by providing an endless film from a roll.
- the at least one electrical component is preferably provided by providing it on an endless film or by providing it in a magazine.
- the at least one electrical component is advantageously arranged in an automated manner by an assembly robot or by hand, in particular with the aid of templates or position markers in or on the film.
- the carrier can be provided by providing individual, cut-to-size carrier sections or by providing an endless carrier from a roll.
- the film is preferably laminated to the carrier by exerting a contact pressure on the film in the direction of the carrier, in particular with the simultaneous action of heat.
- the structuring of the electrically conductive film to form conductor tracks and, if necessary, cooling surfaces is advantageously carried out by direct structuring, e.g. B. with a laser, or by creating a positive or negative mask and then etching.
- the film with the carrier and the at least one electrical component is advantageously wound onto a roll after the film has been structured.
- the at least one electrical component is encased after the component has been arranged on the film with a filler material made of a polymer, in particular a thermoplastic, thermoset or an elastomer.
- the filling material is advantageously filled into a predetermined shape, in particular by pouring, foaming, extruding or lamination.
- At least one further carrier layer is produced on the conductor tracks produced by structuring takes place, this preferably being insulating and / or dielectric and / or containing further conductor tracks.
- At least one reinforcement layer preferably a plurality of reinforcement layers, can be applied to the carrier or the carrier layer.
- the carrier can be cut to size in a predetermined shape for forming the electronic assembly, in particular before and / or after lamination with the circuit board in step 1.6. respectively.
- the electrically conductive film can consist of metal, in particular copper, electrically conductive plastic or electrically conductive ceramic, on the surface of which, if necessary, a layer of silver or a silver compound and / or a three-dimensional structure of metallic nanoparticles is present and possibly through a carrier film is reinforced.
- the electrically conductive film is smooth or roughened on the side facing the at least one electrical component or has a hump structure.
- the at least one electrical component is a passive or active component, in particular a chip, wherein it is preferably provided with a protective coating, in particular a lacquer, i.e. a so-called passivation layer, outside the contact points.
- a protective coating in particular a lacquer, i.e. a so-called passivation layer, outside the contact points.
- the protective coating is electrically insulating and / or a dielectric.
- the carrier can advantageously be a film, in particular made of metal, plastic or ceramic, a mat made of natural materials, such as. B. vegetable fibers, a leather section, a textile section or a section of another fabric or Be a composite material or a printed circuit board, a ceramic carrier or a glass carrier.
- the carrier is assigned a reinforcing layer and can in particular be made of metal, plastic or ceramic, made of natural materials, such as. B. vegetable fibers, leather, textile or some other fabric or composite material or can be a printed circuit board, a ceramic carrier or a glass carrier.
- the at least one electrical component can have at least one contact side, in each of which at least one electrical contact point is arranged, the at least one electrical contact point preferably being flat with the corresponding contact side.
- the contact point is advantageously made of copper or a copper compound, on the surface of which a layer of silver or a silver compound and / or a three-dimensional structure made of metallic nanoparticles may be present.
- a section of the electrically conductive film is formed as a heat-dissipating contact area on the at least one electrical component (film cooling section).
- a cooling body or a cooling channel is connected to the film cooling section and / or the at least one electronic component.
- fig. 1 shows schematically a detail of a side view of an electrically conductive foil 3 made of copper unwound from a roll.
- a film surface 3o which subsequently faces an electrical component 5, is provided with a uniform coating of nanoparticles, for example silver particles with a particle size of approx. 20-300 nm or a silver-containing alloy.
- the film 3 is reinforced on the side opposite the side 3o by a carrier film 3a which is laminated onto the film 3 and consists of a polymer.
- fig. 2 shows schematically an electrical component 5, in this case a chip, in a sectional view.
- the component 5 is made up of a protective layer 5a on all sides coated with electrically insulating lacquer, ie a so-called passivation layer.
- the component 5 has a contact side 5b, which is also referred to as the active side, with two contact points 5c for making electrical contact with the film 3, which are cut out by the applied protective layer 5a.
- the component 5 can have further contact points, such as on its edge 21 or on the upper side 22.
- the surfaces of the contact points 5c are, as shown in FIG fig. 2 B can be seen, coated with a layer of silver (or a silver-containing alloy), namely with nanoparticles 37.
- the nanoparticles can partially diffuse into the contact points 5c, which results in a particularly low electrical contact resistance.
- the components 5 are provided from a film unwound from a roll, on which they are arranged at a distance from one another. For example, the component 5 is a bare die, the contact points 5c then being designed as so-called contact pads.
- a robot arm picks up one or more components 5 from the film and places them on the coated surface 3o of the film 3 at defined locations.
- an adhesive is applied between the component 5 and the surface 30 of the electrically conductive film in order to fix the component by forming an adhesive connection, the connection 7 being an adhesive connection.
- the adhesive is applied to the surface 30 of the film before one of the components 5 is set down.
- the adhesive can be applied, for example likewise robotically, to the active side, ie the contact side 5b of the component 5, outside the electrical contact points 5c.
- Another example that does not fall under the claimed invention is that the component is first positioned by the robot arm on the surface 30 of the electrically conductive film in order to arrange the component there, and that the adhesive is then applied to produce the adhesive connection, for example by applying the adhesive along the side edge of the component (see also the examples according to Fig. 9 ).
- the adhesive connection produced in this way fixes the components 5 mechanically on the film 3 without electrically contacting them.
- the adhesive 20 (cf. Fig. 9 ) applied outside the electrical contact points 5c in order to allow the subsequent formation of the mechanical and electrical connection 23 (cf. Fig. 4 ) not to be hindered by the low-temperature sintering, especially since the adhesive 20 in this example contains ⁇ a metallic nanoparticle.
- fig. 3 shows the arrangement of two components 5 fastened in this way on the film 3.
- a film of a thermoplastic polymer is unrolled from a further roll and onto the arrangement of the fig. 3 hung up.
- Both are passed through a gap between two heated rollers in order to heat the film of the thermoplastic polymer and to press it against the film 3 in order to enclose the components 5.
- the low-temperature sintering ie the formation of a mechanical and electrical connection 23 between the contact points 5c and the surface 30, can already occur when the rollers are sufficiently warm.
- a film of a plastic composite material in the present case glass fibers arranged in an epoxy resin, is now unwound from a further roll and placed on the arrangement of the fig. 4th hung up. Both are passed through a gap between two heated rollers in order to heat the film of the plastic composite material and to press it against the envelope, ie the filler material 19, in order to laminate the plastic composite material onto the envelope.
- the laminated plastic composite material forms a carrier 9 for the arrangement of fig. 4th , in the present case a rigid carrier 9.
- the low-temperature sintering for forming the mechanical and electrical connection 23 between the contact points 5c and the surface 30 is carried out in this step by the lamination takes place in a temperature range required for this, so that sintering is also triggered at the same time as the lamination.
- a laser beam directed onto the film surface 3u vaporizes predetermined sections of the film 3.
- the remaining sections of the film 3 form conductor tracks 11 and an electrically non-connected film cooling section 13, see FIG. fig. 6th .
- layer 9a being a thermoplastic polymer
- layer 9b being a plastic composite material, in the present case glass fibers arranged in an epoxy resin, see fig. fig. 7th .
- the Figure 9a shows a perspective view of the film 3 with two electronic components 5.1 and 5.2, which are each designed here as so-called bare dies.
- the Figure 9b shows a plan view of the film which does not fall under the claimed invention, the film 3 with the components 5.1 and 5.2 fixed thereon by the adhesive connection.
- the adhesive 20 is applied so that the adhesive connection between the lateral edge 21 and the surface 30 of the film 3 results.
- the adhesive 20 for fixing the component 5.2 is applied punctiformly on the film 3 in the area of the corners of the component 5.2, as also shown in FIG. 9b.
- the Figure 9c shows the corresponding sectional views.
- the possible active surface for electrical contacting of the components 5.1 or 5.2 is not or only insignificantly reduced by the formation of the adhesive connection.
- essentially the entire underside of the components 5.1 or 5.2, ie the contact side 5b, is available for electrical contact with the film 3, as is the upper sides of the components 5.1 and 5.2.
- Fig. 10 to fig. 14th show schematically a section of a conductive film 3 unwound from a roll according to a further example which does not fall under the claimed invention.
- This film 3 has adjustment markings 2 at certain precisely defined points, for example in the form of holes extending through the film 3.
- the film 3 is uncoated on both sides. It is, for example, a copper foil.
- Adhesive 20 is applied to the upper side 30 at certain points which are defined in their position with respect to the adjustment marks 2.
- the application can be done by printing, spraying, dripping or the like.
- Individual spacer elements 31, for example glass spheres of a certain size, can be mixed into the adhesive. With the size of the spacer it is possible to set different thicknesses of the dielectric.
- the adhesive also contains nanoparticles to enable the subsequent low-temperature sintering, preferably a pressureless low-temperature sintering.
- an envelope made of a filler material 19, for example a polymer mass can be applied around the electronic components 5, which envelops individual or all electronic components in a separate or a common envelope.
- This process can trigger the sintering of the nanoparticles contained in the adhesive 20 in order to create the connections 23 (cf. Fig. 4 ) if the process is carried out at a sufficiently high temperature.
- the envelope extends outside the electronic components 5 up to that in the Fig. 10 to fig. 13 upper side 30 of the slide 3.
- the adjustment markings 2 can also be used for dimensioning and arranging the cover made of the polyester compound with respect to the electronic components 5.
- the sheathing envelops components 5 and extends as far as the film 3, and possibly also forms a type of adhesive bond with the film 3, a mechanically stable block is thereby formed.
- the envelope also extends between the contact points, as in FIG Figures 13 and 14 shown.
- the film 3 provided with the covering is laminated to a circuit board carrier 9, which comes to lie on the side of the film 3 on which the electronic components 5 are also arranged (cf. the arrangement according to FIG Fig. 5 ). This, at the latest, triggers the sintering and thus the production of the connections 23.
- the film 3 is now structured on its free side 8, so that conductor tracks are now produced.
- fig. 15th shows such a further embodiment of an electronic assembly, with practically two assemblies, as in fig. 14th shown, are connected back to back with the interposition of a metallic layer 12, which is arranged between the two circuit board supports 9.
- This metallic layer 12 is used, for example, to dissipate the heat generated in the electronic components 5.
- the two assemblies summarized here differ from the simple assembly of the fig. 14th nor in that on the in fig. 14th
- metallized cooling channels 15 lead through the circuit board carrier 9 to the central cooling layer 12, so that the heat can be dissipated here.
- the fig. 16 to fig. 21st show states during the implementation of the procedure which are approximately the fig. 10 to fig. 14th correspond.
- the illustrated embodiment is a film 33 as the starting material, which is attached to a carrier film 34.
- the carrier film 34 can consist of metal, ceramic or also polymer.
- the conductive foil 33 consists for example of copper and is not coated with nanoparticles.
- connection pads 35 are formed on the carrier film 34 which correspond to the connection points 5c of the electronic components to be fastened.
- Such an electronic component 5 is shown in fig. 18th shown.
- This electronic component 5 is now connected to the connection pads 35 with its connection points 5c. This can be done, for example, by applying adhesive 20 to the connection pads 35 or the sides of the connection points 5c of the electronic component 5 facing them.
- the adhesive 20 is an adhesive with nanoparticles distributed in the adhesive. As a result, an adhesive layer is formed that is present between the connection pads 35 and the connection points 5c of the electronic component 5. In this way, the electronic component 5 is connected to its connection points 5c facing the connection pads 35, namely initially only via an adhesive connection.
- the electronic component 5 can then be surrounded by an envelope made of a filler material 19, again made of polymer compound, which surrounds the entire electronic component 5 including the connection pads 35 and extends as far as the carrier film 34.
- a filler material 19 again made of polymer compound
- the carrier film 34 can then be separated, which is shown in FIG fig. 20th is shown.
- the further treatment of the casing or a lamination and the electronic component 5 contained therein takes place in the manner customary for printed circuit boards. It is essential that the wrapping with the filler material or the lamination a temperature range is reached in which the low-temperature sintering of the nanoparticles contained in the adhesive 20 is triggered in order to create the connections 23 (cf. Fig. 4 ) to produce.
- fig. 20th shows the detachment of the carrier layer 34. Instead of detaching the carrier layer 34, it is also possible not to detach the carrier layer 34, but to structure it further, for example by etching, by removal or the like. This is in fig. 21st shown.
- the fig. 22 and fig. 23 show a further example which does not fall under the claimed invention, wherein a thicker film 36 is used as the starting film, which is then similar to FIG fig. 17th is initially structured on its side facing the electronic components, in order to thereby form connection pads 35. Links in fig. 22nd the initial state of this thicker film 36 is shown, while on the right in FIG fig. 22nd the result of the structuring is shown.
- the electronic component 5 is then placed on the structured film produced in this way in the same way, fastened with the aid of the adhesive 20, as shown in FIG fig. 18th was shown.
- structuring can take place after the electronic component 5 and the casing have been attached.
- the method proposed by the invention makes it possible to achieve a considerably increased use of space on electronic circuit carriers. Additional layers can be produced with components populated in a very small space, both active and passive components.
- the passive and active electronic components can be encapsulated inexpensively, which results in a high level of reliability. Risky mixed techniques, namely soldering, gluing and wire bonding are avoided in production.
- a planar initial structure enables reproducible RF transitions to be achieved. It is of particular advantage that no separate process step is required for the formation of the electrical connections, since this takes place by low-temperature sintering together with the casing or the lamination, and that this simultaneously creates a particularly stable mechanical connection and an electrical connection with a low contact resistance and a short length results, which is advantageous for high frequency applications.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- General Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Public Health (AREA)
- Animal Behavior & Ethology (AREA)
- Biomedical Technology (AREA)
- Veterinary Medicine (AREA)
- Otolaryngology (AREA)
- Heart & Thoracic Surgery (AREA)
- Mechanical Engineering (AREA)
- Hematology (AREA)
- Anesthesiology (AREA)
- Vascular Medicine (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Neurosurgery (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Laminated Bodies (AREA)
- Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
- Radiology & Medical Imaging (AREA)
- Cardiology (AREA)
Claims (13)
- Procédé de fabrication d'un module électronique (1) avec les étapes :1.1 fourniture d'une feuille (3) électriquement conductrice, notamment une feuille support (3a),1.2 fourniture d'au moins un composant (5) électrique avec au moins un point de contact électrique (5c),1.3 dépôt d'un adhésif (20) entre le composant électrique et une surface (30) de la feuille électriquement conductrice,1.4 agencement de l'au moins un composant (5) avec l'au moins un point de contact électrique (5c) sur la surface (30) de la feuille (3) électriquement conductrice, et fixation de l'au moins un composant par la création d'une liaison adhésive entre le composant électrique et la surface,1.5 fourniture d'un support (9), notamment à base d'un matériau souple,1.6 laminage de la feuille (3) avec le support (9) de telle façon que l'au moins un composant (5) électrique soit disposé entre la feuille (3) et le support (9), et formation d'une liaison (23) mécanique et électrique entre le point de contact électrique de l'au moins un composant (5) électrique et la feuille (3) conductrice électriquement par un frittage à basse température de nanoparticules,1.7 structuration de la feuille (3) électriquement conductrice en pistes conductrices (11) et/ou en surfaces de refroidissement (13), caractérisé en ce que le laminage de la feuille a lieu simultanément au frittage à basse température.
- Procédé selon la revendication 1, dans lequel le laminage et le frittage à basse température ont lieu à 130 - 300 degrés Celsius, ou entre 150 et 250 degrés Celsius, ou à 170 à 190 degrés Celsius, ou à 180 degrés Celsius.
- Procédé selon la revendication 1 ou la revendication 2, dans lequel l'adhésif contient des nanoparticules, et l'adhésif est rapporté sur l'au moins un point de contact électrique.
- Procédé selon la revendication 3, dans lequel des nanoparticules frittées, qui sont incorporées dans une matrice formée par l'adhésif, sont créées par le frittage à basse température.
- Procédé selon l'une des revendications précédentes, dans lequel le frittage à basse température est exécuté à une pression de 15 à 20 bar, c'est-à-dire de 1500 à 2000 kPa.
- Procédé selon l'une des revendications précédentes, dans lequel le laminage de la feuille (3) avec le support (9) dans l'étape 1.6 a lieu par l'exercice d'une pression d'appui sur la feuille (3) en direction du support (9) sous l'influence simultanée de chaleur.
- Procédé selon l'une des revendications précédentes, caractérisé par un enveloppement de l'au moins un composant électrique après l'étape 1.4 avec un matériau de remplissage (19) à base d'un polymère.
- Procédé selon la revendication 8, caractérisé en ce que le polymère est un thermoplastique, un duroplastique, un élastomère ou un polymère cristal liquide.
- Procédé selon l'une des revendications précédentes, caractérisé en ce qu'après l'étape 1.7, il y a une application d'au moins une couche de renforcement (9b) sur le support (9) ou la couche support (9a), ou que le support (9) est retiré après l'étape 1.6.
- Procédé selon l'une des revendications précédentes, caractérisé par un découpage du support (9) dans une forme prédéterminée pour former le module électrique (1) avant ou après le laminage avec le support (9) dans l'étape 1.6.
- Procédé selon l'une des revendications précédentes, dans lequel, dans le cas des nanoparticules, il s'agit d'argent avec une taille particulaire entre 20 et 300 nm.
- Procédé selon l'une des revendications précédentes, dans lequel la surface de la feuille est munie d'un revêtement régulier de 200 à 300 nm d'argent ou d'un alliage contenant de l'argent.
- Procédé selon l'une des revendications précédentes, dans lequel les nanoparticules sont formées à base d'or, d'argent, de nickel ou de cuivre ou d'un alliage à base de ces métaux.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2012/059476 WO2013174418A1 (fr) | 2012-05-22 | 2012-05-22 | Procédé de fabrication d'un module électronique |
Publications (2)
Publication Number | Publication Date |
---|---|
EP2852970A1 EP2852970A1 (fr) | 2015-04-01 |
EP2852970B1 true EP2852970B1 (fr) | 2021-01-06 |
Family
ID=46146895
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP12722392.3A Not-in-force EP2852970B1 (fr) | 2012-05-22 | 2012-05-22 | Procédé de fabrication d'un module électronique |
Country Status (3)
Country | Link |
---|---|
US (1) | US20150131240A1 (fr) |
EP (1) | EP2852970B1 (fr) |
WO (1) | WO2013174418A1 (fr) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2856500A4 (fr) * | 2012-06-04 | 2015-12-02 | Nokia Technologies Oy | Appareil comprenant des parties conductrices et procédé de fabrication de l'appareil |
DE102013210668A1 (de) | 2013-06-07 | 2014-12-11 | Würth Elektronik GmbH & Co. KG | Verfahren zur Herstellung eines optischen Moduls |
US9640468B2 (en) * | 2014-12-24 | 2017-05-02 | Stmicroelectronics S.R.L. | Process for manufacturing a package for a surface-mount semiconductor device and semiconductor device |
CN107454547B (zh) * | 2017-09-08 | 2019-11-15 | 维沃移动通信有限公司 | 一种麦克风和麦克风制作方法 |
TWI645973B (zh) * | 2017-12-15 | 2019-01-01 | 律勝科技股份有限公司 | 聚醯亞胺薄化軟性基板及其製造方法 |
EP3796373B1 (fr) * | 2019-09-20 | 2023-06-28 | BIOTRONIK SE & Co. KG | Agencement de platine d'un appareil médical implantable |
CN111524883B (zh) * | 2020-04-29 | 2022-09-20 | 业成科技(成都)有限公司 | 膜内电子组件及其制备方法 |
CN113339186A (zh) * | 2021-06-30 | 2021-09-03 | 北京航空航天大学宁波创新研究院 | 一种液压泵马达摩擦副配对结构及应用 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008141007A (ja) * | 2006-12-01 | 2008-06-19 | Denso Corp | 多層基板の製造方法 |
DE102008040488A1 (de) * | 2008-07-17 | 2010-01-21 | Robert Bosch Gmbh | Elektronische Baueinheit und Verfahren zu deren Herstellung |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7176055B2 (en) * | 2001-11-02 | 2007-02-13 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component |
JP2004201285A (ja) * | 2002-12-06 | 2004-07-15 | Murata Mfg Co Ltd | 圧電部品の製造方法および圧電部品 |
US20070107837A1 (en) * | 2005-11-04 | 2007-05-17 | Dutton Steven L | Process for making high count multi-layered circuits |
US7829389B2 (en) * | 2007-10-05 | 2010-11-09 | Texas Instruments Incorporated | Roll-on encapsulation method for semiconductor packages |
DE102008009220A1 (de) | 2008-02-06 | 2009-08-13 | Robert Bosch Gmbh | Verfahren zum Herstellen einer Leiterplatte |
DE102008039828A1 (de) | 2008-08-27 | 2010-03-04 | W.C. Heraeus Gmbh | Steuerung der Porosität von Metallpasten für den druckfreien Niedertemperatursinterprozess |
DE102009050199A1 (de) * | 2009-10-21 | 2011-04-28 | Giesecke & Devrient Gmbh | Herstellung von Leiterstrukturen auf Kunststoff-Folien mittels Nanotinten |
US8193040B2 (en) * | 2010-02-08 | 2012-06-05 | Infineon Technologies Ag | Manufacturing of a device including a semiconductor chip |
US8338231B2 (en) * | 2010-03-29 | 2012-12-25 | Infineon Technologies Ag | Encapsulated semiconductor chip with external contact pads and manufacturing method thereof |
DE102010014579A1 (de) | 2010-04-09 | 2011-10-13 | Würth Elektronik Rot am See GmbH & Co. KG | Verfahren zum Herstellen einer elektronischen Baugruppe |
-
2012
- 2012-05-22 EP EP12722392.3A patent/EP2852970B1/fr not_active Not-in-force
- 2012-05-22 US US14/402,095 patent/US20150131240A1/en not_active Abandoned
- 2012-05-22 WO PCT/EP2012/059476 patent/WO2013174418A1/fr active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008141007A (ja) * | 2006-12-01 | 2008-06-19 | Denso Corp | 多層基板の製造方法 |
DE102008040488A1 (de) * | 2008-07-17 | 2010-01-21 | Robert Bosch Gmbh | Elektronische Baueinheit und Verfahren zu deren Herstellung |
Also Published As
Publication number | Publication date |
---|---|
EP2852970A1 (fr) | 2015-04-01 |
WO2013174418A1 (fr) | 2013-11-28 |
US20150131240A1 (en) | 2015-05-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2852970B1 (fr) | Procédé de fabrication d'un module électronique | |
EP2027600B1 (fr) | Procédé pour noyer au moins un composant dans un élément de carte de circuits imprimés | |
DE102011006489B4 (de) | Leiterplatte mit eingebautem Halbleiterchip und Verfahren zur Herstellung derselben | |
DE112004001727B4 (de) | Verfahren zur Herstellung eines elektronischen Moduls | |
DE102010042567B3 (de) | Verfahren zum Herstellen eines Chip-Package und Chip-Package | |
EP1926355B1 (fr) | Procédé de fabrication d'un support de circuit extensible et support de circuit extensible | |
EP3081056B1 (fr) | Procédé d'intégration d'un composant dans une carte à circuit imprimé | |
EP2260683B1 (fr) | Procédé de fabrication d'un module électronique | |
EP3231262B1 (fr) | Circuit imprimé semi-flexible avec composant encapsulé | |
DE102011006341A1 (de) | Verfahren zur Fertigung eines Verdrahtungssubsrats mit eingebetteten Halbleiterchip | |
DE102009011975B4 (de) | Halbleiteranordnung mit einem lagestabilen überdeckten Element | |
DE112005000952T5 (de) | Elektronik-Modul und Verfahren zur Herstellung desselben | |
WO2016091992A1 (fr) | Carte de circuits imprimés à structure de couches asymétrique | |
DE102008033651B4 (de) | Verfahren zur Herstellung eines Leistungshalbleitermoduls | |
DE102015120745B4 (de) | Chip-Schutzumhüllung und -verfahren | |
DE60133429T2 (de) | Verdrahtungssubstrat, seine Herstellung und Halbleiterbauteil | |
DE10232788B4 (de) | Elektronisches Bauteil mit einem Halbleiterchip auf einem Systemträger, Systemträger und Verfahren zur Herstellung eines elektronischen Bauteils | |
DE102020125813A1 (de) | Verfahren zum herstellen eines chipgehäuses und chipgehäuse | |
EP0071311A2 (fr) | Procédé de fabrication d'élements de contact montés sur les surfaces de connection d'un composant intégré | |
EP2982226B1 (fr) | Procédé de fabrication d'un élément de circuit imprimé | |
WO2009153129A2 (fr) | Procédé de fabrication d'un module électronique | |
WO2009098033A1 (fr) | Procédé de fabrication d'une plaquette | |
DE102010064453B4 (de) | Verfahren zum Herstellen eines Chip-Package | |
EP2491582A1 (fr) | Procédé de réalisation de trous métallisés | |
DE102006023168B4 (de) | Herstellungsverfahren für eine elektronische Schaltung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20141222 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
DAX | Request for extension of the european patent (deleted) | ||
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
17Q | First examination report despatched |
Effective date: 20170302 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: A61N 1/36 20060101ALN20191219BHEP Ipc: H01L 23/367 20060101ALN20191219BHEP Ipc: A61M 5/142 20060101ALN20191219BHEP Ipc: H01L 21/60 20060101AFI20191219BHEP Ipc: H01L 21/56 20060101ALI20191219BHEP Ipc: H01L 23/48 20060101ALN20191219BHEP Ipc: A61N 1/362 20060101ALN20191219BHEP |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: A61M 5/142 20060101ALN20200227BHEP Ipc: A61N 1/36 20060101ALN20200227BHEP Ipc: H01L 23/367 20060101ALN20200227BHEP Ipc: A61N 1/362 20060101ALN20200227BHEP Ipc: H01L 21/60 20060101AFI20200227BHEP Ipc: H01L 23/48 20060101ALN20200227BHEP Ipc: H01L 21/56 20060101ALI20200227BHEP |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 21/56 20060101ALI20200409BHEP Ipc: H01L 23/48 20060101ALN20200409BHEP Ipc: H01L 23/367 20060101ALN20200409BHEP Ipc: H01L 21/60 20060101AFI20200409BHEP Ipc: A61N 1/36 20060101ALN20200409BHEP Ipc: A61M 5/142 20060101ALN20200409BHEP Ipc: A61N 1/362 20060101ALN20200409BHEP |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 21/56 20060101ALI20200508BHEP Ipc: A61N 1/362 20060101ALN20200508BHEP Ipc: H01L 23/367 20060101ALN20200508BHEP Ipc: A61M 5/142 20060101ALN20200508BHEP Ipc: H01L 21/60 20060101AFI20200508BHEP Ipc: A61N 1/36 20060101ALN20200508BHEP Ipc: H01L 23/48 20060101ALN20200508BHEP |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 23/48 20060101ALN20200605BHEP Ipc: A61N 1/36 20060101ALN20200605BHEP Ipc: H01L 23/367 20060101ALN20200605BHEP Ipc: A61M 5/142 20060101ALN20200605BHEP Ipc: H01L 21/60 20060101AFI20200605BHEP Ipc: H01L 21/56 20060101ALI20200605BHEP Ipc: A61N 1/362 20060101ALN20200605BHEP |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: KOSTELNIK, JAN |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: A61M 5/142 20060101ALN20200622BHEP Ipc: H01L 21/60 20060101AFI20200622BHEP Ipc: H01L 23/367 20060101ALN20200622BHEP Ipc: A61N 1/362 20060101ALN20200622BHEP Ipc: A61N 1/36 20060101ALN20200622BHEP Ipc: H01L 21/56 20060101ALI20200622BHEP Ipc: H01L 23/48 20060101ALN20200622BHEP |
|
INTG | Intention to grant announced |
Effective date: 20200722 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: REF Ref document number: 1353278 Country of ref document: AT Kind code of ref document: T Effective date: 20210115 Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 502012016572 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: LANGUAGE OF EP DOCUMENT: GERMAN |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20210106 |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG9D |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210407 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210506 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210406 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210406 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210506 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 502012016572 Country of ref document: DE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 502012016572 Country of ref document: DE |
|
26N | No opposition filed |
Effective date: 20211007 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20210522 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210531 Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210522 Ref country code: AL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210531 |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20210531 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210522 Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210522 Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211201 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210506 Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210531 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MM01 Ref document number: 1353278 Country of ref document: AT Kind code of ref document: T Effective date: 20210522 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210531 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210522 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO Effective date: 20120522 Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210106 |