Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B41/42—Simultaneous manufacture of periphery and memory cells
  • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
  • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor

Definitions

• the present invention relates to a semiconductor fabrication process, and more particular, to a method of isolating dual-trench element and a method of fabricating flash memory by etching an active region.
• an isolation layer of a semiconductor element is formed by using a
• LOCOS LOCaI Oxidation of Silicon
• PBL Poly Buffered Locos
• FlG. 1 shows a cross-sectional view of a wafer formed by using the conventional method of isolating a dual-trench element.
• dual-trench isolation layers TI-I and TI-2 each having a different depth are formed on a semiconductor substrate 100.
• the trench isolation layer TI-I is formed deep, whereas the trench isolation layer
• TI-2 is formed shallow.
• a pad oxide grows on the semiconductor substrate 100, and a dielectric material layer is then deposited thereon.
• the dielectric material layer and the pad oxide are removed from a portion where the trench isolation layers TI-I and TI-2 are formed.
• an exposed substrate surface is etched to the extent of a trench depth of the trench isolation layer TI-2, thereby forming trenches.
• only a portion where the trench isolation layer TI-I is formed is open by performing the patterning and etching processes again, and the substrate surface is etched to form a trench depth of the trench isolation layer TT-I.
• a high density plasma oxide is deposited on the entire substrate surface so as to fill the trenches formed on the trench isolation layers TI-I and TI-2.
• the substrate surface is then polished through a CMP (Chemical Mechanical Polish) process.
• FlG. 2 is a cross-sectional view of a flash memory formed by using the conventional method of isolating a dual-trench element.
• the flash memory includes transistors that form floating gates by using two poly silicon layers. Referring to FlG. 2, the transistors of the flash memory are formed on a substrate 100 on which trenches TI-I and TI-2 are formed.
• a second poly silicon layer 202 is formed on an active region of a first area 210 where the trench TI-I is formed.
• a first poly silicon layer 201 and the second polysilicon layer 202 are laminated on an active region of a second area 220 where the trenches TI-2 are formed.
• the first area 210 and the second area 220 have a step difference A.
• the step difference A leads to a poor step coverage.
• the poor step coverage causes yield decrease in the flash memory. For example, a bridge effect may occur in a subsequent process. Disclosure of Invention Technical Problem
• the present invention provides a method of isolating a dual-trench element, in which a poor step coverage can be improved.
• the present invention also provides a method of fabricating a flash memory by using the method of isolating a dual-trench element.
• a method of isolating a dual-trench element comprising steps of: (a) forming a pad oxide and a first dielectric material layer on a semiconductor substrate; (b) forming first and second trenches by patterning the first dielectric material layer and the pad oxide and by etching the substrate; (c) filling the first and second trenches by depositing an oxide on the entire surface of the substrate, and polishing the surface of the substrate through a chemical mechanical polish process; (d) depositing and patterning a second dielectric material layer on the entire surface of the substrate and removing the second dielectric material layer, the first dielectric material layer, and the pad oxide in an area where the second trench is formed; and (e) etching an active surface of the area where the second trench is formed.
• the method may further comprise (f) removing the second dielectric material layer, the first dielectric material layer, and the pad oxide from an area where the first trench is formed.
• a method of fabricating a flash memory by using the method of isolating a dual-trench element comprising steps of: (g) performing thermal oxidation on the entire surface of a substrate so as to release a damage occurring when an active surface is etched, and then removing a thermal oxide, the second dielectric material layer in the first trench, and a part of S ⁇ oxide formed on the entire surface of the substrate; (h) depositing a tunnel oxide and a first polysilicon layer on the entire surface of the substrate; (i) polishing the entire surface of the substrate through a chemical mechanical polish process so that the first dielectric material layer and an oxide of the first trench are exposed in a first area where the first trench is formed whereas the first polysilicon layer and an oxide of the second trench are exposed in a second area where the second trench is formed; (j) etching the oxide of the second trench between a pair of first polysilicon layers in the second area after the first dielectric material layer in the first area is
• the first area may become a peripheral circuit area of a flash memory cell array block
• the second area may become an area of the flash memory cell array block
• the first polysilicon layer may be used for a floating gate of a flash memory cell
• the second polysilicon layer may be used for a control gate of the flash memory cell
• the first dielectric layer may be formed of an ONO
• FlG. 1 shows a cross-sectional view of a wafer formed by using the conventional method of isolating a dual-trench element.
• FlG. 2 is a cross-sectional view of a flash memory formed by using the conventional method of isolating a dual-trench element.
• FlG. 3 is a cross-sectional view of a wafer formed by using a method of isolating a dual-trench element according to an embodiment of the present invention.
• FIGS. 4 to 8 are views for explaining the method of isolating a dual-trench element of the present invention.
• FIGS. 9 to 14 are views for explaining a method of fabricating a flash memory by using the method of isolating a dual-trench element of the present invention. Best Mode for Carrying Out the Invention
• FlG. 3 is a cross-sectional view of a wafer formed by using a method of isolating a dual-trench element according to an embodiment of the present invention.
• first trenches TI-I and second trenches TI-2 are formed in a semiconductor substrate 100 such that their bottoms are located on the same line.
• an active surface of an area 320 where the second trenches TI-2 are formed is lower than an active surface of an area 310 where the first trenches TI-I are formed.
• the first trenches TI-I are uniformly formed on the entire surface of the substrate 100, and only a portion where the trenches TI-2 are formed is patterned, thereby selectively etching the active surface. Accordingly, an active surface of the area 320 defined by the trenches TI-2 is located lower than an active surface of the area 310 defined by the trenches TT-I. Since the bottoms of the first and second trenches TI-I and TI-2 are formed when the trenches TI-I are formed on the entire surface of the substrate 100, the trenches TT-I and TI-2 are located on the same line.
• FIGS. 4 to 8 are views for explaining the method of isolating a dual-trench element of the present invention.
• a pad oxide 401 grows on a semiconductor substrate 100, and a first dielectric material layer 402 is then deposited thereon.
• the first dielectric material layer 402 may be formed of a silicon nitride film.
• the first dielectric material layer 402 and the pad oxide 401 are removed from a portion where the first and second trenches TI-I and TI-2 are formed. Then, a surface of the substrate 100 is etched to the extent of the trench depths of the first and second trenches TI-I and TI-2, thereby forming the first and second trenches TI-I and TI-2.
• an oxide 403, for example, a HDP (High Density Plasma) oxide is deposited on the entire surface of the substrate 100 so as to fill the first and second trenches TT-I and TT-2, and the surface is polished through a CMP (Chemical Mechanical Polish) process.
• CMP Chemical Mechanical Polish
• a second dielectric material layer 404 is deposed on the entire surface of the substrate 100, and a photoresist 405 is deposited thereon.
• the second dielectric material layer 404 may be formed of an oxide film.
• the photoresist 405 is used in a coating process, followed by a patterning process. Thus, a portion where the second trenches TT-2 are formed is open, and the second dielectric material layer 404 is etched. If the second dielectric material layer 404 is etched through an oxide wet etching process, an upper portion of the oxide 403 filling the second trenches TI-2 is partially etched.
• the photoresist 405 of FlG. 5 is removed, the first dielectric material layer 402 is wet-etched by using the second dielectric material layer 404 as a mask, and the pad oxide 401 is removed. Accordingly, an active surface where the second trenches Tl-2 are formed is exposed.
• the oxide 403 filling the second dielectric material layer 404 and the second trenches TI-2 etches the active surface by using an etching method with a high selection ratio.
• the etching method may be a reactive ion etching method in which HBr, C2F6, CF4, He, or O2 is used as an etchant chemistry.
• the second dielectric material layer 404, the first dielectric material layer 402, and the pad oxide 401 of FlG. 7 are sequentially etched.
• FlG. 14 shows a flash memory formed by using the method of isolating a dual- trench element of FIGS. 4 to 8. FlG. 14 will be described later.
• FIGS. 9 to 14 are views for explaining a method of fabricating a flash memory by using the method of isolating a dual-trench element of the present invention.
• thermal oxidation is carried out on the entire surface of a substrate 100.
• a thermal oxide, the second dielectric material layer 404, and a part of the STI oxide 403 are removed through a wet oxide etching process.
• a tunnel oxide 501 and the first polysilicon layer 502 are deposited on the entire surface of the substrate 100.
• the first polysilicon layer 502 is used as a floating gate of a flash memory cell.
• the first polysilicon layer 502 is polished through the CMP process.
• the first area 310 where the first trenches TI-I are formed is polished so that the first dielectric material layer 402 and the HDP oxide 403 of the first trenches TI-I are exposed.
• the second area 320 where the second trenches TI-2 are formed is polished so that the first polysilicon layer 502 and the oxide 403 of the second trenches TI-2 are exposed.
• the first area 310 becomes a peripheral circuit area of a flash memory cell array block.
• the second area 320 becomes an area of the flash memory cell array block.
• the first dielectric material layer 402 of the first area 310 is wet-etched to be removed by using phosphoric acid (H3PO4). Then, the first dielectric material layer 402 is patterned to etch the HDP oxide 403 of the second trenches TI-2 between a pair of first polysilicon layers 502. Thereafter, a photoresist 403 is removed.
• H3PO4 phosphoric acid
• a first dielectric layer 504 is deposited on the entire surface of the substrate 100, and is then patterned to remove the first dielectric layer 504 from the first area 310. Further, the photoresist 403 is removed.
• the first dielectric layer 504 is formed of an ONO (Oxide-Nitride-Oxide) film.
• a second dielectric layer 505 is formed on the first area 310.
• a second polysilicon layer 506 is deposited on the entire surface of the substrate 100 and is patterned. The second polysilicon layer 506 is used as a control gate of a flash memory cell in the second area 320. Thereafter, a metal wire process is carried out according to a typical semiconductor fabricating process.
• the active surface of the second area 320 where the second trenches TI-2 are formed is etched, and the first polysilicon layer 502 is deposited and then polished with CMP, thereby forming a floating gate.
• the top of the first polysilicon layer 502 and the top of the first trench TI-I of the first area 310 are located on the same line with the same height.
• the second polysilicon layer 506 forming the control gate is formed in the first and second areas 310 and 320 with the same height. That is, the second polysilicon layer 506 does not have a step difference between the first and second areas 310 and 320. Accordingly, the flash memory does not experience a conventional problem of a step coverage illustrated in FlG. 2.
• a flash memory formed by using a method of isolating a dual-trench element of the present invention a step difference between a memory cell array area and a peripheral circuit area is removed, thereby improving a step coverage.

Landscapes

• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Element Separation (AREA)
• Semiconductor Memories (AREA)
• Non-Volatile Memory (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=38256473

Family Applications (1)

Country Status (3)

Citations (3)

• 2006
  • 2006-01-12 KR KR1020060003448A patent/KR100760829B1/ko not_active IP Right Cessation
  • 2006-12-04 WO PCT/KR2006/005166 patent/WO2007081089A1/en active Application Filing
  • 2006-12-12 TW TW095146534A patent/TW200727390A/zh unknown

Patent Citations (3)

Also Published As

Similar Documents

Legal Events