TW200727390A - Method of isolating dual-trench element and method of fabricating flash memory by etching active region - Google Patents

Method of isolating dual-trench element and method of fabricating flash memory by etching active region

Info

Publication number
TW200727390A
TW200727390A TW095146534A TW95146534A TW200727390A TW 200727390 A TW200727390 A TW 200727390A TW 095146534 A TW095146534 A TW 095146534A TW 95146534 A TW95146534 A TW 95146534A TW 200727390 A TW200727390 A TW 200727390A
Authority
TW
Taiwan
Prior art keywords
material layer
dielectric material
trench
area
flash memory
Prior art date
Application number
TW095146534A
Other languages
Chinese (zh)
Inventor
Han-Heung Kim
Original Assignee
Excel Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Excel Semiconductor Inc filed Critical Excel Semiconductor Inc
Publication of TW200727390A publication Critical patent/TW200727390A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Provided is a method of isolating dual-trench element and a method of fabricating flash memory by etching an active region. In the method of isolating a dual-trench element, a pad oxide and a first dielectric material layer are formed on a semiconductor substrates, and first and second trenches are formed by patterning the first dielectric material layer and the pad oxide and by etching the substrate. The first and second trenches are filled by depositing an oxide on the entire surface of the substrate, and the surface of the substrate is polished through a chemical mechanical polish process. A second dielectric material layer is deposited and polished on the entire surface of the substrates so as to remove the second dielectric material layer, the first dielectric material layer, and the pad oxide in an area where the second trench is formed. An active surface of the area where the second trench is formed is etched. The second dielectric material layer, the first dielectric material layer, and the pad oxide from an area where the first trench is formed are removed. Accordingly, a step difference between a memory cell array area and a peripheral circuit area is removed, thereby improving a step coverage.
TW095146534A 2006-01-12 2006-12-12 Method of isolating dual-trench element and method of fabricating flash memory by etching active region TW200727390A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060003448A KR100760829B1 (en) 2006-01-12 2006-01-12 Dual trench isolation method and fabrication method of flash memory device using active area etching method

Publications (1)

Publication Number Publication Date
TW200727390A true TW200727390A (en) 2007-07-16

Family

ID=38256473

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095146534A TW200727390A (en) 2006-01-12 2006-12-12 Method of isolating dual-trench element and method of fabricating flash memory by etching active region

Country Status (3)

Country Link
KR (1) KR100760829B1 (en)
TW (1) TW200727390A (en)
WO (1) WO2007081089A1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849518B2 (en) 2002-05-07 2005-02-01 Intel Corporation Dual trench isolation using single critical lithographic patterning
KR100454135B1 (en) 2002-10-10 2004-10-26 삼성전자주식회사 Method of forming non-volatile memory device
KR20040050967A (en) * 2002-12-11 2004-06-18 삼성전자주식회사 Method for forming dual trench structure in flash memory device

Also Published As

Publication number Publication date
KR20070075089A (en) 2007-07-18
WO2007081089A1 (en) 2007-07-19
KR100760829B1 (en) 2007-09-21

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