WO2007056949A1 - Amplificateur de puissance numerique applique a une communication sur porteuse basse tension - Google Patents

Amplificateur de puissance numerique applique a une communication sur porteuse basse tension Download PDF

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Publication number
WO2007056949A1
WO2007056949A1 PCT/CN2006/003081 CN2006003081W WO2007056949A1 WO 2007056949 A1 WO2007056949 A1 WO 2007056949A1 CN 2006003081 W CN2006003081 W CN 2006003081W WO 2007056949 A1 WO2007056949 A1 WO 2007056949A1
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WO
WIPO (PCT)
Prior art keywords
circuit
output
low voltage
power amplifier
gate
Prior art date
Application number
PCT/CN2006/003081
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English (en)
Chinese (zh)
Inventor
Chaosheng Song
Yunlai Wang
Yanhui Wu
Original Assignee
Miartech, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Miartech, Inc. filed Critical Miartech, Inc.
Publication of WO2007056949A1 publication Critical patent/WO2007056949A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers

Definitions

  • the present invention relates to a power amplifier, and more particularly to a digital power amplifier suitable for low voltage carrier communication. Background technique
  • a power amplifier is a special type of amplifier whose primary function is to provide sufficient output power to meet system design requirements. Differentiated by purpose, there are mainly audio power amplifiers and communication power amplifiers. Here we mainly discuss communication power amplifiers.
  • the main performance indicators of the power amplifier include output power, power conversion efficiency, etc., which are classified into Class A power amplifiers, Class B power amplifiers, Class AB power amplifiers, and Class D power amplifiers. The first three are working in the linear region of the amplifier, while the class D amplifier is working in the switch mode.
  • Class D power amplifiers are commonly used in some industrial and audio fields where the output signal frequency is relatively low.
  • the structure is shown in Figure 2. It includes D/A converter 110, triangular wave generator 111, pulse width modulator 112, and power stage drive circuit. 113 and band pass filter 114, wherein the triangular wave generator 111 outputs a high frequency triangular wave, usually having a frequency greater than 10 times greater than the highest frequency of the input signal, and the pulse width modulator 112 performs the conversion of the input D/A converter 110.
  • the pulse width modulation of the analog signal changes the linear input signal into a level signal, and the power stage driving circuit 113 completes the power amplification of the level signal.
  • the bandpass filter 114 performs low pass filtering of the output signal of the pulse width modulator 112, ultimately reducing the linear input signal.
  • the pulse width modulator 112 typically operates at a frequency of a few hundred kilohertz. If it is used to amplify a signal with a high frequency of the output signal, such as a signal carrier frequency used for low-voltage carrier communication, generally in the range of tens of kilohertz to hundreds of kilohertz, the power amplification achieved by the above analog method is due to its adoption.
  • the present invention provides a power amplifier realized in an all-digital manner, which can greatly improve power amplifier efficiency and reduce heat consumption.
  • the digital power amplifier technical solution provided by the present invention comprises a power stage driving circuit, a band pass filter and a transformer, wherein the amplifier further comprises: an upsampling filter for converting the low voltage carrier digital signal to be amplified To a more awkward sampling frequency; a noise shaping circuit that removes noise of the low-voltage carrier digital signal and outputs two differential signals; a dead zone control circuit for processing the two differential signals into two overlapping edges a signal that is shifted; wherein an input end of the noise shaping circuit is connected to an output end of the upsampling filter, and an output end thereof is connected to an input end of the dead zone control circuit, and an output end of the dead zone control circuit An input terminal of the power stage driving circuit is connected.
  • the dead zone control circuit includes: an RS flip-flop for processing two differential signals output by the noise shaping circuit to generate two mutually overlapping offset signals.
  • the RS flip-flop comprises: a NOR gate and a NAND gate, a first and a second non-gate delay unit, wherein the NOR gate is connected in series with the first NOT gate delay circuit, a NAND gate is connected in series with the first two-gate delay unit, an output end of the first non-gate delay circuit is connected to an input end of the NAND gate, and an output end of the second non-gate delay unit is connected The input of the NOR gate.
  • the dead zone controller further includes: a power stage driving circuit, which performs power amplification on the two mutually overlapping offset signals output by the RS flip-flop to push the half-bridge circuit; the half-bridge circuit, Generating an output signal of the power amplifier according to an output signal of the power stage driving circuit; wherein an input end of the power stage driving circuit is connected to an output end of the first and second non-gate delay circuits of the RS flip-flop The output of the power stage driving circuit is connected to the input end of the half bridge circuit.
  • the noise shaping circuit further includes: a subtracter that receives the output signal of the upsampling filter for subtraction processing to obtain multi-bit output data; and a unit delay module that is low for the multi-bit output data 2 bits of data are delayed; a limiter is configured to limit the upper 2 bits of the multi-bit output data to a three-value level of +1, 0, -1; a logical transformation unit The three-value level is converted into two differential digital signals suitable for driving the half-bridge power conversion circuit.
  • Figure 1 is a block diagram of a known linear power amplifier structure
  • FIG. 2 is a block diagram of an existing class D power amplifier structure
  • FIG. 3 is a structural diagram of a specific implementation of a digital power amplifier of the present invention.
  • Figure 4 is a structural diagram of an upsampling filter
  • Figure 5 is a structural diagram of a noise shaping circuit
  • Figure 6 is a structural diagram of a dead zone control circuit
  • Figure 7 is a circuit diagram of a band pass filter implementation
  • FIG. 8 is a schematic diagram of voltage and current of an output stage of a digital power amplifier according to the present invention. detailed description
  • the block diagram of the present invention is shown in Figure 3.
  • the all-digital power amplifier includes an upsampling filter 121, a noise shaping circuit 122, a dead zone control circuit 123, driver stage circuits 124, 125, a band pass filter 126, and a transformer 127.
  • the composition different from the conventional class D power amplifier is embodied in the first half thereof, that is, the portion formed by the three stages of the upsampling filter 121, the noise shaping circuit 122, and the dead zone control circuit 123.
  • the power stage drive circuits 124, 125, the band pass filter 126, and the transformer 127 are substantially similar to conventional Class D power amplifiers.
  • the input end of the noise shaping circuit 122 is connected to the output end of the upsampling filter 121, the output end thereof is connected to the f input end of the dead zone control circuit 123, and the output of the dead zone control circuit 123 enters the power stage driving circuit 124. Zoom in at 125.
  • the signal whose input signal is a low clock frequency first passes through an upsampling filter 121.
  • the specific structure of the upsampling filter 121 is as shown in FIG. 4, and includes a first order differentiator 131, a ascending sample unit 132, and a first order.
  • the integrator 133 and the limiter 134 after the digital signal that needs to be amplified passes through the differentiator 131, enters the upsampling unit 132 for processing.
  • the so-called ascending sample is also subjected to high-power clock sampling, and then passes through the integrator 133 to complete the upsampling filtering.
  • the upsampled filtered data is input to a limiter 134 for limiting processing.
  • the function of the ascending sample filter 121 is mainly to low-pass filter the input low-voltage carrier digital signal, and high-pass filtering for noise, thereby reducing the noise energy in the pass band and effectively suppressing the signal. Stray.
  • FIG. 5 is a block diagram of the noise shaping circuit 122, including the subtractor 141, the unit Delay module 142, limiter 143 and logic transformation unit 144.
  • the ascending sample-filtered carrier digital signal is input to the subtractor 141 for subtraction, and the subtractor 141 performs processing according to the result in two cases: a case where the carrier digital signal has a number less than or equal to 2 bits
  • the signal is returned to the subtracter 141 through the unit delay module 142 and then subtracted from the digital signal input by the subtracter 141, that is, the subtractor 141 and the unit delay module 142 jointly implement differential processing to complete the noise shaping function of the class D power amplifier, and second.
  • the limiter 143 for data higher than 2 bits, it is directly sent to the limiter 143 for limiting processing, and its output signal is limited to between +1 and -1, and finally passes through the logic conversion unit 144, the logic conversion unit.
  • the noise shaping circuit 122 converts the output signal +1, 0, -1 three-value level into two differential digital signals 125, 126 suitable for driving the half-bridge power conversion circuit as the output of the noise shaping circuit 122.
  • the noise shaping circuit 122 can further move the quantization noise outside the passband, and the out-of-band noise can be filtered by the subsequent filter. Through the noise shaping circuit 122, the in-band noise is minimized, and the signal-to-noise ratio of the output signal is improved. Since the final output of the class D power amplifier must pass through a band pass or low pass filter, the noise shaping circuit 122 exists to move the noise inside the filter band out of the filter band, and the noise after passing through the filter is reduced. Therefore, the function of noise shaping is realized.
  • the above-mentioned data subjected to noise shaping processing is sent to the dead zone control circuit 123, and its composition is as shown in FIG. 6.
  • the dead zone control circuit 123 is designed to prevent the two output switching transistors in the half bridge circuit 157 from being turned on at the same time, thereby causing a very large current and a corresponding increase in power consumption.
  • the dead zone control circuit 123 includes a NOR gate 151 and a NAND gate 152, two NOT gate delay units 153, 154, two power stage drive circuits 155, 156 and a half bridge circuit 157, which are output by the noise shaping circuit 122.
  • the two differential digital signals enter the NOR gate 151 and the NAND gate 152, respectively, and then the data output from the NOR gate 151 and the NAND gate 152 are delayed by the non-gate delay units 153 and 154, respectively.
  • the output data of the delay units 153, 154 respectively enters the power stage driving circuits 155 and 156 for power amplification, and the amplified signal is used to control the half bridge circuit 157 to finally form a processed differential output signal.
  • the NOR gate 151 and the NAND gate 152 and the subsequent two NOT gate delay units 153 and 154 constitute an RS flip-flop 159, and the final RS flip-flop 159 generates a difference of two overlapping offsets.
  • the digital signal boosts the half bridge circuit 157 efficiently.
  • the dead zone control circuit 123 is used to prevent the two switching transistors in the half bridge circuit 157 from being turned on at the same time, so that the power supply is short-circuited and the circuit is burned.
  • the differential digital signals processed by the dead zone control enter the power stage driving circuits 124, 125, respectively, for power
  • the data output by the power stage driving circuit is a three-value level, and the original signal is recovered by the band pass filter 126; the transformer 127 in FIG. 3 is mainly for power line transmission, and the data is amplified by the transformer and output to the power line to drive the load. 128.
  • FIG. 7 shows a specific implementation circuit diagram of an output bandpass filter 127.
  • the bandpass filter 127 uses a simple LC filter 164, 165 to recover the original signal.
  • the input signal is bandpass filtered through two inductors 161, 164, two capacitors 162, 165, and two resistors 163, 166.
  • the specific component values are determined by the signal requirements, and the output of the final bandpass filter drives the load. 128 achieves the function of the entire power amplification.
  • the present invention improves the analog part of the conventional class D power amplifier into a digital mode, and the digital power amplifier mainly performs power amplification on the input low frequency signal, and since the amplifier realizes using the class D method, the final The output transistor works in the non-linear region and is only used as a switch. Its voltage and current characteristics are shown in Figure 8. The current and voltage always have a value of approximately 0, so the power consumption PVXI is also approximately 0, compared to the conventional linear power amplifier transistor. Working in the linear region can greatly improve efficiency, and it has great benefits for improving the power consumption of the system.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

Amplificateur de puissance numérique de communication sur porteuse basse tension comprenant un circuit de commande de niveau de puissance, un filtre passe-bande et un transformateur. Cet amplificateur comporte également un filtre de sur-échantillonnage servant à convertir un signal numérique de porteuse basse tension devant être amplifié en signal de fréquence d'échantillonnage supérieure, un circuit de mise en forme de bruit servant à supprimer le bruit dudit signal numérique et à sortir deux signaux différentiels, un circuit de contrôle de zone morte servant à traiter les deux signaux différentiels en deux bruits respectifs se chevauchant et décalés. L'extrémité d'entrée du circuit de mise en forme de bruit est couplée à l'extrémité de sortie du filtre de sur-échantillonnage, l'extrémité de sortie dudit circuit de mise en forme de bruit est couplée à l'extrémité d'entrée du circuit de contrôle de zone morte et l'extrémité de sortie dudit circuit de contrôle est couplée à l'extrémité d'entrée du circuit de commande de niveau de puissance.
PCT/CN2006/003081 2005-11-16 2006-11-16 Amplificateur de puissance numerique applique a une communication sur porteuse basse tension WO2007056949A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200510110392.8 2005-11-16
CNB2005101103928A CN100472946C (zh) 2005-11-16 2005-11-16 一种适用于电力线载波通信的数字功率放大器

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WO2007056949A1 true WO2007056949A1 (fr) 2007-05-24

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109752608A (zh) * 2017-11-01 2019-05-14 恩智浦有限公司 负载检测器
CN111224625A (zh) * 2020-01-22 2020-06-02 青岛中加特电气股份有限公司 一种差分音频功率放大电路

Families Citing this family (9)

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US7973596B2 (en) * 2009-05-12 2011-07-05 Number 14 B.V. Low-noise, low-power, low drift offset correction in operational and instrumentation amplifiers
CN102186130B (zh) * 2011-02-23 2017-07-07 启攀微电子（上海）有限公司 一种摆率控制驱动电路
CN102324273A (zh) * 2011-05-30 2012-01-18 上海湘湘电子有限公司 一种多功能多层绝缘线
US9876501B2 (en) * 2013-05-21 2018-01-23 Mediatek Inc. Switching power amplifier and method for controlling the switching power amplifier
CN103973242B (zh) * 2014-05-21 2017-04-19 瑞斯康微电子（深圳）有限公司 一种电力线载波功率放大电路
CN104617913B (zh) * 2015-02-10 2017-05-31 东南大学 一种射频高q值带通滤波器
CN110463034B (zh) * 2017-03-27 2021-02-09 华为技术有限公司 数字功率放大器
CN111030730A (zh) * 2019-12-05 2020-04-17 国网天津市电力公司电力科学研究院 一种低压电力线噪声录制及注入系统
CN111162741B (zh) * 2019-12-23 2023-07-25 上海船舶电子设备研究所(中国船舶重工集团公司第七二六研究所) 一种数字功率放大器及匹配滤波方法

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JPH04207817A (ja) * 1990-11-30 1992-07-29 Matsushita Electric Ind Co Ltd オーバーサンプリング型ｄａ変換器
US5959501A (en) * 1998-01-14 1999-09-28 Harris Corporation Class D amplifier with scaled clock and related methods
CN1257343A (zh) * 1998-11-18 2000-06-21 英特赛尔公司 一种低噪声、低失真的d类放大器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04207817A (ja) * 1990-11-30 1992-07-29 Matsushita Electric Ind Co Ltd オーバーサンプリング型ｄａ変換器
US5959501A (en) * 1998-01-14 1999-09-28 Harris Corporation Class D amplifier with scaled clock and related methods
CN1257343A (zh) * 1998-11-18 2000-06-21 英特赛尔公司 一种低噪声、低失真的d类放大器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109752608A (zh) * 2017-11-01 2019-05-14 恩智浦有限公司 负载检测器
CN109752608B (zh) * 2017-11-01 2023-07-28 恩智浦有限公司 负载检测器
CN111224625A (zh) * 2020-01-22 2020-06-02 青岛中加特电气股份有限公司 一种差分音频功率放大电路
CN111224625B (zh) * 2020-01-22 2023-04-07 青岛中加特电气股份有限公司 一种差分音频功率放大电路

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CN100472946C (zh) 2009-03-25
CN1968007A (zh) 2007-05-23

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