WO2007055263A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2007055263A1
WO2007055263A1 PCT/JP2006/322339 JP2006322339W WO2007055263A1 WO 2007055263 A1 WO2007055263 A1 WO 2007055263A1 JP 2006322339 W JP2006322339 W JP 2006322339W WO 2007055263 A1 WO2007055263 A1 WO 2007055263A1
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WO
WIPO (PCT)
Prior art keywords
wire
semiconductor device
loop
bonding
wires
Prior art date
Application number
PCT/JP2006/322339
Other languages
English (en)
French (fr)
Inventor
Kenzo Ide
Original Assignee
Tatsuta Electric Wire & Cable Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tatsuta Electric Wire & Cable Co., Ltd. filed Critical Tatsuta Electric Wire & Cable Co., Ltd.
Publication of WO2007055263A1 publication Critical patent/WO2007055263A1/ja

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    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a semiconductor device in which a semiconductor element such as an IC or LSI (hereinafter referred to as “semiconductor element”) and a lead frame are connected by a bonding wire (hereinafter simply referred to as “wire” t).
  • semiconductor element such as an IC or LSI
  • wire hereinafter simply referred to as “wire” t).
  • Patent Document 1 and Patent Document 2 as prior arts related to a semiconductor device in which a semiconductor element and a lead frame are connected by a wire.
  • Patent Document 1 Japanese Patent No. 2501303 (Claims and Drawings)
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2002-280410 (summary and selection drawing)
  • Patent Document 1 described above attempts to obtain a semiconductor device having good conductive characteristics by performing good ball bonding using a wire made of a copper alloy with a specific trace element added based on copper.
  • a bump having an inclined wedge is formed on the second conductor (lead frame) side during the bonding operation, and secondary bonding is performed on the inclined wedge to form a strong loop with a low height.
  • the semiconductor device 10 is required to have higher functionality, smaller size, and higher integration.
  • the pitch of the wires 13 becomes finer, and the semiconductor element 12 is laminated with a stronger force.
  • the wires 13 are arranged three-dimensionally to further radiate.
  • the bonded wire 13 forms a regular loop so that it does not interfere with the adjacent wire, and the formed loop is deformed at the time of injection of the resin. So that they do not interfere with adjacent wires.
  • the wire In order for the wire to form a regular loop, the wire must be homogeneous over its length, and the formed loop should not be deformed by the external force of resin injection. It is necessary to give the wire a certain strength, and to make it as low as possible instead of the conventional high mountain loop.
  • An object of the present invention is to provide a semiconductor device in which the wire cost is reduced in the semiconductor device based on the above knowledge, the bonding condition is good, and the shape of the loop is improved.
  • the present invention provides a semiconductor in which a wire is connected by performing a primary bond on the lead frame side, and a wire is connected by performing a secondary bond on the bond pad side of the semiconductor element while forming a loop.
  • gold or gold alloy bumps are formed on the bond pad, and copper or copper alloy wire is adopted as the wire.
  • FIG. 1 is an explanatory diagram of the bonding procedure of the present invention.
  • a highly integrated semiconductor device has three semiconductor elements 12 stacked on a substrate 14 via an insulating layer 15 in a stepped manner, and each bond pad 16 corresponds to each of them.
  • the lead frame 11 is connected with the wire 13.
  • the semiconductor element has a three-layer / staircase structure, but the number of layers and the form of arrangement are not limited.
  • connection between the lead frame 11 and the bond pad 16 of the semiconductor element 12 by the wire 13 is performed by applying gold or gold alloy bumps 17 on the bond pad 16 in advance as shown in FIG. Make a primary bond A and move the capillaries to draw the loop R and lead the wire 13 to the metal or gold alloy bump 17 while making the secondary bond B.
  • the wire used here is 25 ⁇ manufactured using high-purity copper, and the semiconductor device bonded as described above has a bonding status, a loop formation status, and a loop maintenance. It was confirmed that good results were obtained with any of the shape forces. In addition, the same results as described above were obtained with the copper alloy wire 25 ⁇ of phosphorous of Patent Document 1 as the copper alloy wire.
  • the cost of the wire can be reduced, the bonding condition is good, the loop shape and the shape retaining force are good, and the industrial utility value is extremely high. is there.

Abstract

 ワイヤのコストダウンを図り、ボンディング状況が良好でループの形状・保形力を向上させた半導体装置を提供する。  リードフレーム１１に一次ボンドＡによりワイヤ１３を接続し、ループＲを形成しながら半導体素子１２のボンドパッド１６に、二次ボンドＢによりワイヤ１３を接続してなる半導体装置１０において、上記ワイヤ１３として銅または銅合金線を採用し、半導体素子１２のボンドパッド１６に金または金合金バンプ１７を形成してなる。

Description

明 細 書
半導体装置
技術分野
[0001] この発明は、 ICあるいは LSIなどの半導体素子 (以下、「半導体素子」という）と リードフレームとをボンディングワイヤ（以下、単に「ワイヤ」 t 、う）で接続した半導体 装置に関する。
背景技術
[0002] 半導体素子とリードフレームとをワイヤで接続した半導体装置に関する先行技術と して特許文献 1および特許文献 2がある。
[0003] 特許文献 1 :特許第 2501303号公報 (特許請求の範囲および図面）
[0004] 特許文献 2：特開 2002— 280410号公報（要約および選択図面）
発明の開示
発明が解決しょうとする課題
[0005] 上記特許文献 1は、銅をベースとする特定の微量元素を添加した銅合金を素材と するワイヤを用いて、良好なボールボンディングを行い、導電特性の良い半導体装 置を得ようとするもので、特許文献 2は、ボンディング操作に際し第 2導体 (リードフレ ーム)側に傾斜ゥエッジを有するバンプを形成し、この傾斜ゥエッジ上に二次ボンディ ングして高さが低く強いループを形成しょうとするもので、こうした技術動向は半導体 装置の高機能化 ·高集積ィ匕を実現するためのものである。
[0006] 今日、半導体装置 10には、高機能化、小型化 ·高集積ィ匕が求められ、図 2に示す ようにワイヤ 13のピッチが一層細密になり、し力も半導体素子 12を積層して図 3に示 すようにワイヤ 13が三次元的に配置されて一層輻湊することとなっている。
[0007] 上記状態になると、ボンディングされたワイヤ 13が規則的なループを形成して隣接 するワイヤと干渉し合わないように、また、形成されたループが後工程ゃ榭脂注入時 に変形して隣接するワイヤと干渉し合わな 、ようにする必要がある。
[0008] ワイヤが規則的なループを形成するには、ワイヤが長さ方向に亘つて均質であるこ と、形成されたループが後工程ゃ榭脂注入の外力によって変形しな ヽようにするに はワイヤに一定の強度与えること、また、従来のように高い山のループではなくできる だけ低い山のループとすること、が必要になる。
[0009] こうした!/、ろ!/、ろな角度からの検討の過程で、リードフレーム側で一次ボンドを行！ヽ 、半導体素子側で二次ボンドをする逆ボンド方式が試みられている。このようにすれ ばトーチを備えたキヤビラリ一の移動経路との関係から、ワイヤのループを低くするこ とができ、また、従来力 金合金ワイヤの代替として安価に銅ワイヤは知られているが 、銅は金より硬 、特性を有することから半導体素子へのボンディング時にチップ割れ が発生する場合があるのを半導体素子側のボンドパッド部に金または金合金バンプ を形成することにより、ボンディング時、半導体素子に加わる押圧力を軽減できる効 果が得られることが判明し、金合金線に代えて銅または銅合金線を使用できる可能 '性がでてきた。
[0010] 上記知見をもとに半導体装置において、ワイヤのコストダウンを図り、ボンディング 状況が良好でループの形状'保形力を向上させた半導体装置を提供することを課題 する。
課題を解決するための手段
[0011] 上記状況に鑑みこの発明は、リードフレーム側に一次ボンドを行ってワイヤを接続 し、ループを形成しながら半導体素子のボンドパッド側に二次ボンドを行ってワイヤを 接続してなる半導体装置にぉ 、て、上記ボンドパッド上に金または金合金バンプを 形成し、上記ワイヤとして銅、または銅合金線を採用してなる。
発明の効果
[0012] 上記の如く構成するこの発明によれば、金合金線より安価な銅または銅合金線を 使用してもチップ割れが発生する恐れがない。また、銅の硬い特性力 ボンディング されたワイヤのループ形状が均一で蛇行がなぐループの保形力が大きくなつて後 工程ゃ榭脂注入時にループが変形して隣接するワイヤとの干渉が起きる恐れがない 図面の簡単な説明
[0013] [図 1]本発明のボンディング手順説明図
[図 2]輻湊するボンディング状況説明図 [図 3]多層化した半導体装置の部分断面図
符号の説明
[0014] 10 半導体装置
11 リードフレーム
12 半導体素子
13 ワイヤ
14 基板
15 絶縁層
16 ボンドパッド
17 金または金合金バンプ
A 一次ボンド
B 二次ボンド
R ループ
発明を実施するための最良の形態
[0015] 次にこの発明の実施の形態を、図面を参照しながら説明する。高集積ィ匕した半導 体装置は図 3に示すように基板 14上に絶縁層 15を介して半導体素子 12を三層重ね て階段状に配置し、それぞれのボンドパッド 16と、それに対応するリードフレーム 11 とをワイヤ 13で繋いでいる。なお、図 3では半導体素子を三層 ·階段構造にしている が層数および配置の形態は限定されな 、。
[0016] 上記リードフレーム 11と半導体素子 12のボンドパッド 16とのワイヤ 13による接続は 、図 1に示すようにボンドパッド 16上に予め金または金合金バンプ 17を施した後リー ドフレーム 11側に一次ボンド Aを行 、、図示しな!、キヤピラリーを移動させながらルー プ Rを画き金または金合金バンプ 17にワイヤ 13を導き二次ボンド Bを行う。
[0017] この手順でワイヤ 13を接続すると金または金合金バンプ 17によってボンドパッド 16 にかかる押圧力が軽減される。また、形成されるワイヤのループ Rが低くなり、保形力 が大きくなつて後工程ゃ榭脂注入時にループが変形するのを防止することができる。
[0018] ここで使用したワイヤは高純度銅を使用して製作した 25 μ ΐη φであり上記のように ボンディングした半導体装置は、ボンディング状況、ループの形成状況、ループの保 形力のいずれも良好な結果が得られることを確認した。また、銅合金線として特許文 献 1のリン入り銅 25 μ ΐη φでも前記と同様の結果が得られた。
産業上の利用可能性
以上説明した通りこの発明によれば、ワイヤのコストダウンを図ることができ、ボンデ イング状況が良好で、ループの形状、保形力も良好であって産業上の利用価値は極 めて高いものである。

Claims

請求の範囲
リードフレームに一次ボンドによりボンディングワイヤを接続し、ループを形成しなが ら半導体素子のボンドパッドに二次ボンドによりボンディングワイヤを接続してなる半 導体装置において、上記ボンドパッド上に金または金合金バンプを形成し、上記ボン デイングワイヤとして銅または銅合金線を採用したことを特徴とする半導体装置。
PCT/JP2006/322339 2005-11-10 2006-11-09 半導体装置 WO2007055263A1 (ja)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2133915A1 (de) * 2008-06-09 2009-12-16 Micronas GmbH Halbleiteranordnung mit besonders gestalteten Bondleitungen und Verfahren zum Herstellen einer solchen Anordnung
CN103811446A (zh) * 2012-11-15 2014-05-21 万国半导体(开曼)股份有限公司 一种半导体器件中的铜线键接结构及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010258286A (ja) * 2009-04-27 2010-11-11 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150836A (ja) * 1985-12-25 1987-07-04 Hitachi Ltd 半導体装置
JP2002237499A (ja) * 2001-02-09 2002-08-23 Mitsubishi Electric Corp 半導体装置の製造方法、半導体装置の製造装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150836A (ja) * 1985-12-25 1987-07-04 Hitachi Ltd 半導体装置
JP2002237499A (ja) * 2001-02-09 2002-08-23 Mitsubishi Electric Corp 半導体装置の製造方法、半導体装置の製造装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2133915A1 (de) * 2008-06-09 2009-12-16 Micronas GmbH Halbleiteranordnung mit besonders gestalteten Bondleitungen und Verfahren zum Herstellen einer solchen Anordnung
CN103811446A (zh) * 2012-11-15 2014-05-21 万国半导体(开曼)股份有限公司 一种半导体器件中的铜线键接结构及其制造方法

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