WO2007043205A1 - Irradiation unit, method of irradiation and semiconductor device - Google Patents

Irradiation unit, method of irradiation and semiconductor device Download PDF

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Publication number
WO2007043205A1
WO2007043205A1 PCT/JP2006/308543 JP2006308543W WO2007043205A1 WO 2007043205 A1 WO2007043205 A1 WO 2007043205A1 JP 2006308543 W JP2006308543 W JP 2006308543W WO 2007043205 A1 WO2007043205 A1 WO 2007043205A1
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Prior art keywords
wavelength
film
insulating film
light
irradiation
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PCT/JP2006/308543
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French (fr)
Japanese (ja)
Inventor
Yoshimi Shioya
Original Assignee
Yatabe Massao
Okumura Masaru
Yoshimi Shioya
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Application filed by Yatabe Massao, Okumura Masaru, Yoshimi Shioya filed Critical Yatabe Massao
Priority to JP2007539812A priority Critical patent/JPWO2007043205A1/en
Publication of WO2007043205A1 publication Critical patent/WO2007043205A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • H01L21/67115Apparatus for thermal treatment mainly by radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si

Definitions

  • Irradiation apparatus Irradiation apparatus, irradiation method, and semiconductor device
  • the present invention relates to an irradiation apparatus, an irradiation method, and a semiconductor device.
  • a semiconductor device includes various insulating films.
  • These insulating films include an IC interlayer insulating film (for example, a low dielectric constant film (hereinafter referred to as “Low-k film”), a noria insulating film of a wiring material formed between wirings, and a high dielectric constant.
  • Gate insulation film hereinafter referred to as “High-k film”.
  • SiN, SiON, SiOCH, SiOCNH, SiCH, SiCNH, SiOCF, SiCF, etc. are used as the material of the insulation film .
  • Low-k films are required to have a low dielectric constant and high mechanical strength.
  • One way to achieve a low dielectric constant is to perform a thermal annealing on the low-k film.
  • One method for realizing high mechanical strength is to perform ultraviolet light irradiation treatment as described in Patent Document 1.
  • the thermal annealing treatment is required to be performed at a temperature of 400 ° C or higher for 30 minutes or longer.
  • the ultraviolet light irradiation treatment is required to irradiate ultraviolet light having a wavelength of 200 nm or less.
  • the barrier insulating film is required to be uniform and highly dense, but there is also a demand for a thin film.
  • the high-k film (HfO film) is dense and can cause leakage current to flow.
  • annealing treatment after high-k film formation is important.
  • a high-k film has been formed by metal organic chemical vapor deposition (MOCVD) or the like. Specifically, prior to formation of the high-k film, heating is performed at a temperature of 425 ° C. while supplying O gas onto the silicon.
  • MOCVD metal organic chemical vapor deposition
  • a boundary layer is formed by metalorganic chemical vapor deposition at a temperature of 450 ° C to 550 ° C. After that, at a temperature of 700 ° C to 900 ° C, N
  • Non-patent Documents 1 and 2 By supplying N 2 / O 2 2 or NH gas, the Si—O bond silicon in the high-k film is replaced with nitrogen. Perform SiN (Nation) to form SiN bond. Further, annealing is performed in argon (Ar) (Non-patent Documents 1 and 2).
  • Patent Document 1 JP 2004-356508 A
  • Non-Patent Document 1 IEEE Electron Devices 52, pl839 (2005).
  • Non-Patent Document 2 The Electrochemical Society Interface, Summer 2005, p30 (2005). Disclosure of the Invention
  • the low-k film has a problem in that although the mechanical strength is improved, the dielectric constant is also increased.
  • the Young's modulus which is the mechanical strength, becomes 8 GPa.
  • the dielectric constant is 2.6. More than that.
  • the thermal annealing treatment is performed at a temperature as high as 400 ° C for 30 minutes or more.
  • wiring materials such as copper (Cu) used in semiconductor devices are used.
  • the force ow— diffuses into the k film and increases the leakage current between wires.
  • the thermal annealing process takes more than 30 minutes, while other manufacturing processes for semiconductor devices take about 5 minutes. Therefore, when the thermal annealing process is performed, there is a problem that the manufacturing throughput of the semiconductor device is lowered.
  • an object of the present invention is to provide a semiconductor manufacturing apparatus capable of modifying an insulating film.
  • the irradiation apparatus of the present invention includes a first irradiation unit that irradiates the insulating film with ultraviolet light having a first wavelength;
  • Second irradiating means for irradiating the insulating film with ultraviolet light or visible light having a second wavelength different from the first wavelength.
  • one of the lights is light having a wavelength equal to or less than a wavelength necessary for cutting a bonding group that is not in a stable state in the insulating film, and the other of the lights Is light with a wavelength longer than the absorption edge.
  • the insulating film is an inter-wiring insulating film or a barrier insulating film
  • one of the lights is light having a wavelength equal to or shorter than a wavelength necessary for cutting a bonding group in the insulating film.
  • the other is light having a wavelength longer than the absorption edge.
  • one of the lights is light having a wavelength less than a wavelength necessary for the transition metal oxide or a wavelength necessary for breaking the CH bond.
  • the other of the lights is light having a wavelength longer than the absorption edge.
  • a semiconductor manufacturing apparatus of the present invention includes the irradiation apparatus and a transfer apparatus that transfers a wafer having the insulating film.
  • the first and second irradiation means may be provided in the same chamber, or may be provided in different chambers.
  • the semiconductor device of the present invention when manufactured by a chemical vapor deposition apparatus, the semiconductor device includes an insulating film having a dielectric constant of 2.4 or less and a Young's modulus of 5 GPa or more.
  • the semiconductor device of the present invention When the semiconductor device of the present invention is manufactured by a semiconductor device spin coating film forming apparatus, the semiconductor device includes an insulating film having a dielectric constant of 2.3 or less and a Young's modulus of 6 GPa or more.
  • the irradiation method of the present invention includes a first irradiation step of irradiating the insulating film with ultraviolet light having a first wavelength
  • FIG. 1 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 1 of the present invention.
  • an apparatus for modifying a low-k film will be mainly described.
  • FIG. 1 shows a hoop 41 that accommodates a wafer, a wafer alignment 42 that positions a wafer taken out from the hoop 41, and a mouth-drop chamber that is a decompression chamber having a load lock mechanism. 43, a first chamber 1 that irradiates a wafer with relatively long wavelength light, a second chamber 2 that irradiates a wafer with relatively short wavelength light, and a low-lock chamber 43 And a transfer chamber 44 having a robot arm for transferring a wafer between the first chamber 11 and the second chamber 1.
  • FIG. 2 is a schematic configuration diagram of the first chamber 11 in FIG. Fig. 2 shows a number of light beams with a wavelength of 300 nm or more, such as a high-pressure mercury lamp determined by the material of the low-k film, or a wavelength of 400 nm or more and 770 nm or less, such as a halogen lamp Four lamps 3, quartz pipes 4 that protect each lamp 3 from stress applied during decompression and prevent oxygen from contacting each lamp 3, and nitrogen (N ) Inert gas such as gas 5 and semiconductor device covered with an insulator
  • a nozzle 14 provided between the pipes 11 and 12 and the gas tank, and a mass flow 13 for measuring the gas flow rate through the pipes 11 and 12 and controlling the opening and closing of the valve 14 according to the measurement results are shown. Yes. If necessary, an inert gas other than nitrogen is introduced into the first chamber 11. Make it available.
  • the configuration of the second chamber 12 is the same as that of the first chamber 11, but a low-pressure mercury lamp or an excimer lamp such as Xe, Kr, I, KrBr is used instead of each lamp 3. Yes.
  • the low-pressure mercury lamp has a relatively strong light with a wavelength of 186 nm when the base temperature of the lamp is around 60 ° C, and a relatively strong light with a wavelength of 254 nm when the temperature at the base of the lamp is 0 ° C. Is.
  • a lamp for irradiating light of the same wavelength may be provided in both the first chamber 11 and the second chamber 12.
  • the wafer 7 processed by the semiconductor manufacturing apparatus shown in FIG. 1 has a heating time twice that of the conventional one, so that the mechanical strength of the insulating film is increased. This is because an effect is obtained.
  • a visible light lamp, a xenon lamp, an argon laser, or a carbon dioxide gas laser can be used.
  • an excimer laser such as XeF, XeCl, XeBr, KrF, KrCl, ArF, or ArCl can be used for the lamp in the second chamber 12.
  • the lamp 3 needs to be able to irradiate light having a wavelength of 770 nm or less, that is, visible light, in order to cut a bonding group that is not in a stable state in the insulating film.
  • FIG. 3 is a diagram showing the relationship between the wavelength of irradiation light and the binding energy of a substance.
  • the horizontal axis in Fig. 3 is the wavelength (nm), and the vertical axis is the binding energy (eV).
  • SiOCH, SiCF, etc. can be used for the low-k film material, and SiN, SiOCH, SiON, SiOC NH, SiCNH film, etc. can be used for the Cu barrier film.
  • the bonding group When light having a wavelength of a little over nm is irradiated, the bonding group is cleaved. Therefore, when the SiOCH film is used as the insulating film, the bonding group can be cleaved by irradiating light with a wavelength of 350 nm or less.
  • the SiN film has N—H bonds and Si—H bonds. In these, the bonding group is cleaved when irradiated with light having wavelengths of about 3 OOnm and 400 nm, respectively. Therefore, when the SiN film is used as the insulating film, the above bonding group can be cleaved by irradiating light with a wavelength of 400 nm or less.
  • the present inventor has found that the dielectric constant of the low-k film can be lowered by reducing hydrogen components, fluorine components, and the like in an unstable bonding state in the low-k film. .
  • the present inventor has found that the inter-wiring insulating film and the like can be made uniform and high in density by cutting the hydrogen bonding group of the inter-wiring insulating film or the barrier insulating film. Furthermore, the present inventor irradiates the high-k film with light having a wavelength shorter than that required for the transition metal oxide or the wavelength necessary for breaking the C—H bond. UV annealing is performed in an inert gas atmosphere containing about 1 to 2%, preferably 1% or less of inert gas or O gas.
  • the high-k film can be made dense and the leakage current becomes a flow.
  • the insulating film can be modified to a state where the required conditions are cleared.
  • FIG. 4 is a diagram showing the relationship among the wavelength of irradiation light, the absorption edge, and the binding energy.
  • the horizontal axis is the wavelength (nm)
  • the left vertical axis is the absorption edge (eV)
  • the right vertical axis is the binding energy (eV).
  • the wavelength corresponding to the absorption edge of the SiO film is 156 nm. Therefore, the SiON film
  • the light When light with a wavelength of 156 nm or more is irradiated, the light enters the film, and as a result, the light is absorbed by the structure (bonding skeleton) in the film, increasing the density of the SiO film or SiON film, and mechanically. Strong
  • the degree becomes higher.
  • the wavelength corresponding to the absorption edge / absorption edge of SiN is 275.6 nm, when the SiN film is irradiated with light having a wavelength of 275.6 nm or more, the density of the SiN film is improved, or a hydrogen component, etc. Is removed.
  • FIG. 5 is a schematic cross-sectional view of a part of the wafer 7 shown in FIG. FIG. 5 shows a wiring layer 31 for transmitting signals in the semiconductor device, and a wiring layer 31 formed on the wiring layer 31!
  • a barrier insulating film 32 that barriers against leakage of water, and a low-k film 33 that is formed on the NORI-insulating film 32 and insulates the layer formed on the low-k film itself in a later step. Is shown.
  • the wiring layer 31 is made of Cu or the like, and has a thickness of about 200 to 300 nm.
  • the barrier one insulating film 32 is selected from materials such as SiOC, SiCH, SiOCH, and SiOCNH, and has a thickness of about 20 to 30 nm.
  • the low-k film 33 is made of SiOCH or the like and has a thickness of about 200 to 300 nm.
  • the procedure for the modification process of the low-k film 33 will be described by taking the wafer 7 selected as the SiOCH film power low-k film 33 as an example.
  • the CVD apparatus power in a clean room (not shown) is also transported while being accommodated in the hoop 41. Thereafter, the wafer is taken out from the hoop 41 and transferred to the wafer alignment 42 side.
  • the wafer alignment 42 the wafer is positioned. Thereafter, the wafer 7 is transferred to the load lock chamber 43 before being transferred to the first chamber 11.
  • the wafer 7 is transferred into the transfer chamber 44. Subsequently, the wafer 7 is transferred from the load lock chamber 43 to the first chamber 11 by the robot arm in the transfer arch yanber 44.
  • the wafer 7 is placed on the pins 8 protruding above the heater 6. Thereafter, the heater 6 is raised, and the wafer 7 placed on the pin 8 comes into direct contact with the heater 6. Then, prior to the irradiation of the light from the lamp 3, the wafer 7 is heated by heating at a heater 8 [thereby, f line, approximately 90 times f3 ⁇ 4, 350-400 ° C].
  • the inside of the first chamber 11 is evacuated by an evacuation means (not shown), and the valve 14 on the nitrogen gas side is opened by the mass flow 13 so that the inside of the first chamber 1 is in a nitrogen atmosphere.
  • the above heating is performed under the condition that the inside of the first chamber 11 becomes, for example, lTorr.
  • the opening / closing control of the nozzle 14 is controlled by the amount of nitrogen gas supplied to the first chamber 11 as an example. For example, it is performed under the condition of lOOccZ.
  • the inside of the first chamber 11 may be in a normal pressure state that is not in a reduced pressure state. If necessary, another inert gas may be supplied into the first chamber 11 instead of the N gas.
  • a mixed gas of N gas and other inert gas may be used.
  • the heater 8 is raised in a range where the distance between the wafer 7 and the lamp 3 is, for example, 100 to 200 mm so that the light irradiated from the lamp 3 reaches the wafer 7 without unevenness in intensity. Yes.
  • the illuminance of the lamp 3 is increased continuously or stepwise in a time of about 5 to: L0 seconds.
  • the increase in illuminance may be, for example, linear, exponential, or another form.
  • the wafer 7 is transferred from the first chamber 11 into the second chamber 2 by the transfer chamber 44.
  • Wafer 7 is processed in the second chamber 12 in the same manner as in the processing in the first chamber 1.
  • the condition for irradiating the wafer 7 from the low-pressure mercury lamp is that the illuminance is 3 mWZcm. 2
  • the irradiation time is 1 to 4 minutes.
  • an increase in the dielectric constant of the low-k film 33 can be suppressed, and the mechanical strength can be increased.
  • the wafer 7 taken out from the second chamber 12 has, for example, a low-k film 33 having a Young's modulus of about 5 GPa or more and a dielectric constant of 2.5 or less.
  • the Young's insulating film 32 has a Young's modulus of about 60 GPa, a dielectric constant of about 4.0, and a density of about 2.5 gZcm 3 .
  • FIG. 6 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic configuration diagram of the chamber 15 in FIG. In the present embodiment, the first chamber 1 and the second chamber 1 shown in FIG.
  • the chamber 15 includes a plurality of (for example, five) lamps 3 and a plurality of (for example, four) lamps 21.
  • the distance between the lamp 21 and the wafer 7 is about 100 mm when the chamber 15 is used.
  • the distance between the lamp 3 and the wafer 7 is about 120 mm.
  • the number of the lamps 3 and the low-pressure mercury lamps 21 may be the same, or the lamps 3 and 21 may be arranged two-dimensionally.
  • the wafer 7 may be irradiated with ultraviolet rays first from either the lamp 3 or the lamp 21.
  • the dielectric constant of the low-k film 33 could not be lowered and the mechanical strength could not be improved even when irradiated simultaneously.
  • the semiconductor device manufacturing process is the same as that in the first embodiment.
  • the respective irradiation times of the lamp 3 and the lamp 21 may be the same as those in the first embodiment. Under these conditions, the heating time of the wafer 7 before irradiation is 1 minute, the total irradiation time is 5 minutes, and the cleaning time is 1 minute. None to do! /
  • the processing of the low-k film 33 has been mainly described.
  • a process for increasing the stress of the SiN film of the strained silicon device will be described.
  • a technique using an insulating film in a semiconductor device is a strained silicon technique.
  • Strained silicon technology uses silicon germanium (SiGe) layers at the source and drain to increase the density of electrons and makes use of the property that the lattice of silicon atoms in the channel region under the gate tends to align with each other. This is a technology that increases the mobility of electrons by increasing the distance between the electrodes, reducing the collision of electrons and silicon atoms, which are responsible for source-drain current.
  • SiGe silicon germanium
  • the semiconductor manufacturing apparatus shown in FIG. 1 or 6 can also be used.
  • the lamp 3 an I lamp that irradiates light with a wavelength of 341 nm, for example,
  • an XeBr lamp that irradiates light with a wavelength of 282 nm or an XeCl lamp that irradiates light with a wavelength of 308 nm, for example, is used.
  • hydrogen is desorbed from the SiN film by the irradiation light from the I lamp, and the
  • the stress on the SiN film is increased by the irradiation light from the XeBr lamp.
  • FIG. 8 is a schematic cross-sectional view of a part of the wafer 7 shown in FIG. FIG. 8 shows a P-type silicon layer 51, an N-type region 52 formed in the P-type silicon layer 51, and a source region 53 and a drain region such as SiGe formed in the N-type region 52. 54, a gate insulating film 62 formed on the N-type well region 52, a gate electrode 55 formed on the gate insulating film 62, and a source region 58 and drain such as SiGe formed in the P-type silicon layer 51.
  • membrane 56, 61 On membrane 56, 61
  • a SiN film 57 to be a formed sidewall is shown.
  • the transistor on the source region 53 and drain region 54 side is a P-channel transistor, and the transistor on the source region 58 and drain region 59 side is an N-channel transistor.
  • Such a wafer 7 is formed by a diffusion furnace, an ion implantation apparatus, and a chemical vapor deposition system (CVD) apparatus.
  • This wafer 7 has a hydrogen component, etc. in the SiN film 57 due to the irradiation light from the I lamp.
  • the remaining hydrogen in the SiN film 57 is further removed by the irradiation light from the XeBr lamp, and the SiN film 57 is almost completely free of hydrogen. As a result, the mechanical strength of the SiN film 57 is increased.
  • FIG. 9 is a schematic cross-sectional view after removing a part of the SiN film 57 of the wafer 7 shown in FIG. After the above light irradiation treatment, the P channel transistor side of the SiN film 57 is removed. Thus Create strained silicon devices.
  • the hydrogen concentration of the SiN cover insulating film can also be reduced, and the gate caused by hydrogen in the DRAM cover film can be reduced. Toe drain leakage current can be reduced and retention defects can be reduced.
  • FIG. 10 is a schematic configuration diagram of the first chamber 11 according to the fourth embodiment of the present invention.
  • This first chamber 11 is suitable when a halogen lamp having a wavelength of 400 nm or more is used.
  • the cooling water 2 is used to cool the halogen lamp 3.
  • the halogen lamp 3 removes hydrogen by heating the insulating film on the Si wafer in a short time by the light of the lamp.
  • UV light is irradiated from a 308 nm XeCl lamp in the second chamber 12 to increase the stress.
  • FIG. 11 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 5 of the present invention. Here, an example in which a low-k film is formed using an SOD film will be described.
  • an SOD film is applied, for example, to 500 nm on a wiring formed on a wafer having a thickness of 300 ⁇ m.
  • the wafer is transferred to a chamber 102 having a beta stage for blowing off the solvent of the SOD film, and the solvent is blown off by performing beta at a temperature of about 200 ° C.
  • the wafer is then transferred to a chamber 103 equipped with a cure stage to drive off solvent and porogen or to harden the film, and a beta for 5 minutes at a temperature of about 400 ° C. Do.
  • the film is densified, for example, by blowing off the solvent or porogen in the SOD film.
  • the same processing as in the first embodiment is performed.
  • the low-k film has a dielectric constant of 2.3 or less and a Young's modulus of 6 GPa or more.
  • FIG. 12 is a schematic cross-sectional view of a part of a wafer 7 that is a semiconductor device according to Embodiment 6 of the present invention.
  • UV annealing is applied to the high-k film 73 in wafer 7. explain about.
  • This wafer 7 is formed on a silicon wafer 71, for example, a lnm-thick SiO-rich boundary layer 7
  • a high-k film 73 having a force such as HfO is provided on the boundary layer 72.
  • an electrode 74 having a force such as polysilicon is formed on the high-k film 73.
  • the high-k film 73 is formed by supplying N gas ZO gas for about 10 minutes at a temperature of 800 ° C., for example.
  • light is irradiated for about 2 to 4 minutes at an illuminance of about 5 to 15 mWZcm 2 from four XeC 1 lamps having a wavelength of about 308 nm separated from the wafer by 100 to 200 mm.
  • the first chamber 1 and the second chamber 1 are various inert gas atmospheres including a reduced pressure state with a pressure of about lTorr, a temperature of about 500 ° C, and nitrogen gas.
  • the cleaning is performed by supplying an oxygen gas supply amount at a rate of, for example, 100 ccZ under a reduced pressure of about lTorr and turning on the UV lamp. After that, for example, the forming gas (N gas ZH gas) treatment is performed at 425 ° C for about 30 minutes.
  • an oxygen gas supply amount at a rate of, for example, 100 ccZ under a reduced pressure of about lTorr and turning on the UV lamp.
  • the forming gas (N gas ZH gas) treatment is performed at 425 ° C for about 30 minutes.
  • the charge density in the boundary layer 72 can be reduced to 1 ⁇ 10 12 Zcm 3, and the leakage current of the HfO film can also be reduced.
  • bonding groups related to hydrogen such as H-N and H-Si.
  • the wavelengths required to cleave these bonding groups are 353 nm and 399 nm, respectively. Also, about 240 nm is the wavelength corresponding to the absorption edge. Therefore, when the SiN film is irradiated with light having a wavelength of 180 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be decreased.
  • bonding groups related to hydrogen such as H—N, C—H, and H—Si.
  • the wavelengths required to cleave these linking groups are 353 nm, 353 nm, and 399 nm, respectively. Moreover, about 265 nm is a wavelength corresponding to the absorption edge. For these reasons, when the SiC H film is irradiated with light having a wavelength of 180 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be decreased.
  • a SiOCNH film there are hydrogen-related bonding groups such as H-0, H-N, C-H, and H-Si.
  • the wavelengths necessary to cleave these bonding groups are 280 ⁇ m, 353nm, 353nm, and 399nm, respectively.
  • the wavelength corresponding to the absorption edge is about 156 to 263 nm, but the wavelength corresponding to the absorption edge is considered to be about 180 nm considering that the concentration of C and N is more than a few percent. Therefore, when the SiOCNH film is irradiated with light having a wavelength of 180 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be decreased.
  • the SiOCH film there are bonding groups related to hydrogen such as H-0, H-N, C-H, H-Si.
  • the wavelengths necessary for cleaving these bonding groups are 280 nm, 353 nm, 353 nm, and 399 nm, respectively.
  • the wavelength corresponding to the absorption edge is about 156 nm.
  • FIG. 17 is a schematic configuration diagram of the prevention ring 8A for preventing the positional deviation of the wafer 7 provided in the first chamber 11 and the second chamber 12. As shown in FIG. FIG. 17 also shows the wafer 7 and the heater 6 described above!
  • the first chamber 1 and the second chamber 1 according to Embodiment 8 of the present invention prevent the wafer 7 from being misaligned due to static electricity.
  • the prevention ring 8A may be a static elimination ring.
  • the prevention ring 8A is used on the heater 6 so as to surround the periphery of the wafer 7.
  • the chamber 1 is provided with a sensor for detecting this positional deviation. Therefore, when the positional deviation exceeds a predetermined amount, the sensor reacts to stop the manufacturing process. As a result, continuous processing cannot be performed, and manufacturing throughput is reduced.
  • the prevention ring 8A is provided in the first chamber 11 and the second chamber 12 so that the sensor does not react even if the wafer 7 is displaced, thereby preventing the wafer 7 from being attached to the prevention ring 8. It can be stopped by the inner wall of A.
  • the neutralizing ring 8A at least the surface may be made of polysilicon, single crystal silicon, aluminum, or the like.
  • the shape of the static elimination ring 8A is not limited to the mode shown in FIG. 17, and may be, for example, a rectangular parallelepiped or a cuboid.
  • This type of static eliminator may be placed on the heater 6 at a position that does not interfere with the loading and unloading of the wafer 7.
  • FIG. 18 if a plurality of substantially rainbow-shaped neutralization ring pieces 8B are used, the wafer 7 is easily carried into the position surrounded by the static elimination ring pieces 8B. Is unlikely to occur. Whether it is a static elimination body such as a rectangular parallelepiped or the static elimination ring piece 8B, it is easier to create than the static elimination ring 8A.
  • the generated static electricity can be removed, it is not essential to provide the static elimination ring 8A or the like.
  • the static elimination pin may be made of at least a surface such as polysilicon, single crystal silicon, or aluminum.
  • a polysilicon thin film, amorphous silicon thin film, SiN thin film, SiC film, or SiOC film can be formed on the surface of the heater 6 or the like.
  • the thickness of the thin film is not limited. As an example, the thickness of the thin film can be about 500 to 10,000 angstroms.
  • a polysilicon thin film is formed by plasma CVD, sputtering, or low pressure CVD, for example, by applying a high frequency 562 W of 380 KHz to the heater 6 under a substrate temperature surface of 350 ° C and a pressure of 0.6 Torr. Approx. 5,000 to 10,000 angstroms by flowing SiH at 100cc / min
  • SiN thin film is formed by plasma CVD method, sputtering method or low pressure CVD method, for example, applying high frequency 562W of 380KHz to heater 6, substrate temperature surface 350 ° C, pressure 0.6 Torr environment, SiH 100ccZmin
  • a thickness of 3000 to 5000 angstroms can be formed.
  • FIGS. 19 to 21 are views showing a modification of the manufacturing process of the wafer 7 shown in FIGS.
  • a P-channel transistor a transistor on the source region 53 and drain region 54 side of the wafer 7, that is, a P-channel transistor.
  • UV light of low-pressure mercury is irradiated to the P-channel transistor and N-channel transistor for 5 minutes at 400 ° C and illuminance of 14 mWZcm2, for example (Fig. 19).
  • the SiN film 57 on the N-channel transistor side has a tensile stress of about 1.5 GPa. It becomes.
  • the conditions of the ultraviolet light absorbing material are not limited to polysilicon as long as it has a band gap for realizing the absorption and can withstand the heating of about 400 ° C.
  • the polysilicon thin film 64 formed on the P-channel transistor is removed (FIG. 20). As a result, only the SiN film 57 on the N channel transistor side is subjected to tensile stress.
  • the N channel transistor is covered with a thick resist film 65, and N + ions are implanted into the center of the SiN film 57 on the P channel transistor side, for example, at a dose of 5 X 1015 using an ion implanter (Fig. 21). ).
  • the SiN film 57 on the N channel transistor side is protected by the resist film 65, the stress does not change.
  • the SiN film 57 on the P channel transistor side is stressed and becomes about lGPa.
  • the wafer 7 shown in FIG. 8 is obtained.
  • the semiconductor device was actually manufactured through the low-k film 33 treatment under the following conditions.
  • Lamp 1 in the first chamber 3 Four high-pressure mercury lamps with a wavelength of about 300 nm to 770 nm, illumination of about 8 mWZcm 2 , irradiation time of about 4 minutes,
  • Low pressure mercury lamp in the second chamber 4 lamps with wavelengths of about 186 nm and about 254 nm, illuminance of about 3 mWZcm 2 , irradiation time of about 1 minute,
  • 1st chamber 1 and 1st chamber 2 lTorr depressurized condition, temperature of about 400 ° C, various inert gas atmospheres including nitrogen gas, cleaning, and cleaning conditions under lTorr depressurized! / Large oxygen gas supply volume for lOOccZ,
  • Wafer 7 A SiOCH film with a diameter of about 300 mm and a thickness of about 300 nm is formed!
  • the Young's modulus indicating the mechanical strength of the wafer 7 was 8 GPa.
  • the dielectric constant was 2.4.
  • low-k film 33 under the following conditions: Through these processes, a semiconductor device was actually manufactured.
  • Lamp 3 Four high-pressure mercury lamps with a wavelength of about 300 nm to 770 nm, illuminance of about 4 mW / cm 2 , irradiation time of about 4 minutes,
  • Lamp 21 4 low-pressure mercury lamps with wavelengths of about 186 nm and 254 nm, illuminance of about 3 mW / cm 2 , irradiation time of about 1 minute,
  • Chamber 1 lTorr decompression state, temperature is about 250 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply rate is lOOcc / min under cleaning conditions of lTorr decompression,
  • Wafer 7 A SiOCH film with a diameter of about 300 mm and a thickness of about 300 nm is formed!
  • the Young's modulus indicating the mechanical strength of the wafer 7 was 8 GPa.
  • the dielectric constant was 2.4.
  • a semiconductor device was actually manufactured by processing the SiN film 57 under the following conditions using the semiconductor manufacturing apparatus shown in FIG. 1 or FIG.
  • Lamp 1 in chamber 1 3 4 I lamps with a wavelength of about 341 nm, illuminance of about 13 mW
  • Lamp in the second chamber 12 4 XeBr lamps with a wavelength of about 282nm, illuminance of about 13m W / cm 2 , irradiation time of about 2 minutes,
  • 1st chamber l lTorr decompression state, temperature is about 400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount is lOOccZ for cleaning conditions under reduced pressure of lTorr,
  • Second chamber 1 lTorr decompression state, temperature is about 400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount is lOOccZ for lTorr under reduced pressure
  • Wafer 7 Diameter is about 300 mm, DRAM is formed, and the cover SiO film has a cover.
  • One SiN film force S is formed with a thickness of about 300 nm.
  • the hydrogen concentration in the cover SiN film 57 can be reduced, the leakage current in the DRAM gate-drain region can be reduced, and the data retention time can be increased.
  • the defective rate could be reduced.
  • a semiconductor device was actually manufactured by processing the SiN film 57 under the following conditions using the semiconductor manufacturing apparatus shown in FIG. 1 or FIG.
  • Lamp 1 in the first chamber 1 4 I lamps with a wavelength of about 341nm, illuminance of about 13mW
  • Lamp in the second chamber 1-2 4 XeCl lamps with a wavelength of about 308nm, illuminance of about 13m W / cm 2 , irradiation time of about 2 minutes,
  • 1st chamber l lTorr decompression state, temperature is about 250 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount is lOOccZ for lTorr under reduced pressure cleaning condition
  • Second chamber 1 lTorr decompression state, temperature is about 350 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply volume is lOOccZ for cleaning conditions of lTorr decompression,
  • Wafer 7 A diameter of about 300 mm, DRAM is formed, and a sidewall SiN film is formed on the transistor with a thickness of about 300 nm!
  • the tensile stress was 2 X 10 9 dyneZcm 2 before the treatment, whereas 2 X 10 1G dyneZcm 2 was obtained after the treatment. It was tensile stress. As a result, the source / drain current increased.
  • the semiconductor device was actually manufactured through the low-k film 33 treatment under the following conditions.
  • Halogen lamp in the first chamber 4 lamps with a wavelength of about 400 or more and 770 nm or less, illuminance of about 15mWZcm 2 , irradiation time of about 2 minutes,
  • Low pressure mercury lamp in the second chamber 4 lamps with wavelengths of about 186 nm and about 254 nm, illumination intensity of about 3 mWZcm 2 , irradiation time of about 2 minutes,
  • 1st chamber 1 and 1st chamber 2 lTorr depressurized condition, temperature is about 400 ° C, various inert gas atmospheres including nitrogen gas, vacuum, cleaning conditions are lTorr depressurized /! Oxygen gas supply volume for lOOccZ minutes,
  • Wafer 7 A diameter of about 300 mm and a SiOCH film with a thickness of about 300 nm are formed!
  • the Young's modulus indicating the mechanical strength of the wafer 7 was 8 GPa.
  • the dielectric constant was 2.4.
  • the semiconductor device was actually manufactured through the processing of the SOD film 33 under the following conditions.
  • Lamp 1 in the first chamber 1 3 4 XeCl lamps with a wavelength of about 308 nm,
  • Illuminance is about 10mWZcm 2 , irradiation time is about 4 minutes,
  • Lamp in the second chamber 1-2 4 Xe lamps with a wavelength of about 172 nm, illuminance of about 4 mWZ cm 2 , irradiation time of about 1 minute,
  • 1st chamber 1 and 1st chamber 2 lTorr reduced pressure, temperature about 350 ° C, various inert gas atmospheres including nitrogen gas, cleaning, cleaning conditions lTorr reduced pressure! / Large oxygen gas supply volume for lOOccZ,
  • Wafer 7 A 300 mm diameter, SOD film 33 is formed with a thickness of about 300 nm!
  • the Young's modulus indicating the mechanical strength of the wafer 7 was 8 GPa.
  • the dielectric constant was 2.3.
  • the HfO film 33 is
  • Lamp 3 in the first chamber 1 4 XeCl lamps with a wavelength of about 308 nm, illuminance of about 10 mW / cm 2 , irradiation time of about 4 minutes,
  • Lamp in the second chamber 1-2 4 Xe lamps with a wavelength of about 172 nm, illuminance of about 4 mWZ cm 2 , irradiation time of about 1 minute,
  • 1st chamber 1 and 1st chamber 2 lTorr depressurized state, temperature is about 500 ° C, various inert gas atmospheres containing nitrogen gas, cleaning, cleaning conditions are lTorr depressurized! / Large oxygen gas supply volume for lOOccZ,
  • Wafer 7 SiO-rich boundary layer with a diameter of about 300mm and a thickness of about lnm, and on the boundary layer The formed HfO film having a thickness of about 5 nm is formed.
  • the charge density in the boundary layer could be reduced to 1 ⁇ 10 12 Zcm 3 and the leakage current of the HfO film could be reduced.
  • a semiconductor device was actually manufactured using the semiconductor manufacturing apparatus shown in FIG.
  • Lamp 4 KrCl lamps with a wavelength of about 222 nm, illuminance of about 4
  • Chamber 1 lTorr decompression state, temperature power of about 300-400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount of lOOccZ for cleaning conditions of lTorr decompression,
  • Wafer 7 Diameter is about 300 mm, and as shown in FIG. 13, a SiOC film 22, which is a barrier film having a thickness of about 3 Onm, is formed on the Cu wiring layer 21.
  • the modified SiOC film 22 is subjected to heat treatment at a temperature of about 400 ° C for 3 hours, the SiOC film 22 has a high density, so that almost no leakage current flows from the SiOC film 22. It did not flow.
  • a semiconductor device was actually manufactured using the semiconductor manufacturing apparatus shown in FIG.
  • a PE-CVDSiN film 24 deposited by force by opening a Noria insulating film 23 formed via a low-k film (SiOC film) 22 on the Cu wiring layer 21 shown in FIG.
  • SiOC film low-k film
  • Lamp 4 XeCl lamps with a wavelength of about 308 nm, illuminance of about 4-15 mWZcm 2 , irradiation time of about 1-2 minutes, distance to wafer 7 of about 10-20 cm,
  • Chamber 1 lTorr decompression state, temperature power of about 300-400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount of lOOccZ for cleaning conditions of lTorr decompression,
  • Wafer 7 Diameter is about 300mm, as shown in Fig. 14, Cu wiring layer 21, thickness from substrate side A SiOC film 22, a NORI insulation film 23, and a PE-CV DSiN film 24, which are low-k films with a thickness of about 30 nm, are formed!
  • a tantalum / tantalum nitride (TaZTaN) film which is a diffusion prevention metal 25, 26, is formed on the PE-CVDSiN film 24 thus modified, and a Cu wiring layer is formed in the via. Even if the wafer 7 on which 27 is formed is heated at a temperature of about 400 ° C. for 3 hours, PE—CVDSiN 24 forming the side surface of the via hole has a high density. As a result, Ta in diffusion prevention metal 25 and 26 did not diffuse.
  • a semiconductor device was actually manufactured using the semiconductor manufacturing apparatus shown in FIG. 6 or FIG.
  • Lamp 4 XeCl lamps with a wavelength of about 308 nm, illuminance of about 4-15 mWZcm 2 , irradiation time of about 1-2 minutes, distance to wafer 7 of about 10-20 cm,
  • Chamber 1 lTorr decompression state, temperature power of about 300-400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount of lOOccZ for cleaning conditions of lTorr decompression,
  • Wafer 7 Diameter is about 300 mm, and transistor 82 and the like are formed as shown in FIG.
  • cover P By changing the pressure in the CVD process of the E-CVDSiN film 84, replacing it with the cover LP-CV DSiN film, it was about 25% before modification, but about 1% after modification. Natsu.
  • the HfO film 33 is processed under the following conditions, and the semiconductor device is actually processed.
  • Lamp 4 XeBr lamps with a wavelength of about 282nm, illuminance of about 5-13mWZcm 2 , irradiation time of about 3 minutes,
  • Chamber 1 lTorr decompression state, temperature is about 250 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply rate is lOOcc / min under cleaning conditions of lTorr decompression,
  • Wafer 7 LP-SiN film with a diameter of about 300 mm and sidewalls is formed with a thickness of about 300 nm.
  • FIG. 1 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic configuration diagram of the first chamber 11 in FIG.
  • FIG. 3 is a diagram showing the relationship between the wavelength of irradiated light and the binding energy of a substance.
  • FIG. 4 is a diagram showing the relationship between the wavelength of irradiated light, the absorption edge, and the binding energy.
  • FIG. 5 is a schematic cross-sectional view of a part of the wafer 7 shown in FIG.
  • FIG. 6 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic configuration diagram of the chamber 15 in FIG. 6.
  • FIG. 8 is a schematic cross-sectional view of a part of the wafer 7 shown in FIG.
  • FIG. 9 is a schematic cross-sectional view after removing a part of the SiN film 57 of the wafer 7 shown in FIG.
  • FIG. 10 is a schematic configuration diagram of a first chamber 11 according to Embodiment 4 of the present invention.
  • FIG. 11 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 5 of the present invention.
  • FIG. 12 is a schematic cross-sectional view of a part of a wafer 7 to be a semiconductor device according to Embodiment 6 of the present invention.
  • FIG. 13 is a partial cross-sectional view of a semiconductor device according to an example of the present invention.
  • FIG. 14 is a partial cross-sectional view of a semiconductor device according to an example of the present invention.
  • FIG. 15 is a partial cross-sectional view of a semiconductor device according to an example of the present invention.
  • FIG. 16 is a partial cross-sectional view of a semiconductor device according to an example of the present invention.
  • FIG. 17 is a schematic configuration diagram of a prevention ring 8 A for preventing the positional deviation of the wafer 7 provided in the first chamber 11 and the second chamber 12.
  • FIG. 18 is a diagram showing a modification of FIG.
  • FIG. 19 is a diagram showing a modification of the manufacturing process of the wafer 7 shown in FIGS. 8 and 9.
  • FIG. 20 is a view showing a modification of the manufacturing process of the wafer 7 shown in FIGS. 8 and 9.
  • FIG. 20 is a view showing a modification of the manufacturing process of the wafer 7 shown in FIGS. 8 and 9.
  • FIG. 20 is a view showing a modification of the manufacturing process of the wafer 7 shown in FIGS. 8 and 9.
  • FIG. 21 is a view showing a modification of the manufacturing process of the wafer 7 shown in FIGS. 8 and 9.

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Abstract

[PROBLEMS] To provide a semiconductor production apparatus capable of modifying an insulating film. [MEANS FOR SOLVING PROBLEMS] Irradiation unit is provided with not only first irradiation means for irradiating an insulating film with a light of first wavelength but also second irradiation means for irradiating the insulating film with a light of second wavelength.

Description

明 細 書  Specification
照射装置、照射方法及び半導体デバイス  Irradiation apparatus, irradiation method, and semiconductor device
技術分野  Technical field
[0001] 本発明は、照射装置、照射方法及び半導体デバイスに関する。  The present invention relates to an irradiation apparatus, an irradiation method, and a semiconductor device.
背景技術  Background art
[0002] 従来、半導体デバイスは、種々の絶縁膜を備えて 、る。これらの絶縁膜には、 ICの 層間絶縁膜 (例えば、低誘電率膜 (以下、「Low— k膜」と称する。)、配線間に形成さ れる配線材料のノリア一絶縁膜、高誘電率ゲート絶縁膜 (以下、「High— k膜」と称 する。)などがある。また、絶縁膜の材料には、 SiN、 SiON、 SiOCH、 SiOCNH、 Si CH、 SiCNH、 SiOCF、 SiCFなどが用いられる。  Conventionally, a semiconductor device includes various insulating films. These insulating films include an IC interlayer insulating film (for example, a low dielectric constant film (hereinafter referred to as “Low-k film”), a noria insulating film of a wiring material formed between wirings, and a high dielectric constant. Gate insulation film (hereinafter referred to as “High-k film”), etc. In addition, SiN, SiON, SiOCH, SiOCNH, SiCH, SiCNH, SiOCF, SiCF, etc. are used as the material of the insulation film .
[0003] Low— k膜は、低誘電率及び高機械的強度であることが要求されて 、る。低誘電 率を実現するための一法は、 Low— k膜に対して熱ァニール処理を行うことである。 高機械的強度を実現するための一法は、特許文献 1に記載されているように、紫外 光照射処理を行うことである。  [0003] Low-k films are required to have a low dielectric constant and high mechanical strength. One way to achieve a low dielectric constant is to perform a thermal annealing on the low-k film. One method for realizing high mechanical strength is to perform ultraviolet light irradiation treatment as described in Patent Document 1.
[0004] 具体的には、上記熱ァニール処理は、 400°C以上の温度で、 30分以上ァニール することが必要とされている。また、上記紫外光照射処理は、 200nm以下の波長の 紫外光を照射することが必要とされて 、る。  [0004] Specifically, the thermal annealing treatment is required to be performed at a temperature of 400 ° C or higher for 30 minutes or longer. The ultraviolet light irradiation treatment is required to irradiate ultraviolet light having a wavelength of 200 nm or less.
[0005] また、バリアー絶縁膜は、均一で高蜜度であることが要求されているが、薄膜化の 要請もある。  [0005] Also, the barrier insulating film is required to be uniform and highly dense, but there is also a demand for a thin film.
[0006] さらに、 High-k膜 (HfO膜)は、緻密なことと、リーク電流を流れに《することとが  [0006] Further, the high-k film (HfO film) is dense and can cause leakage current to flow.
2  2
要求されている。このために、 High— k膜形成後に行うァニール処理が重要になつ ている。従来、 High— k膜は、有機金属化学気相蒸着法(Metaト Organic Chemical Vapor Deposition : MOCVD)などで形成されていた。具体的には、 High— k膜の形 成に先立って、シリコン上に Oガスを供給しながら、 425°Cの温度で加熱することで  It is requested. For this reason, annealing treatment after high-k film formation is important. Conventionally, a high-k film has been formed by metal organic chemical vapor deposition (MOCVD) or the like. Specifically, prior to formation of the high-k film, heating is performed at a temperature of 425 ° C. while supplying O gas onto the silicon.
2  2
境界層を形成する。その後、 450°C〜550°Cの温度下で有機金属化学気相蒸着に より、 High— k膜を形成する。その後 700°Cから 900°Cの温度下で N ス  Form a boundary layer. Thereafter, a high-k film is formed by metalorganic chemical vapor deposition at a temperature of 450 ° C to 550 ° C. After that, at a temperature of 700 ° C to 900 ° C, N
2、 N /Oガ 2 2 または NHガスを供給することにより、 High— k膜中の Si— O結合のシリコンを窒素 ィ匕 (N化)を行い SiN結合を形成する。さらにアルゴン (Ar)中でァニール処理を行う( 非特許文献 1, 2)。 2. By supplying N 2 / O 2 2 or NH gas, the Si—O bond silicon in the high-k film is replaced with nitrogen. Perform SiN (Nation) to form SiN bond. Further, annealing is performed in argon (Ar) (Non-patent Documents 1 and 2).
[0007] 特許文献 1:特開 2004— 356508号公報 [0007] Patent Document 1: JP 2004-356508 A
非特許文献 1 : IEEE Electron Devices 52, pl839 (2005).  Non-Patent Document 1: IEEE Electron Devices 52, pl839 (2005).
非特許文献 2 : The Electrochemical Society Interface, Summer 2005, p30 (2005). 発明の開示  Non-Patent Document 2: The Electrochemical Society Interface, Summer 2005, p30 (2005). Disclosure of the Invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0008] しかし、従来の紫外線照射処理を行うと、 Low— k膜は、その機械的強度が向上す るものの、誘電率も増加するという問題があった。例えば、誘電率が 2. 4の Low— k 膜に、波長が 172nm、照度が 14mWZcm2の紫外光を 2分間照射すると、機械的 強度であるヤング率は 8GPaになる力 誘電率は 2. 6以上に増加した。 However, when the conventional ultraviolet irradiation treatment is performed, the low-k film has a problem in that although the mechanical strength is improved, the dielectric constant is also increased. For example, when a low-k film with a dielectric constant of 2.4 is irradiated with ultraviolet light with a wavelength of 172 nm and an illuminance of 14 mWZcm 2 for 2 minutes, the Young's modulus, which is the mechanical strength, becomes 8 GPa. The dielectric constant is 2.6. More than that.
[0009] また、熱ァニール処理を行うことによって 2. 3以下の誘電率を実現可能な回転塗布  [0009] In addition, spin coating that can achieve a dielectric constant of 2.3 or less by thermal annealing treatment
(Spin on Deposition: SOD)膜に対して、波長が 172nm、照度が 14mWZcm2の紫 外光を 4分間照射すると、機械的強度であるヤング率は 8GPaになるが、誘電率が 2 . 5に増加した。 When (Spin on Deposition: SOD) film is irradiated with ultraviolet light with a wavelength of 172 nm and illuminance of 14 mWZcm 2 for 4 minutes, the Young's modulus, which is mechanical strength, becomes 8 GPa, but the dielectric constant becomes 2.5. Increased.
[0010] さらに、上記熱ァニール処理は、既述のように、 400°Cという高い温度で 30分以上 のァニールを行うため、例えば、半導体デバイスで使用される、銅 (Cu)などの配線 材料力 ow— k膜へ拡散し、配線間のリーク電流が多くなる。また、上記熱ァニール 処理は 30分以上の時間を要するのに対して、半導体デバイスの他の製造工程は 5 分程度である。したがって、上記熱ァニール処理を行うと、半導体デバイスの製造ス ループットが低下するという問題がある。  [0010] Further, as described above, the thermal annealing treatment is performed at a temperature as high as 400 ° C for 30 minutes or more. For example, wiring materials such as copper (Cu) used in semiconductor devices are used. The force ow— diffuses into the k film and increases the leakage current between wires. The thermal annealing process takes more than 30 minutes, while other manufacturing processes for semiconductor devices take about 5 minutes. Therefore, when the thermal annealing process is performed, there is a problem that the manufacturing throughput of the semiconductor device is lowered.
[0011] また、バリアー絶縁膜を薄くして、さらに、その密度を高めることは困難であった。も つとも、従来、バリアー絶縁膜の密度を高める具体的手法は、存在していない。  [0011] Further, it has been difficult to make the barrier insulating film thinner and further increase its density. In the past, there has been no specific method for increasing the density of the barrier insulating film.
[0012] さらに、 High— k膜の場合には、 High— k膜中に多くのチャージが存在し、ソース ドレイン電流が小さくなることと、 High— k膜のリーク電流が大きくなることとに問題 があった。これらは、 High— k膜中の酸素(O)の欠損によって生じた空孔に起因する 問題である。  [0012] Further, in the case of a high-k film, there are many charges in the high-k film, which causes a problem that the source / drain current decreases and the leak current of the high-k film increases. was there. These are problems caused by vacancies caused by oxygen (O) loss in the high-k film.
[0013] このように、絶縁膜に対しては、その用途に応じた改質が求められている。 [0014] そこで、本発明は、絶縁膜を改質可能な半導体製造装置を提供することを課題と する。 As described above, the insulating film is required to be modified in accordance with its use. Therefore, an object of the present invention is to provide a semiconductor manufacturing apparatus capable of modifying an insulating film.
課題を解決するための手段  Means for solving the problem
[0015] 上記課題を解決するために、本発明の照射装置は、絶縁膜に対して第 1の波長の 紫外光を照射する第 1照射手段と、 In order to solve the above-described problem, the irradiation apparatus of the present invention includes a first irradiation unit that irradiates the insulating film with ultraviolet light having a first wavelength;
前記絶縁膜に対して第 1の波長とは異なる第 2の波長の紫外光または可視光を照 射する第 2照射手段と、を備える。  Second irradiating means for irradiating the insulating film with ultraviolet light or visible light having a second wavelength different from the first wavelength.
[0016] 前記絶縁膜が低誘電率膜の場合には、前記光の一方は絶縁膜内の安定状態にな い結合基を切断するために必要な波長以下の光であり、前記光の他方は吸収端以 上の波長の光である。 [0016] When the insulating film is a low dielectric constant film, one of the lights is light having a wavelength equal to or less than a wavelength necessary for cutting a bonding group that is not in a stable state in the insulating film, and the other of the lights Is light with a wavelength longer than the absorption edge.
[0017] また、前記絶縁膜が配線間絶縁膜又はバリアー絶縁膜の場合には、前記光の一方 は絶縁膜内の結合基を切断するために必要な波長以下の光であり、前記光の他方 は吸収端以上の波長の光である。  [0017] When the insulating film is an inter-wiring insulating film or a barrier insulating film, one of the lights is light having a wavelength equal to or shorter than a wavelength necessary for cutting a bonding group in the insulating film. The other is light having a wavelength longer than the absorption edge.
[0018] さらに、前記絶縁膜が高誘電率ゲート絶縁膜の場合には、前記光の一方は遷移金 属の酸ィヒに必要な波長または C H結合を切断するのに必要な波長以下の光であ り、前記各光の他方は吸収端以上の波長の光である。 [0018] Further, when the insulating film is a high dielectric constant gate insulating film, one of the lights is light having a wavelength less than a wavelength necessary for the transition metal oxide or a wavelength necessary for breaking the CH bond. The other of the lights is light having a wavelength longer than the absorption edge.
[0019] また、本発明の半導体製造装置は、上記照射装置と、前記絶縁膜を有するウェハ を搬送する搬送装置と、を備える。 In addition, a semiconductor manufacturing apparatus of the present invention includes the irradiation apparatus and a transfer apparatus that transfers a wafer having the insulating film.
[0020] 前記第 1及び第 2照射手段は、同一のチャンバ一に設けられていてもよいし、異な るチャンバ一に設けられて 、てもよ 、。 [0020] The first and second irradiation means may be provided in the same chamber, or may be provided in different chambers.
[0021] さらに、本発明の半導体デバイスは、化学的気相蒸着装置によって製造される場 合には、誘電率が 2. 4以下であって、ヤング率が 5GPa以上である絶縁膜を備える。 Furthermore, when the semiconductor device of the present invention is manufactured by a chemical vapor deposition apparatus, the semiconductor device includes an insulating film having a dielectric constant of 2.4 or less and a Young's modulus of 5 GPa or more.
[0022] 本発明の半導体デバイスは、半導体デバイス回転塗布成膜装置によって製造され る場合には、誘電率が 2. 3以下であって、ヤング率が 6GPa以上である絶縁膜を備 える。 [0022] When the semiconductor device of the present invention is manufactured by a semiconductor device spin coating film forming apparatus, the semiconductor device includes an insulating film having a dielectric constant of 2.3 or less and a Young's modulus of 6 GPa or more.
[0023] さらに、本発明の照射方法は、絶縁膜に対して第 1の波長の紫外光を照射する第 1 照射工程と、  [0023] Further, the irradiation method of the present invention includes a first irradiation step of irradiating the insulating film with ultraviolet light having a first wavelength;
前記第 1照射工程の後に第 1の波長とは異なる第 2の波長の紫外光または可視光 を照射する第 2照射工程と、を含む。 After the first irradiation step, ultraviolet light or visible light having a second wavelength different from the first wavelength And a second irradiation step of irradiating.
発明の実施の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0024] 以下、本発明の実施形態について、図面を参照して説明する。なお、各図におい て、同様の部分には、同一の符号を付している。  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the same part.
[0025] (実施形態 1)  [Embodiment 1]
図 1は、本発明の実施形態 1の半導体製造装置の模式的な構成図である。本実施 形態では、主として、 Low— k膜を改質する装置について説明する。  FIG. 1 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 1 of the present invention. In the present embodiment, an apparatus for modifying a low-k film will be mainly described.
[0026] 図 1には、ウェハが収容されるフープ 41と、フープ 41から取り出されたウェハの位置 決めを行うウェハァライメント 42と、ロードロック機構を有する減圧チャンバ一である口 一ドロツクチャンバー 43と、ウェハに対して相対的に長波長の光を照射する第一チヤ ンバー 1と、ウェハに対して相対的に短波長の光を照射する第二チャンバ一 2と、ロー ドロツクチャンバー 43と第一チャンバ一 1と第二チャンバ一 2との間でウェハを搬送す るロボットアームを有するトランスファーチャンバ一 44とを示している。  FIG. 1 shows a hoop 41 that accommodates a wafer, a wafer alignment 42 that positions a wafer taken out from the hoop 41, and a mouth-drop chamber that is a decompression chamber having a load lock mechanism. 43, a first chamber 1 that irradiates a wafer with relatively long wavelength light, a second chamber 2 that irradiates a wafer with relatively short wavelength light, and a low-lock chamber 43 And a transfer chamber 44 having a robot arm for transferring a wafer between the first chamber 11 and the second chamber 1.
[0027] 図 2は、図 1の第一チャンバ一 1の模式的な構成図である。図 2には、 Low— k膜の 材料によって決定される高圧水銀ランプのように 300nm以上の波長の光を照射する 又はハロゲンランプのように 400nm以上 770nm以下の波長の光を照射する複数( 例えば 4つ)のランプ 3と、減圧時にかかる応力から各ランプ 3を保護するとともに各ラ ンプ 3への酸素の接触をことを防止する石英パイプ 4と、石英パイプ 4内に供給される 窒素 (N )ガスなどの不活性ガス 5と、絶縁物で覆われており半導体デバイスとなるゥ FIG. 2 is a schematic configuration diagram of the first chamber 11 in FIG. Fig. 2 shows a number of light beams with a wavelength of 300 nm or more, such as a high-pressure mercury lamp determined by the material of the low-k film, or a wavelength of 400 nm or more and 770 nm or less, such as a halogen lamp Four lamps 3, quartz pipes 4 that protect each lamp 3 from stress applied during decompression and prevent oxygen from contacting each lamp 3, and nitrogen (N ) Inert gas such as gas 5 and semiconductor device covered with an insulator
2 2
ェハ 7と、昇降ステージ上に位置しておりウェハ 7を加熱する絶縁物 (A1N)カゝら成るヒ 一ター 6と、トランスファーチャンバ一 44によって搬送されてきたウェハ 7を受けるピン 8と、連続的 ·定期的 ·間歇的にランプ 3からの照射光の照度を測定する石英パイプ 4 内或いは第一チャンバ一 1の内壁に取り付けられている受光センサー 9と、第一チヤ ンバー 1内に窒素ガスを供給するための配管 11と、ウェハ 7を処理した後に第一チヤ ンバー 1内をクリーニングするための酸素(O )ガスを供給するための配管 12と、各配  , A heater 6 made of an insulator (A1N) located on the elevating stage and heating the wafer 7, and a pin 8 for receiving the wafer 7 conveyed by the transfer chamber 44, Continuously, periodically, intermittently measure the illuminance of the light emitted from the lamp 3 in the quartz pipe 4 or the light receiving sensor 9 attached to the inner wall of the first chamber 1 and nitrogen in the first chamber 1 A pipe 11 for supplying gas, a pipe 12 for supplying oxygen (O) gas for cleaning the inside of the first chamber 1 after processing the wafer 7, and each of the lines
2  2
管 11, 12とガスタンクとの間に設けられたノ レブ 14と、各配管 11, 12を通るガス流 量を計測するとともに計測結果に応じてバルブ 14の開閉を制御するマスフロー 13と を示している。なお、必要に応じて、窒素以外の不活性ガスを第一チャンバ一 1内に 供給できるようにしてちょい。 A nozzle 14 provided between the pipes 11 and 12 and the gas tank, and a mass flow 13 for measuring the gas flow rate through the pipes 11 and 12 and controlling the opening and closing of the valve 14 according to the measurement results are shown. Yes. If necessary, an inert gas other than nitrogen is introduced into the first chamber 11. Make it available.
[0028] また、第二チャンバ一 2の構成も、第一チャンバ一 1と同様であるが、各ランプ 3に代 えて、低圧水銀ランプまたは Xe、 Kr、 I、 KrBrなどのエキシマランプを用いている。 低圧水銀ランプは、ランプのベース部温度が 60°C付近で 186nmの波長の光が相対 的に強くなり、ランプのベース部温度力 0°C付近で 254nmの波長の光が相対的に 強くなるものである。  [0028] The configuration of the second chamber 12 is the same as that of the first chamber 11, but a low-pressure mercury lamp or an excimer lamp such as Xe, Kr, I, KrBr is used instead of each lamp 3. Yes. The low-pressure mercury lamp has a relatively strong light with a wavelength of 186 nm when the base temperature of the lamp is around 60 ° C, and a relatively strong light with a wavelength of 254 nm when the temperature at the base of the lamp is 0 ° C. Is.
[0029] なお、第一チャンバ一 1と第二チャンバ一 2との双方に、同じ波長の光を照射するラ ンプを設けてもよい。この場合には、図 1に示す半導体製造装置で処理されたウェハ 7は、加熱時間が従来に比して 2倍に増加するので、絶縁膜の機械的強度が高まる t 、う点で改質効果が得られるためである。  [0029] Note that a lamp for irradiating light of the same wavelength may be provided in both the first chamber 11 and the second chamber 12. In this case, the wafer 7 processed by the semiconductor manufacturing apparatus shown in FIG. 1 has a heating time twice that of the conventional one, so that the mechanical strength of the insulating film is increased. This is because an effect is obtained.
[0030] また、第一チャンバ一 1のランプ 3には、可視光ランプ、キセノンランプ、アルゴンレ 一ザ、炭酸ガスレーザを用いることもできる。さらに、第二チャンバ一 2のランプには、 XeF、 XeCl、 XeBr、 KrF、 KrCl、 ArF、 ArClなどのエキシマレーザを用いることもで きる。なお、絶縁膜内の安定状態にない結合基を切断するためには、ランプ 3は、波 長が 770nm以下の光、つまり可視光を照射できるものとする必要がある。換言すると 、ランプ 3として、赤外領域の波長範囲の光を照射するランプを用いた場合には、絶 縁膜内の安定状態にない結合基の大半に振動は生じるものの、これらが限定的な時 間内では切断されない。なお、 770nm以下の可視光であれば、 Si— H結合及び C H結合の結合基の大半が好適に切断でき、 500nm以下の可視光であれば更に 好適に切断できることを実験により確認した。  [0030] As the lamp 3 of the first chamber 11, a visible light lamp, a xenon lamp, an argon laser, or a carbon dioxide gas laser can be used. Further, an excimer laser such as XeF, XeCl, XeBr, KrF, KrCl, ArF, or ArCl can be used for the lamp in the second chamber 12. Note that the lamp 3 needs to be able to irradiate light having a wavelength of 770 nm or less, that is, visible light, in order to cut a bonding group that is not in a stable state in the insulating film. In other words, when a lamp that irradiates light in the infrared wavelength range is used as the lamp 3, vibration occurs in most of the bonding groups that are not in a stable state in the insulating film, but these are limited. It is not disconnected in time. It was confirmed by experiments that most of the bonding groups of Si—H bonds and C—H bonds can be suitably cleaved when visible light is 770 nm or less, and can be cleaved more suitably when visible light is 500 nm or less.
[0031] 図 3は、照射光の波長と物質の結合エネルギーとの関係を示す図である。図 3の横 軸が波長(nm)、縦軸が結合エネルギー(eV)である。例えば、 Low— k膜の材料に は、 SiOCH、 SiCFなどを、また Cuのバリアー膜には SiN、 SiOCH、 SiON、 SiOC NH、 SiCNH膜などを用いることが考えられる。  FIG. 3 is a diagram showing the relationship between the wavelength of irradiation light and the binding energy of a substance. The horizontal axis in Fig. 3 is the wavelength (nm), and the vertical axis is the binding energy (eV). For example, SiOCH, SiCF, etc. can be used for the low-k film material, and SiN, SiOCH, SiON, SiOC NH, SiCNH film, etc. can be used for the Cu barrier film.
[0032] 例えば、 SiOCH膜には、 C— H結合と Si— CH結合とが存在する。これらは、 300  [0032] For example, in the SiOCH film, there are C—H bonds and Si—CH bonds. These are 300
3  Three
nm強の波長の光が照射されると結合基が切断される。したがって、 SiOCH膜を絶 縁膜に採用した場合には、 350nm以下の波長の光を照射することで、上記結合基 を切断することが可能となる。 [0033] 同様に、 SiN膜には、 N—H結合と Si— H結合とが存在する。これらは、それぞれ 3 OOnm, 400nm程度の波長の光が照射されると結合基が切断される。したがって、 S iN膜を絶縁膜に採用した場合には、 400nm以下の波長の光を照射することで、上 記結合基を切断することが可能となる。 When light having a wavelength of a little over nm is irradiated, the bonding group is cleaved. Therefore, when the SiOCH film is used as the insulating film, the bonding group can be cleaved by irradiating light with a wavelength of 350 nm or less. Similarly, the SiN film has N—H bonds and Si—H bonds. In these, the bonding group is cleaved when irradiated with light having wavelengths of about 3 OOnm and 400 nm, respectively. Therefore, when the SiN film is used as the insulating film, the above bonding group can be cleaved by irradiating light with a wavelength of 400 nm or less.
[0034] ここで、本発明者は、 Low— k膜内の不安定な結合状態にある水素成分、フッ素成 分などを低減することで、 Low— k膜の誘電率を低くできることを見出した。  [0034] Here, the present inventor has found that the dielectric constant of the low-k film can be lowered by reducing hydrogen components, fluorine components, and the like in an unstable bonding state in the low-k film. .
[0035] したがって、ランプ 3からの 350nm以下の波長の光を照射することによって、 SiOC H膜内の C— H結合と Si— CH結合とを除去できる。この結果、 SiOCH膜内の水素  Therefore, by irradiating light with a wavelength of 350 nm or less from the lamp 3, the C—H bond and the Si—CH bond in the SiOC H film can be removed. As a result, hydrogen in the SiOCH film
3  Three
成分等が低減され、 SiOCH膜の誘電率が低くなる。  Components and the like are reduced, and the dielectric constant of the SiOCH film is lowered.
[0036] また、本発明者は、配線間絶縁膜又はバリアー絶縁膜の水素成分の結合基を切断 することで、配線間絶縁膜等を均一で高密度とすることができることを見出した。さら に、本発明者は、 High— k膜に、遷移金属の酸ィ匕に必要な波長或いは C—H結合を 切断するのに必要な波長以下の光を照射すること、 High— k膜を不活性ガス又は O ガスを 1〜2%程度、好ましくは 1%以下含む不活性ガス雰囲気で UVァニールする[0036] Further, the present inventor has found that the inter-wiring insulating film and the like can be made uniform and high in density by cutting the hydrogen bonding group of the inter-wiring insulating film or the barrier insulating film. Furthermore, the present inventor irradiates the high-k film with light having a wavelength shorter than that required for the transition metal oxide or the wavelength necessary for breaking the C—H bond. UV annealing is performed in an inert gas atmosphere containing about 1 to 2%, preferably 1% or less of inert gas or O gas.
2 2
ことで、 High— k膜を緻密とすることができ、かつ、リーク電流が流れに《なることを 見出した。  As a result, it was found that the high-k film can be made dense and the leakage current becomes a flow.
[0037] したがって、上記各絶縁膜の材料に応じて波長を選択したランプを用いれば、絶縁 膜を、その要求条件をクリアした状態に改質することができる。  [0037] Therefore, if a lamp whose wavelength is selected according to the material of each of the insulating films is used, the insulating film can be modified to a state where the required conditions are cleared.
[0038] 図 4は、照射光の波長と吸収端と結合エネルギーとの関係を示す図である。図 4の 横軸が波長 (nm)、左縦軸が吸収端 (eV)、右縦軸が結合エネルギー(eV)である。 例えば、 SiO膜の吸収端に対応する波長は 156nmである。したがって、 SiON膜に  FIG. 4 is a diagram showing the relationship among the wavelength of irradiation light, the absorption edge, and the binding energy. In Fig. 4, the horizontal axis is the wavelength (nm), the left vertical axis is the absorption edge (eV), and the right vertical axis is the binding energy (eV). For example, the wavelength corresponding to the absorption edge of the SiO film is 156 nm. Therefore, the SiON film
2  2
156nm以上の波長の光を照射すると、光が膜内に進入して、その結果、光が膜内の 構造 (結合の骨格)に吸収され、 SiO膜または SiON膜の密度が向上し、機械的強  When light with a wavelength of 156 nm or more is irradiated, the light enters the film, and as a result, the light is absorbed by the structure (bonding skeleton) in the film, increasing the density of the SiO film or SiON film, and mechanically. Strong
2  2
度が高くなる。同様に、 SiNの吸収端吸収端に対応する波長は 275. 6nmであるの で、 SiN膜に 275. 6nm以上の波長の光を照射すると、 SiN膜の密度が向上する、 又は、水素成分等が除去される。  The degree becomes higher. Similarly, since the wavelength corresponding to the absorption edge / absorption edge of SiN is 275.6 nm, when the SiN film is irradiated with light having a wavelength of 275.6 nm or more, the density of the SiN film is improved, or a hydrogen component, etc. Is removed.
[0039] 図 5は、図 2に示すウェハ 7の一部の模式的な断面図である。図 5には、半導体デバ イス内の信号を伝送する配線層 31と、配線層 31上に形成されて!、て配線層 31の成 分の漏れをバリアーするバリアー絶縁膜 32と、ノ リア一絶縁膜 32上に形成されてい て後の工程で Low— k膜自体の上に形成される層とを絶縁する Low— k膜 33とを示 している。 FIG. 5 is a schematic cross-sectional view of a part of the wafer 7 shown in FIG. FIG. 5 shows a wiring layer 31 for transmitting signals in the semiconductor device, and a wiring layer 31 formed on the wiring layer 31! A barrier insulating film 32 that barriers against leakage of water, and a low-k film 33 that is formed on the NORI-insulating film 32 and insulates the layer formed on the low-k film itself in a later step. Is shown.
[0040] 配線層 31は、 Cuなどが材料として選択され、厚さは 200〜300nm程度である。バ リア一絶縁膜 32は、 SiOC、 SiCH、 SiOCH、 SiOCNHなどが材料として選択され、 厚さは 20〜30nm程度である。 Low— k膜 33は、 SiOCHなどが材料として選択され 、厚さは 200〜300nm程度である。  [0040] The wiring layer 31 is made of Cu or the like, and has a thickness of about 200 to 300 nm. The barrier one insulating film 32 is selected from materials such as SiOC, SiCH, SiOCH, and SiOCNH, and has a thickness of about 20 to 30 nm. The low-k film 33 is made of SiOCH or the like and has a thickness of about 200 to 300 nm.
[0041] つぎに、 SiOCH膜力Low— k膜 33として選択されたウェハ 7を例に、 Low— k膜 33 の改質処理の手順について説明する。本実施形態では、まず、図示しないクリーン ルーム内の CVD装置力もフープ 41に収容された状態で搬送されてくる。その後、ゥ エノ、は、フープ 41から取り出され、ウェハァライメント 42側へ搬送される。  Next, the procedure for the modification process of the low-k film 33 will be described by taking the wafer 7 selected as the SiOCH film power low-k film 33 as an example. In the present embodiment, first, the CVD apparatus power in a clean room (not shown) is also transported while being accommodated in the hoop 41. Thereafter, the wafer is taken out from the hoop 41 and transferred to the wafer alignment 42 side.
[0042] ウェハァライメント 42では、そのウェハの位置決めが行われる。その後、ウェハ 7は、 第一チャンバ一 1に搬送されるのに先立って、ロードロックチャンバ一 43に搬送され る。  In the wafer alignment 42, the wafer is positioned. Thereafter, the wafer 7 is transferred to the load lock chamber 43 before being transferred to the first chamber 11.
[0043] つぎに、ロードロックチャンバ一 43内が減圧される。そして、ロードロックチャンバ一 43内が所望の圧力になると、ロードロックチャンバ一 43とトランスファーチャンバ一 44 との間を仕切っているゲートバルブが開かれる。  [0043] Next, the pressure in the load lock chamber 43 is reduced. When the pressure in the load lock chamber 43 reaches a desired pressure, the gate valve that partitions the load lock chamber 43 and the transfer chamber 44 is opened.
[0044] その後、ウェハ 7は、トランスファーチャンバ一 44内に搬送される。つづいて、トラン スフアーチヤンバー 44内のロボットアームによって、ロードロックチャンバ一 43内から 第一チャンバ一 1内へ、ウェハ 7が搬送されていく。  Thereafter, the wafer 7 is transferred into the transfer chamber 44. Subsequently, the wafer 7 is transferred from the load lock chamber 43 to the first chamber 11 by the robot arm in the transfer arch yanber 44.
[0045] 第一チャンバ一 1内では、ウェハ 7は、ヒーター 6の上部に突出しているピン 8上に載 置される。その後、ヒーター 6が上昇され、ピン 8に載置されていたウェハ 7は、ヒータ 一 6に直に接触することになる。それから、ウェハ 7は、ランプ 3からの光の照射に先立 つて、ヒーター 8【こよって、 f列え ίま、、約 90禾少 f¾、 350〜400°Cでカロ熱される。  In the first chamber 11, the wafer 7 is placed on the pins 8 protruding above the heater 6. Thereafter, the heater 6 is raised, and the wafer 7 placed on the pin 8 comes into direct contact with the heater 6. Then, prior to the irradiation of the light from the lamp 3, the wafer 7 is heated by heating at a heater 8 [thereby, f line, approximately 90 times f¾, 350-400 ° C].
[0046] また、この加熱と共に、図示しない排気手段によって第一チャンバ一 1内が排気さ れ、かつ、マスフロー 13によって窒素ガス側のバルブ 14が開かれ、第一チャンバ一 1 内が窒素雰囲気となる。上記加熱は、第一チャンバ一 1内が例えば lTorrとなる条件 で行われ、ノ レブ 14の開閉制御は、第一チャンバ一 1への窒素ガスの供給量が、例 えば lOOccZ分となる条件で行われる。 [0046] Further, along with this heating, the inside of the first chamber 11 is evacuated by an evacuation means (not shown), and the valve 14 on the nitrogen gas side is opened by the mass flow 13 so that the inside of the first chamber 1 is in a nitrogen atmosphere. Become. The above heating is performed under the condition that the inside of the first chamber 11 becomes, for example, lTorr. The opening / closing control of the nozzle 14 is controlled by the amount of nitrogen gas supplied to the first chamber 11 as an example. For example, it is performed under the condition of lOOccZ.
[0047] なお、第一チャンバ一 1内は、減圧状態でなぐ常圧状態であってもよい。また、必 要に応じて、 Nガスに代えて他の不活性ガスを、第一チャンバ一 1内に供給してもよ [0047] It should be noted that the inside of the first chamber 11 may be in a normal pressure state that is not in a reduced pressure state. If necessary, another inert gas may be supplied into the first chamber 11 instead of the N gas.
2  2
いし、 Nガスと他の不活性ガスとの混合ガスを用いてもよい。  Alternatively, a mixed gas of N gas and other inert gas may be used.
2  2
[0048] ヒーター 8の上昇は、ランプ 3から照射される光がウェハ 7に強度ムラがなく到達する ように、ウェハ 7とランプ 3との距離が例えば 100〜200mmとなる範囲で行うようにし ている。  [0048] The heater 8 is raised in a range where the distance between the wafer 7 and the lamp 3 is, for example, 100 to 200 mm so that the light irradiated from the lamp 3 reaches the wafer 7 without unevenness in intensity. Yes.
[0049] つぎに、ランプ 3からウェハ 7に対して光を照射する。この際、光の照度を受光セン サー 9で測定し、その照度が高圧水銀ランプの場合は例えば 8mWZcm2、ハロゲン ランプの場合は例えば 15mWZcm2となるように、ランプ 3を制御する。 Next, light is irradiated from the lamp 3 to the wafer 7. In this case, the illuminance of light measured by the light receiving sensor 9, for example 8MWZcm 2 when the illuminance is high pressure mercury lamp, as in the case of halogen lamps the example 15MWZcm 2, controls the lamp 3.
[0050] この際、ウェハ 7に対して上記照度で光を照射すると、ウェハ 7内の絶縁膜に、脱離 ガス〖こよるクラックが生じたり、当該絶縁膜の剥離が生じたりする場合がある。そこで、 受光センサー 9の測定結果に基づいて、 5〜: L0秒程度の時間で、連続的に、或いは 、階段状に、ランプ 3の照度を上昇させている。照度の上昇は、例えば、線形的であ つてもよいし、指数関数的であっても、さらには別の形態でもよい。  At this time, if the wafer 7 is irradiated with light at the above illuminance, the insulating film in the wafer 7 may be cracked by desorbed gas or may be peeled off. . Therefore, based on the measurement result of the light receiving sensor 9, the illuminance of the lamp 3 is increased continuously or stepwise in a time of about 5 to: L0 seconds. The increase in illuminance may be, for example, linear, exponential, or another form.
[0051] その後、照射開始から所定時間 (例えば 1〜2分)が経過したら、照射を完了すると ともに、窒素ガス側のバルブ 14を閉じる。こうして、ノ リア一絶縁膜 32及び Low— k 膜 33内の不安定な C H結合、 Si—CH結合および H— CH Si(CH )結合等を  [0051] Thereafter, when a predetermined time (for example, 1 to 2 minutes) elapses from the start of irradiation, the irradiation is completed and the valve 14 on the nitrogen gas side is closed. In this way, unstable C H bonds, Si—CH bonds, H—CH Si (CH) bonds, etc. in the NORI insulating film 32 and the low-k film 33 are removed.
3 2 3 3 除去し、 Low— k膜 33の誘電率を低下させる。  3 2 3 3 Remove and lower the dielectric constant of low-k film 33.
[0052] 引き続き、例えば lTorrの減圧下を維持しながら、酸素ガス側のバルブ 14を開けて 、 O 2ガスを lOOccZ分の割合で第一チャンバ一 1内に約 1分間供給することで第一 チャンバ一 1内をクリーニングする。 [0052] Subsequently, for example, while maintaining the reduced pressure of lTorr, the valve 14 on the oxygen gas side is opened, and O 2 gas is supplied into the first chamber 11 at a rate of lOOccZ for about 1 minute. Clean inside chamber 1.
[0053] つぎに、トランスファーチャンバ一 44によって、第一チャンバ一 1内から第二チャン バー 2内へ、ウェハ 7が搬送される。ウェハ 7は、第二チャンバ一 2においても、第一チ ヤンバー 1での処理の場合と同様に処理される力 低圧水銀ランプからウェハ 7に対 して光を照射する条件は、その照度を 3mWZcm2とする。また、照射時間は、例え ば 1〜4分とする。この照射によって、 Low— k膜 33の誘電率の上昇を抑えることがで き、機械的強度が高めることができる。 [0054] 第二チャンバ一 2から取り出したウェハ 7は、例えば、 Low— k膜 33のヤング率は約 5GPa以上、誘電率は 2. 5以下となる。また、ノリア一絶縁膜 32のヤング率は約 60 GPa、誘電率は約 4. 0、密度は約 2. 5gZcm3となる。 Next, the wafer 7 is transferred from the first chamber 11 into the second chamber 2 by the transfer chamber 44. Wafer 7 is processed in the second chamber 12 in the same manner as in the processing in the first chamber 1. The condition for irradiating the wafer 7 from the low-pressure mercury lamp is that the illuminance is 3 mWZcm. 2 For example, the irradiation time is 1 to 4 minutes. By this irradiation, an increase in the dielectric constant of the low-k film 33 can be suppressed, and the mechanical strength can be increased. The wafer 7 taken out from the second chamber 12 has, for example, a low-k film 33 having a Young's modulus of about 5 GPa or more and a dielectric constant of 2.5 or less. Also, the Young's insulating film 32 has a Young's modulus of about 60 GPa, a dielectric constant of about 4.0, and a density of about 2.5 gZcm 3 .
[0055] (実施形態 2)  [0055] (Embodiment 2)
図 6は、本発明の実施形態 2の半導体製造装置の模式的な構成図である。図 7は、 図 6のチャンバ一 15の模式的な構成図である。本実施形態では、図 1に示した第一 チャンバ一 1と第二チャンバ一 2とを一つのチャンバ一 15で実現している。  FIG. 6 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 2 of the present invention. FIG. 7 is a schematic configuration diagram of the chamber 15 in FIG. In the present embodiment, the first chamber 1 and the second chamber 1 shown in FIG.
[0056] チャンバ一 15は、複数(例えば 5つ)のランプ 3と、複数(例えば 4つ)のランプ 21と を備えている。ここでは、ランプ 21とウェハ 7との距離は、チャンバ一 15の使用時に、 約 100mmとなるようにしてある。一方、ランプ 3とウェハ 7との距離は、約 120mmとな るようにしてある。ランプ 3と低圧水銀ランプ 21との数は同じであってもよいし、ランプ 3とランプ 21とは 2次元に並べてもよい。  The chamber 15 includes a plurality of (for example, five) lamps 3 and a plurality of (for example, four) lamps 21. Here, the distance between the lamp 21 and the wafer 7 is about 100 mm when the chamber 15 is used. On the other hand, the distance between the lamp 3 and the wafer 7 is about 120 mm. The number of the lamps 3 and the low-pressure mercury lamps 21 may be the same, or the lamps 3 and 21 may be arranged two-dimensionally.
[0057] ウェハ 7に対しては、ランプ 3とランプ 21とのいずれから先に、紫外線を照射してもよ い。ただし、同時に照射しても、 Low— k膜 33の誘電率を低下させ、かつ、機械的強 度を向上させることはできな 、ので留意された 、。  [0057] The wafer 7 may be irradiated with ultraviolet rays first from either the lamp 3 or the lamp 21. However, it was noted that the dielectric constant of the low-k film 33 could not be lowered and the mechanical strength could not be improved even when irradiated simultaneously.
[0058] 半導体デバイスの製造プロセスは、実施形態 1と同様である。ランプ 3とランプ 21と の各照射時間も、実施形態 1と同様とすればよい。この条件であれば、照射前のゥ ハ 7の加熱時間は 1分、照射時間の総計は 5分、クリーニング時間は 1分であるので、 他の工程も 7分であれば、製造スループットが低下することはな!/、。  The semiconductor device manufacturing process is the same as that in the first embodiment. The respective irradiation times of the lamp 3 and the lamp 21 may be the same as those in the first embodiment. Under these conditions, the heating time of the wafer 7 before irradiation is 1 minute, the total irradiation time is 5 minutes, and the cleaning time is 1 minute. Nothing to do! /
[0059] (実施形態 3)  [Embodiment 3]
実施形態 1, 2では、主として、 Low— k膜 33の処理について説明した。本実施形 態では、歪シリコンデバイスの SiN膜のストレスを大きくする処理にっ 、て説明する。  In the first and second embodiments, the processing of the low-k film 33 has been mainly described. In the present embodiment, a process for increasing the stress of the SiN film of the strained silicon device will be described.
[0060] 半導体デバイスにおける絶縁膜を用いる技術に歪みシリコン技術がある。歪みシリ コン技術とは、ソース—ドレインにシリコンゲルマニウム(SiGe)層を設けて電子の密 度を高め、ゲート下のチャネル領域におけるシリコン原子の格子が互いに整列しょう とする性質を利用してシリコン原子の間隔を広げ、ソースドレイン電流の担 、手である 電子とシリコン原子の衝突を少なくし、電子の移動度を大きくする技術のことである。  [0060] A technique using an insulating film in a semiconductor device is a strained silicon technique. Strained silicon technology uses silicon germanium (SiGe) layers at the source and drain to increase the density of electrons and makes use of the property that the lattice of silicon atoms in the channel region under the gate tends to align with each other. This is a technology that increases the mobility of electrons by increasing the distance between the electrodes, reducing the collision of electrons and silicon atoms, which are responsible for source-drain current.
[0061] この技術によると、電子が流れる際の抵抗が少なくなるので、電子を高速移動させ ることが可能となる。したがって、歪みシリコン技術をトランジスタに用いると、高速動 作が可能なトランジスタを実現できる。歪みシリコン技術をトランジスタに用いるために は、 Nチャネルトランジスタ上に例えば SiN膜を形成し、次いで、例えば熱ァニールま たはハロゲン光を照射して、シリコン基板に歪をカ卩えるという手法が採用されている。 [0061] According to this technique, resistance when electrons flow is reduced, so that electrons can be moved at high speed. It is possible to Therefore, when strained silicon technology is used for a transistor, a transistor capable of high-speed operation can be realized. In order to use strained silicon technology for transistors, a method is adopted in which, for example, a SiN film is formed on an N-channel transistor, and then, for example, thermal annealing or halogen light is irradiated to strain the silicon substrate. Has been.
[0062] 本実施形態においても、図 1或いは図 6に示す半導体製造装置を用いることができ る。ただし、ランプ 3に代えて例えば 341nmの波長の光を照射する Iランプを用い、 In this embodiment, the semiconductor manufacturing apparatus shown in FIG. 1 or 6 can also be used. However, instead of the lamp 3, an I lamp that irradiates light with a wavelength of 341 nm, for example,
2  2
ランプ 21に代えて例えば 282nmの波長の光を照射する XeBrランプ或いは例えば 3 08nmの波長の光を照射する XeClランプを用いる。  Instead of the lamp 21, for example, an XeBr lamp that irradiates light with a wavelength of 282 nm or an XeCl lamp that irradiates light with a wavelength of 308 nm, for example, is used.
[0063] 本実施形態では、 Iランプからの照射光によって SiN膜から水素を脱離させ、その In this embodiment, hydrogen is desorbed from the SiN film by the irradiation light from the I lamp, and the
2  2
後、 XeBrランプからの照射光によって SiN膜のストレスを増加させる。  After that, the stress on the SiN film is increased by the irradiation light from the XeBr lamp.
[0064] 図 8は、図 2に示すウェハ 7の一部の模式的な断面図である。図 8には、 P型シリコン 層 51と、 P型シリコン層 51内に作成された N型ゥ ル領域 52と、 N型ゥ ル領域 52 内に形成された SiGeなどのソース領域 53及びドレイン領域 54と、 N型ゥエル領域 52 上に形成されたゲート絶縁膜 62と、ゲート絶縁膜 62に形成されたゲート電極 55と、 P 型シリコン層 51内に形成された SiGeなどのソース領域 58及びドレイン領域 59と、シ リコン層 51上に形成されたゲート絶縁膜 63と、ゲート絶縁膜 63に形成されたゲート 電極 60と、ゲート電極 55, 60上に形成された SiO膜 56, 61と、 SiO膜 56, 61上に FIG. 8 is a schematic cross-sectional view of a part of the wafer 7 shown in FIG. FIG. 8 shows a P-type silicon layer 51, an N-type region 52 formed in the P-type silicon layer 51, and a source region 53 and a drain region such as SiGe formed in the N-type region 52. 54, a gate insulating film 62 formed on the N-type well region 52, a gate electrode 55 formed on the gate insulating film 62, and a source region 58 and drain such as SiGe formed in the P-type silicon layer 51. Region 59, gate insulating film 63 formed on silicon layer 51, gate electrode 60 formed on gate insulating film 63, SiO films 56 and 61 formed on gate electrodes 55 and 60, and SiO. On membrane 56, 61
2 2  twenty two
形成されたサイドウォールとなる SiN膜 57とを示している。  A SiN film 57 to be a formed sidewall is shown.
[0065] ソース領域 53及びドレイン領域 54側のトランジスタは Pチャネルトランジスタであり、 ソース領域 58及びドレイン領域 59側のトランジスタは Nチャネルトランジスタである。 このようなウェハ 7は、拡散炉、イオン注入装置、さらに化学的気相蒸着 (Chemical Va por Deposition System : CVD)装置によって形成される。 The transistor on the source region 53 and drain region 54 side is a P-channel transistor, and the transistor on the source region 58 and drain region 59 side is an N-channel transistor. Such a wafer 7 is formed by a diffusion furnace, an ion implantation apparatus, and a chemical vapor deposition system (CVD) apparatus.
[0066] このウェハ 7は、上記 Iランプからの照射光によって、 SiN膜 57内の水素成分等が 7 [0066] This wafer 7 has a hydrogen component, etc. in the SiN film 57 due to the irradiation light from the I lamp.
2  2
0%程度低減し、 XeBrランプからの照射光によって、更に SiN膜 57内の残りの水素 が除去され、 SiN膜 57内には、ほぼ完全に水素がない状態となる。この結果、 SiN膜 57の機械的強度が高まる。  The remaining hydrogen in the SiN film 57 is further removed by the irradiation light from the XeBr lamp, and the SiN film 57 is almost completely free of hydrogen. As a result, the mechanical strength of the SiN film 57 is increased.
[0067] 図 9は、図 8に示すウェハ 7の SiN膜 57の一部除去後の模式的な断面図である。上 記光照射処理の後に、 SiN膜 57のうち Pチャネルトランジスタ側を除去する。こうして 、歪シリコンデバイスを作成する。 FIG. 9 is a schematic cross-sectional view after removing a part of the SiN film 57 of the wafer 7 shown in FIG. After the above light irradiation treatment, the P channel transistor side of the SiN film 57 is removed. Thus Create strained silicon devices.
[0068] なお、本実施形態の場合と同じ条件で、半導体製造装置を用いて処理を行うと、 Si Nカバー絶縁膜の水素濃度も低減でき、 DRAMのカバー膜中の水素に起因するゲ ート一ドレインリーク電流を低減でき、リテンション不良を減少させることができる。  Note that when processing is performed using the semiconductor manufacturing apparatus under the same conditions as in the present embodiment, the hydrogen concentration of the SiN cover insulating film can also be reduced, and the gate caused by hydrogen in the DRAM cover film can be reduced. Toe drain leakage current can be reduced and retention defects can be reduced.
[0069] (実施形態 4)  [Embodiment 4]
図 10は、本発明の実施形態 4の第一チャンバ一 1の模式的な構成図である。この 第一チャンバ一 1は、波長が 400nm以上のハロゲンランプを用いた場合に好適なも のである。  FIG. 10 is a schematic configuration diagram of the first chamber 11 according to the fourth embodiment of the present invention. This first chamber 11 is suitable when a halogen lamp having a wavelength of 400 nm or more is used.
[0070] 図 10に示すように、本実施形態では、ハロゲンランプ 3を冷却するために、冷却水 2 As shown in FIG. 10, in the present embodiment, the cooling water 2 is used to cool the halogen lamp 3.
2を用いている。ここで、ハロゲンランプ 3は、ランプの光により、短時間に Siウェハ上 の絶縁膜を加熱して水素を除去する。 2 is used. Here, the halogen lamp 3 removes hydrogen by heating the insulating film on the Si wafer in a short time by the light of the lamp.
[0071] その後、第二のチャンバ一 2で 308nmの XeClランプから UV光を照射して、ストレ スを大きくする。 [0071] Thereafter, UV light is irradiated from a 308 nm XeCl lamp in the second chamber 12 to increase the stress.
[0072] (実施形態 5) [0072] (Embodiment 5)
図 11は、本発明の実施形態 5の半導体製造装置の模式的な構成図である。ここで は、 Low— k膜を、 SOD膜で作成する場合の例について説明する。  FIG. 11 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 5 of the present invention. Here, an example in which a low-k film is formed using an SOD film will be described.
[0073] まず、 SOD膜を回転塗布するコーターを備えるチャンバ一 101内で、例えば 300η mの厚さのウェハに形成された配線上に、 SOD膜を例えば 500nm塗布する。 First, in a chamber 101 provided with a coater for spin-coating an SOD film, for example, an SOD film is applied, for example, to 500 nm on a wiring formed on a wafer having a thickness of 300 ηm.
[0074] 次に、このウェハを、 SOD膜の溶剤を飛ばすためのベータステージを備えるチャン バー 102に移して、約 200°Cの温度でベータを行うことによって溶剤を飛ばす。 Next, the wafer is transferred to a chamber 102 having a beta stage for blowing off the solvent of the SOD film, and the solvent is blown off by performing beta at a temperature of about 200 ° C.
[0075] 次に、このウェハを、溶剤およびポロジェンを飛ばす又は膜を強固にするためのキ ユア一ステージを備えるチャンバ一 103に移して、約 400°Cの温度で、 5分間の時間 ベータを行う。こうして、 SOD膜中の溶剤またはポロジェンを飛ばすなどして、膜を緻 密化する。その後は、実施形態 1等と同様の処理を行う。この場合、 Low— k膜は、 誘電率が 2. 3以下であって、ヤング率が 6GPa以上となる。 [0075] The wafer is then transferred to a chamber 103 equipped with a cure stage to drive off solvent and porogen or to harden the film, and a beta for 5 minutes at a temperature of about 400 ° C. Do. Thus, the film is densified, for example, by blowing off the solvent or porogen in the SOD film. Thereafter, the same processing as in the first embodiment is performed. In this case, the low-k film has a dielectric constant of 2.3 or less and a Young's modulus of 6 GPa or more.
[0076] (実施形態 6) [0076] (Embodiment 6)
図 12は、本発明の実施形態 6の半導体デバイスとなるウェハ 7の一部の模式的な 断面図である。ここでは、ウェハ 7内の High— k膜 73を、 UVァニール処理する例に ついて説明する。 FIG. 12 is a schematic cross-sectional view of a part of a wafer 7 that is a semiconductor device according to Embodiment 6 of the present invention. In this example, UV annealing is applied to the high-k film 73 in wafer 7. explain about.
[0077] このウェハ 7は、シリコンウェハ 71上に、例えば lnmの厚さの SiOリッチの境界層 7  This wafer 7 is formed on a silicon wafer 71, for example, a lnm-thick SiO-rich boundary layer 7
2  2
2が形成されている。境界層 72上には、 HfOなど力もなる High— k膜 73が例えば 5  2 is formed. On the boundary layer 72, for example, a high-k film 73 having a force such as HfO is provided.
2  2
nmの厚さで形成されている。 High— k膜 73上には、ポリシリコンなど力もなる電極 7 4が形成されている。なお、 High— k膜 73は、例えば 800°Cの温度下で、約 10分間 Nガス ZOガスを供給することによって形成される。  It is formed with a thickness of nm. On the high-k film 73, an electrode 74 having a force such as polysilicon is formed. The high-k film 73 is formed by supplying N gas ZO gas for about 10 minutes at a temperature of 800 ° C., for example.
2 2  twenty two
[0078] 第一チャンバ一 1では、ウェハから 100〜200mm離した、波長が約 308nmの XeC 1ランプ 4灯から、約 5〜15mWZcm2の照度で、 2〜4分程度の時間、光を照射する [0078] In the first chamber 1, light is irradiated for about 2 to 4 minutes at an illuminance of about 5 to 15 mWZcm 2 from four XeC 1 lamps having a wavelength of about 308 nm separated from the wafer by 100 to 200 mm. Do
[0079] つぎに、第二チャンバ一 2では、ウェハから 100〜200mm離した、波長が約 172η mの Xeランプ 4灯から、約 4〜8mWZcm2の照度で、 1〜3分程度の時間、光を照射 する。 [0079] Next, in the second chamber 12, the illuminance of about 4 to 8 mWZcm 2 from the four Xe lamps having a wavelength of about 172 ηm, 100 to 200 mm away from the wafer, and the time of about 1 to 3 minutes, Irradiate light.
[0080] 第一チャンバ一 1及び第二チャンバ一 2は、圧力が約 lTorrの減圧状態、温度が 約 500°C、窒素ガスを含む種々の不活性ガス雰囲気である。  [0080] The first chamber 1 and the second chamber 1 are various inert gas atmospheres including a reduced pressure state with a pressure of about lTorr, a temperature of about 500 ° C, and nitrogen gas.
[0081] さらに、クリーニングは、約 lTorrの減圧下において、酸素ガス供給量を例えば 100 ccZ分の割合で供給し、 UVランプを点灯させることによって処理する。その後、例え ば、 425°Cでフォーミングガス(Nガス ZHガス)処理を 30分程度の時間行う。  [0081] Further, the cleaning is performed by supplying an oxygen gas supply amount at a rate of, for example, 100 ccZ under a reduced pressure of about lTorr and turning on the UV lamp. After that, for example, the forming gas (N gas ZH gas) treatment is performed at 425 ° C for about 30 minutes.
2 2  twenty two
[0082] その結果、境界層 72中のチャージ密度を、 1 X 1012Zcm3に減少させることができ 、また HfO膜のリーク電流も低減できる。 As a result, the charge density in the boundary layer 72 can be reduced to 1 × 10 12 Zcm 3, and the leakage current of the HfO film can also be reduced.
2  2
[0083] (実施形態 7)  [0083] (Embodiment 7)
ところで、上記各実施形態では、 2種類の波長の光を照射するランプを用いた半導 体製造装置等について説明したが、図 3,図 4を用いて説明したように、ランプの波長 を規定することで、絶縁膜の改質を行うことは可能である。  By the way, in each of the above embodiments, a semiconductor manufacturing apparatus using a lamp that emits light of two types of wavelengths has been described. However, as described with reference to FIGS. 3 and 4, the wavelength of the lamp is defined. By doing so, it is possible to modify the insulating film.
[0084] SiN膜の場合、 H—N、 H— Siなどの水素が関係する結合基が存在する。これらの 結合基を切断するために必要な波長は、それぞれ、 353nm、 399nmである。また、 約 240nmが吸収端に対応する波長である。これらのことから、 SiN膜に対して、 180 nm以上 400nm以下の波長の光を照射すると、絶縁膜の機械的強度を高め、かつ、 誘電率を低くすることができる。 [0085] SiCH膜の場合、 H— N、 C— H、 H— Siなどの水素が関係する結合基が存在する 。これらの結合基を切断するために必要な波長は、それぞれ 353nm、 353nm、 399 nmである。また、約 265nmが吸収端に対応する波長である。これらのことから、 SiC H膜に対して、 180nm以上 400nm以下の波長の光を照射すると、絶縁膜の機械的 強度を高め、かつ、誘電率を低くすることができる。 [0084] In the case of a SiN film, there are bonding groups related to hydrogen, such as H-N and H-Si. The wavelengths required to cleave these bonding groups are 353 nm and 399 nm, respectively. Also, about 240 nm is the wavelength corresponding to the absorption edge. Therefore, when the SiN film is irradiated with light having a wavelength of 180 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be decreased. [0085] In the case of the SiCH film, there are bonding groups related to hydrogen such as H—N, C—H, and H—Si. The wavelengths required to cleave these linking groups are 353 nm, 353 nm, and 399 nm, respectively. Moreover, about 265 nm is a wavelength corresponding to the absorption edge. For these reasons, when the SiC H film is irradiated with light having a wavelength of 180 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be decreased.
[0086] SiCNH膜の場合には、 H— N、 C H、 H— Siなどの水素が関係する結合基が存 在する。これらの結合基を切断するために必要な波長は、それぞれ、 274nm、 353η m、 353nm、 399nmである。また、約 265nmが吸収端に対応する波長である。これ らのこと力 、 SiCNH膜に対して、 274nm以上 400nm以下の波長の光を照射する と、絶縁膜の機械的強度を高め、かつ、誘電率を低くすることができる。  [0086] In the case of a SiCNH film, hydrogen-related bonding groups such as H—N, C H, and H—Si exist. The wavelengths necessary for cleaving these bonding groups are 274 nm, 353 ηm, 353 nm, and 399 nm, respectively. Moreover, about 265 nm is a wavelength corresponding to the absorption edge. For these reasons, when the SiCNH film is irradiated with light having a wavelength of 274 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be lowered.
[0087] SiOCNH膜の場合には、 H— 0、 H— N、 C— H、 H— Siなどの水素が関係する結 合基が存在する。これらの結合基を切断するために必要な波長は、それぞれ、 280η m、 353nm、 353nm、 399nmである。また、約 156から 263nmが吸収端に対応す る波長であるが、 Cや Nの濃度がある数パーセント以上あることを考えて吸収端に対 応する波長は 180nm程度と考えられる。したがって、 SiOCNH膜に対して、 180nm 以上 400nm以下の波長の光を照射すると、絶縁膜の機械的強度を高め、かつ、誘 電率を低くすることができる。  [0087] In the case of a SiOCNH film, there are hydrogen-related bonding groups such as H-0, H-N, C-H, and H-Si. The wavelengths necessary to cleave these bonding groups are 280ηm, 353nm, 353nm, and 399nm, respectively. The wavelength corresponding to the absorption edge is about 156 to 263 nm, but the wavelength corresponding to the absorption edge is considered to be about 180 nm considering that the concentration of C and N is more than a few percent. Therefore, when the SiOCNH film is irradiated with light having a wavelength of 180 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be decreased.
[0088] SiOCH膜の場合には、 H— 0、 H— N、 C— H、 H— Siなどの水素が関係する結合 基が存在する。これらの結合基を切断するために必要な波長は、それぞれ、 280nm 、 353nm、 353nm、 399nmである。また、約 156nmが吸収端に対応する波長であ る。これらのこと力 、 SiOCH膜に対して、 156nm以上 400nm以下の波長の光を照 射すると、絶縁膜の機械的強度を高め、かつ、誘電率を低くすることができる。  [0088] In the case of the SiOCH film, there are bonding groups related to hydrogen such as H-0, H-N, C-H, H-Si. The wavelengths necessary for cleaving these bonding groups are 280 nm, 353 nm, 353 nm, and 399 nm, respectively. Also, the wavelength corresponding to the absorption edge is about 156 nm. For these reasons, when the SiOCH film is irradiated with light having a wavelength of 156 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be lowered.
[0089] SiON膜の場合には、 H— 0、 N—H、 H— Siなどの水素が関係する結合基が存在 する。この結合基を切断するために必要な波長は、 280nm、 353nm、 399nmであ る。また、約 263nmが吸収端に対応する波長である。これらのことから、 SiON膜に 対して、 263nm以上 400nm以下の波長の光を照射すると、絶縁膜の機械的強度を 高め、かつ、誘電率を低くすることができる。  [0089] In the case of a SiON film, hydrogen-related bonding groups such as H-0, N-H, and H-Si are present. The wavelengths necessary for cleaving this bonding group are 280 nm, 353 nm, and 399 nm. In addition, about 263 nm is a wavelength corresponding to the absorption edge. Therefore, when the SiON film is irradiated with light having a wavelength of 263 nm or more and 400 nm or less, the mechanical strength of the insulating film can be increased and the dielectric constant can be lowered.
[0090] (実施形態 8) 図 17は、第一チャンバ一 1及び第二チャンバ一 2内に設けたウェハ 7の位置ズレを 防止する防止リング 8Aの模式的な構成図である。なお、図 17には、既述のウェハ 7 及びヒーター 6も示して!/、る。 [0090] (Embodiment 8) FIG. 17 is a schematic configuration diagram of the prevention ring 8A for preventing the positional deviation of the wafer 7 provided in the first chamber 11 and the second chamber 12. As shown in FIG. FIG. 17 also shows the wafer 7 and the heater 6 described above!
[0091] 本発明の実施形態 8に係る第一チャンバ一 1及び第二チャンバ一 2は、ウェハ 7が 静電気を帯びて位置ズレしょうとすることを防止するものである。なお、静電気自体を 除去するために防止リング 8Aを、除電リングとしてもよい。防止リング 8Aは、ヒーター 6上であって、ウェハ 7の周辺を囲う態様で使用される。  The first chamber 1 and the second chamber 1 according to Embodiment 8 of the present invention prevent the wafer 7 from being misaligned due to static electricity. In order to eliminate static electricity itself, the prevention ring 8A may be a static elimination ring. The prevention ring 8A is used on the heater 6 so as to surround the periphery of the wafer 7.
[0092] ここで、ランプ 3から紫外光などをウェハ 7に対して照射すると、これに起因してゥ ノ、 7とヒーター 6との間に正負の電荷、すなわち静電気が発生する。この結果、ウェハ 7とヒーター 6とが相互に引き合うことになる。この状態で、所定の処理後にウェハ 7を ヒーター 6から離すために昇降ステージを降下させると、当該静電気によってウェハ 7 力 Sヒーター 6に対して位置ズレする場合がある。  Here, when the wafer 7 is irradiated with ultraviolet light or the like from the lamp 3, positive and negative charges, that is, static electricity are generated between the uno 7 and the heater 6. As a result, the wafer 7 and the heater 6 attract each other. In this state, if the elevating stage is lowered in order to separate the wafer 7 from the heater 6 after predetermined processing, the wafer 7 force S may be displaced due to the static electricity.
[0093] 通常、チャンバ一には、この位置ズレを検知するセンサーが設けられている。したが つて、上記位置ズレが所定量以上となると、このセンサーが反応して、製造工程がス トップする。これでは、継続的な処理ができなくなり、製造スループットが低下する。  [0093] Usually, the chamber 1 is provided with a sensor for detecting this positional deviation. Therefore, when the positional deviation exceeds a predetermined amount, the sensor reacts to stop the manufacturing process. As a result, continuous processing cannot be performed, and manufacturing throughput is reduced.
[0094] そこで、上記のように、第一チャンバ一 1及び第二チャンバ一 2内に、ウェハ 7がず れても上記センサーが反応しないように防止リング 8Aを設け、ウェハ 7を防止リング 8 Aの内壁で止められるようにしている。なお、除電リング 8Aとする場合には、少なくと も表面をポリシリコン、単結晶シリコン又はアルミニウムなどとすればよい。  [0094] Therefore, as described above, the prevention ring 8A is provided in the first chamber 11 and the second chamber 12 so that the sensor does not react even if the wafer 7 is displaced, thereby preventing the wafer 7 from being attached to the prevention ring 8. It can be stopped by the inner wall of A. In the case of the neutralizing ring 8A, at least the surface may be made of polysilicon, single crystal silicon, aluminum, or the like.
[0095] なお、除電リング 8Aの形状は、図 17に示す態様に限定されず、例えば直方体、立 方体などの形状としてもよい。この種の除電体は、ヒーター 6上であってウェハ 7の搬 入 Z搬出に邪魔にならない位置に載置すればよい。ただし、例えば、図 18に示すよ うに、略虹状の複数の除電リング片 8Bとすると、除電リング片 8Bで囲まれた位置にゥ ェハ 7が搬入されやすくなるため、ウェハ 7の位置ズレが生じにくい。直方体等の除電 体、除電リング片 8Bのいずれの場合であっても、除電リング 8Aに比して、作成は容 易である。  Note that the shape of the static elimination ring 8A is not limited to the mode shown in FIG. 17, and may be, for example, a rectangular parallelepiped or a cuboid. This type of static eliminator may be placed on the heater 6 at a position that does not interfere with the loading and unloading of the wafer 7. However, for example, as shown in FIG. 18, if a plurality of substantially rainbow-shaped neutralization ring pieces 8B are used, the wafer 7 is easily carried into the position surrounded by the static elimination ring pieces 8B. Is unlikely to occur. Whether it is a static elimination body such as a rectangular parallelepiped or the static elimination ring piece 8B, it is easier to create than the static elimination ring 8A.
[0096] さらに、発生した静電気を除去することができれば、除電リング 8A等を備えることは 必須ではない。たとえば、除電リング 8A等を備えることに代え又はこれと共に、ピン 8 を除電ピンとすることもできる。除電ピンは、少なくとも表面がポリシリコン、単結晶シリ コン又はアルミニウムなどとすればよい。 [0096] Further, if the generated static electricity can be removed, it is not essential to provide the static elimination ring 8A or the like. For example, instead of providing a static elimination ring 8A etc. Can be used as a static elimination pin. The static elimination pin may be made of at least a surface such as polysilicon, single crystal silicon, or aluminum.
[0097] 同様に、ヒーター 6等の表面に、ポリシリコン薄膜、ァモーファスシリコン薄膜、 SiN 薄膜、 SiC膜又は SiOC膜を形成することもできる。薄膜の厚さは、限定的ではない 力 一例としては、 500〜10000オングストローム程度とすることができる。  Similarly, a polysilicon thin film, amorphous silicon thin film, SiN thin film, SiC film, or SiOC film can be formed on the surface of the heater 6 or the like. The thickness of the thin film is not limited. As an example, the thickness of the thin film can be about 500 to 10,000 angstroms.
[0098] 例えば、ポリシリコン薄膜は、プラズマ CVD法、スパッタ法又は減圧 CVD法により、 例えば、 380KHzの高周波 562Wをヒーター 6に印加して、基板温度表面 350°C、 圧力 0. 6Torr環境下で、 SiHを 100cc/min流すことで、約 5000〜10000オング  [0098] For example, a polysilicon thin film is formed by plasma CVD, sputtering, or low pressure CVD, for example, by applying a high frequency 562 W of 380 KHz to the heater 6 under a substrate temperature surface of 350 ° C and a pressure of 0.6 Torr. Approx. 5,000 to 10,000 angstroms by flowing SiH at 100cc / min
4  Four
ストロームの厚さのものを形成可能である。 SiN薄膜は、プラズマ CVD法、スパッタ法 又は減圧 CVD法により、例えば、 380KHzの高周波 562Wをヒーター 6に印加して、 基板温度表面 350°C、圧力 0. 6Torr環境下で、 SiHを 100ccZmin  A strom thickness can be formed. SiN thin film is formed by plasma CVD method, sputtering method or low pressure CVD method, for example, applying high frequency 562W of 380KHz to heater 6, substrate temperature surface 350 ° C, pressure 0.6 Torr environment, SiH 100ccZmin
4 、 NH3を 500 4, NH3 500
OccZminの割合で流すことで、 3000〜5000オングストロームの厚さのものを形成 可能である。 By flowing at a rate of OccZmin, a thickness of 3000 to 5000 angstroms can be formed.
[0099] ヒーター 6等の表面に SiN薄膜を形成した場合には、シリコンリッチなものを用いると 、電流が流れやすくなるため、ウェハ 7がヒーター 6へ吸着しに《望ましい。特に、ヒ 一ター 6等の表面に SiC膜や SiOC膜を形成した場合には、ヒーター 6又は除電リン グ 8Aのアルミニウム成分などがウェハ 7を汚染しな 、ようにすることができると 、う副 次的効果を得ることもできる。  [0099] When a SiN thin film is formed on the surface of the heater 6 or the like, if a silicon-rich material is used, it becomes easier for the current to flow. In particular, when a SiC film or SiOC film is formed on the surface of the heater 6 or the like, the aluminum component of the heater 6 or the static elimination ring 8A can be prevented from contaminating the wafer 7. A secondary effect can also be obtained.
[0100] (実施形態 9)  [0100] (Embodiment 9)
図 19〜図 21は、図 8,図 9に示したウェハ 7の製造工程の変形例を示す図である。 ここでは、 Pチャネルトランジスタをコンプレツシブ膜とし、かつ、 Nチャネルトランジス タにテンスル膜とする手法について説明する。  FIGS. 19 to 21 are views showing a modification of the manufacturing process of the wafer 7 shown in FIGS. Here, we explain the method of using a P-channel transistor as a compressive film and an N-channel transistor as a tensle film.
[0101] 本実施形態では、まず、ウェハ 7のソース領域 53及びドレイン領域 54側のトランジ スタ、つまり、 Pチャネルトランジスタに、紫外光吸収材であるところの約 lOOnmの厚 さのポリシリコン薄膜 64を形成する。この状態で、 Pチャネルトランジスタ及び Nチヤネ ルトランジスタに、低圧水銀の UV光を、例えば、 400°Cで照度 14mWZcm2で 5分 間照射する(図 19)。  [0101] In this embodiment, first, a polysilicon thin film 64 having a thickness of about lOOnm, which is an ultraviolet light absorber, is applied to a transistor on the source region 53 and drain region 54 side of the wafer 7, that is, a P-channel transistor. Form. In this state, UV light of low-pressure mercury is irradiated to the P-channel transistor and N-channel transistor for 5 minutes at 400 ° C and illuminance of 14 mWZcm2, for example (Fig. 19).
[0102] これにより、 Nチャネルトランジスタ側の SiN膜 57は、約 1. 5GPaのテンスルストレス となる。なお、紫外光吸収材の条件は、当該吸収を実現するためのバンドギャップを 有していて、約 400°Cという加熱に耐えられるものであれば、ポリシリコンに限定され るものではない。 [0102] As a result, the SiN film 57 on the N-channel transistor side has a tensile stress of about 1.5 GPa. It becomes. The conditions of the ultraviolet light absorbing material are not limited to polysilicon as long as it has a band gap for realizing the absorption and can withstand the heating of about 400 ° C.
[0103] つづいて、 Pチャネルトランジスタに形成したポリシリコン薄膜 64を除去する(図 20) 。これにより、 Nチャネルトランジスタ側の SiN膜 57だけがテンスルストレスとなる。  Next, the polysilicon thin film 64 formed on the P-channel transistor is removed (FIG. 20). As a result, only the SiN film 57 on the N channel transistor side is subjected to tensile stress.
[0104] その後、 Nチャネルトランジスタを、厚いレジスト膜 65で覆い、イオン注入機を用い て、例えば、 5 X 1015ドーズで N+イオンを Pチャネルトランジスタ側の SiN膜 57の中 心に打ち込む(図 21)。このとき、 Nチャネルトランジスタ側の SiN膜 57は、レジスト膜 65によって保護されているためにストレスの変化は生じない。 一方、 Pチャネルトラン ジスタ側の SiN膜 57は、ストレスがコンプレツシブとなり約 lGPaの大きさとなる。  [0104] Thereafter, the N channel transistor is covered with a thick resist film 65, and N + ions are implanted into the center of the SiN film 57 on the P channel transistor side, for example, at a dose of 5 X 1015 using an ion implanter (Fig. 21). ). At this time, since the SiN film 57 on the N channel transistor side is protected by the resist film 65, the stress does not change. On the other hand, the SiN film 57 on the P channel transistor side is stressed and becomes about lGPa.
[0105] それから、 Nチャネルトランジスタを覆っているレジスト膜 65を除去することで、図 8 に示すウェハ 7となる。  Then, by removing the resist film 65 covering the N-channel transistor, the wafer 7 shown in FIG. 8 is obtained.
実施例  Example
[0106] (実施例 1) [Example 1]
図 1又は図 17などに示す半導体製造装置を用いて、以下の条件で Low— k膜 33 の処理を経て、実際に半導体デバイスを製造した。  Using the semiconductor manufacturing apparatus shown in FIG. 1 or FIG. 17 and the like, the semiconductor device was actually manufactured through the low-k film 33 treatment under the following conditions.
[0107] 第一チャンバ一 1のランプ 3 :波長が約 300nm以上 770nm以下となる高圧水銀ラ ンプを 4灯、照度が約 8mWZcm2、照射時間約 4分、 [0107] Lamp 1 in the first chamber 3: Four high-pressure mercury lamps with a wavelength of about 300 nm to 770 nm, illumination of about 8 mWZcm 2 , irradiation time of about 4 minutes,
第二チャンバ一 2の低圧水銀ランプ:波長が約 186nm及び約 254nmとなるもの 4 灯、照度が約 3mWZcm2、照射時間約 1分、 Low pressure mercury lamp in the second chamber: 4 lamps with wavelengths of about 186 nm and about 254 nm, illuminance of about 3 mWZcm 2 , irradiation time of about 1 minute,
第一チャンバ一 1及び第二チャンバ一 2 : lTorrの減圧状態、温度が約 400°C、窒 素ガスを含む種々の不活性ガス雰囲気、さら〖こ、クリーニング条件が lTorrの減圧下 にお!/ヽて酸素ガス供給量を lOOccZ分、  1st chamber 1 and 1st chamber 2: lTorr depressurized condition, temperature of about 400 ° C, various inert gas atmospheres including nitrogen gas, cleaning, and cleaning conditions under lTorr depressurized! / Large oxygen gas supply volume for lOOccZ,
ウェハ 7:直径約 300mmで、厚さが約 300nmの SiOCH膜が形成されて!ヽる。  Wafer 7: A SiOCH film with a diameter of about 300 mm and a thickness of about 300 nm is formed!
[0108] この結果、ウェハ 7の機械的強度を示すヤング率は 8GPaになった。誘電率は 2. 4 になった。 As a result, the Young's modulus indicating the mechanical strength of the wafer 7 was 8 GPa. The dielectric constant was 2.4.
[0109] (実施例 2) [Example 2]
図 6又は図 17などに示す半導体製造装置を用いて、以下の条件で Low— k膜 33 の処理を経て、実際に半導体デバイスを製造した。 Using the semiconductor manufacturing equipment shown in Fig. 6 or 17 etc., low-k film 33 under the following conditions: Through these processes, a semiconductor device was actually manufactured.
[0110] ランプ 3 :波長が約 300nm以上 770nm以下となる高圧水銀ランプ 4灯、照度が約 4 mW/cm2,照射時間約 4分、 [0110] Lamp 3: Four high-pressure mercury lamps with a wavelength of about 300 nm to 770 nm, illuminance of about 4 mW / cm 2 , irradiation time of about 4 minutes,
ランプ 21:波長が約 186nm及び約 254nmとなる低圧水銀ランプ 4灯、照度が約 3 mW/cm2,照射時間約 1分、 Lamp 21: 4 low-pressure mercury lamps with wavelengths of about 186 nm and 254 nm, illuminance of about 3 mW / cm 2 , irradiation time of about 1 minute,
チャンバ一: lTorrの減圧状態、温度が約 250°C、窒素ガスを含む種々の不活性 ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供給量を lOOcc/分、  Chamber 1: lTorr decompression state, temperature is about 250 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply rate is lOOcc / min under cleaning conditions of lTorr decompression,
ウェハ 7:直径約 300mmで、厚さが約 300nmの SiOCH膜が形成されて!ヽる。  Wafer 7: A SiOCH film with a diameter of about 300 mm and a thickness of about 300 nm is formed!
[0111] この結果、ウェハ 7の機械的強度を示すヤング率は 8GPaになった。誘電率は 2. 4 になった。 As a result, the Young's modulus indicating the mechanical strength of the wafer 7 was 8 GPa. The dielectric constant was 2.4.
[0112] (実施例 3) [0112] (Example 3)
図 1又は図 17などに示す半導体製造装置を用いて、以下の条件で SiN膜 57の処 理を経て、実際に半導体デバイスを製造した。  A semiconductor device was actually manufactured by processing the SiN film 57 under the following conditions using the semiconductor manufacturing apparatus shown in FIG. 1 or FIG.
[0113] 第一チャンバ一 1内のランプ 3 :波長が約 341nmの Iランプ 4灯、照度が約 13mW [0113] Lamp 1 in chamber 1 3: 4 I lamps with a wavelength of about 341 nm, illuminance of about 13 mW
2  2
照射時間約 2分、  Irradiation time about 2 minutes,
第二チャンバ一 2内のランプ:波長が約 282nmの XeBrランプ 4灯、照度が約 13m W/cm2,照射時間約 2分、 Lamp in the second chamber 12: 4 XeBr lamps with a wavelength of about 282nm, illuminance of about 13m W / cm 2 , irradiation time of about 2 minutes,
第一チャンバ一 l : lTorrの減圧状態、温度が約 400°C、窒素ガスを含む種々の不 活性ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供給 量を lOOccZ分、  1st chamber l: lTorr decompression state, temperature is about 400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount is lOOccZ for cleaning conditions under reduced pressure of lTorr,
第二チャンバ一 2 : lTorrの減圧状態、温度が約 400°C、窒素ガスを含む種々の不 活性ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供給 量を lOOccZ分、  Second chamber 1: lTorr decompression state, temperature is about 400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount is lOOccZ for lTorr under reduced pressure
ウェハ 7 :直径約 300mm、 DRAMが形成されていて、カバー SiO膜上には、カバ  Wafer 7: Diameter is about 300 mm, DRAM is formed, and the cover SiO film has a cover.
2  2
一 SiN膜力 S約 300 nmの厚さで形成されている。  One SiN film force S is formed with a thickness of about 300 nm.
[0114] その結果、カバー SiN膜 57の水素濃度を低減することができ、 DRAMのゲート— ドレイン領域のリーク電流を低減でき、データリテンションタイムを長くすることができ、 不良率を低減できた。 As a result, the hydrogen concentration in the cover SiN film 57 can be reduced, the leakage current in the DRAM gate-drain region can be reduced, and the data retention time can be increased. The defective rate could be reduced.
[0115] (実施例 4)  [0115] (Example 4)
図 1又は図 17などに示す半導体製造装置を用いて、以下の条件で SiN膜 57の処 理を経て、実際に半導体デバイスを製造した。  A semiconductor device was actually manufactured by processing the SiN film 57 under the following conditions using the semiconductor manufacturing apparatus shown in FIG. 1 or FIG.
[0116] 第一チャンバ一 1内のランプ 3 :波長が約 341nmの Iランプ 4灯、照度が約 13mW [0116] Lamp 1 in the first chamber 1: 4 I lamps with a wavelength of about 341nm, illuminance of about 13mW
2  2
照射時間約 2分、  Irradiation time about 2 minutes,
第二チャンバ一 2内のランプ:波長が約 308nmの XeClランプ 4灯、照度が約 13m W/cm2,照射時間約 2分、 Lamp in the second chamber 1-2: 4 XeCl lamps with a wavelength of about 308nm, illuminance of about 13m W / cm 2 , irradiation time of about 2 minutes,
第一チャンバ一 l : lTorrの減圧状態、温度が約 250°C、窒素ガスを含む種々の不 活性ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供給 量を lOOccZ分、  1st chamber l: lTorr decompression state, temperature is about 250 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount is lOOccZ for lTorr under reduced pressure cleaning condition
第二チャンバ一 2 : lTorrの減圧状態、温度が約 350°C、窒素ガスを含む種々の不 活性ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供給 量を lOOccZ分、  Second chamber 1: lTorr decompression state, temperature is about 350 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply volume is lOOccZ for cleaning conditions of lTorr decompression,
ウェハ 7 :直径約 300mm、 DRAMが形成されていて、トランジスタにサイドウォール SiN膜が約 300nmの厚さで形成されて!、る。  Wafer 7: A diameter of about 300 mm, DRAM is formed, and a sidewall SiN film is formed on the transistor with a thickness of about 300 nm!
[0117] 半導体製造装置の処理前後の機械的強度を測定した結果、処理前には 2 X 109d yneZcm2の引っ張り応力であつたのに対して、処理後には 2 X 101GdyneZcm2の 引っ張り応力であった。この結果、ソース ドレイン電流が増大した。 [0117] As a result of measuring the mechanical strength of the semiconductor manufacturing apparatus before and after the treatment, the tensile stress was 2 X 10 9 dyneZcm 2 before the treatment, whereas 2 X 10 1G dyneZcm 2 was obtained after the treatment. It was tensile stress. As a result, the source / drain current increased.
[0118] (実施例 5)  [0118] (Example 5)
図 1又は図 17などに示す半導体製造装置を用いて、以下の条件で Low— k膜 33 の処理を経て、実際に半導体デバイスを製造した。  Using the semiconductor manufacturing apparatus shown in FIG. 1 or FIG. 17 and the like, the semiconductor device was actually manufactured through the low-k film 33 treatment under the following conditions.
[0119] 第一チャンバ一 1のハロゲンランプ:波長が約 400以上 770nm以下となるもの 4灯 、照度が約 15mWZcm2、照射時間約 2分、 [0119] Halogen lamp in the first chamber: 4 lamps with a wavelength of about 400 or more and 770 nm or less, illuminance of about 15mWZcm 2 , irradiation time of about 2 minutes,
第二チャンバ一 2の低圧水銀ランプ:波長が約 186nm及び約 254nmとなるもの 4 灯、照度が約 3mWZcm2、照射時間約 2分、 Low pressure mercury lamp in the second chamber: 4 lamps with wavelengths of about 186 nm and about 254 nm, illumination intensity of about 3 mWZcm 2 , irradiation time of about 2 minutes,
第一チャンバ一 1及び第二チャンバ一 2 : lTorrの減圧状態、温度が約 400°C、窒 素ガスを含む種々の不活性ガス雰囲気、さら〖こ、クリーニング条件が lTorrの減圧下 にお!/ヽて酸素ガス供給量を lOOccZ分、 1st chamber 1 and 1st chamber 2: lTorr depressurized condition, temperature is about 400 ° C, various inert gas atmospheres including nitrogen gas, vacuum, cleaning conditions are lTorr depressurized /! Oxygen gas supply volume for lOOccZ minutes,
ウェハ 7:直径約 300mm、 SiOCH膜が約 300nmの厚さで形成されて!ヽる。  Wafer 7: A diameter of about 300 mm and a SiOCH film with a thickness of about 300 nm are formed!
[0120] この結果、ウェハ 7の機械的強度を示すヤング率は 8GPaになった。誘電率は 2. 4 になった。 As a result, the Young's modulus indicating the mechanical strength of the wafer 7 was 8 GPa. The dielectric constant was 2.4.
[0121] (実施例 6) [0121] (Example 6)
図 1又は図 17などに示す半導体製造装置を用いて、以下の条件で SOD膜 33の 処理を経て、実際に半導体デバイスを製造した。  Using the semiconductor manufacturing apparatus shown in FIG. 1 or FIG. 17 and the like, the semiconductor device was actually manufactured through the processing of the SOD film 33 under the following conditions.
[0122] 第一チャンバ一 1内のランプ 3 :波長が約 308nmの XeClランプ 4灯、 [0122] Lamp 1 in the first chamber 1 3: 4 XeCl lamps with a wavelength of about 308 nm,
照度が約 10mWZcm2、照射時間約 4分、 Illuminance is about 10mWZcm 2 , irradiation time is about 4 minutes,
第二チャンバ一 2内のランプ:波長が約 172nmの Xeランプ 4灯、照度が約 4mWZ cm2,照射時間約 1分、 Lamp in the second chamber 1-2: 4 Xe lamps with a wavelength of about 172 nm, illuminance of about 4 mWZ cm 2 , irradiation time of about 1 minute,
第一チャンバ一 1及び第二チャンバ一 2 : lTorrの減圧状態、温度が約 350°C、窒 素ガスを含む種々の不活性ガス雰囲気、さら〖こ、クリーニング条件が lTorrの減圧下 にお!/ヽて酸素ガス供給量を lOOccZ分、  1st chamber 1 and 1st chamber 2: lTorr reduced pressure, temperature about 350 ° C, various inert gas atmospheres including nitrogen gas, cleaning, cleaning conditions lTorr reduced pressure! / Large oxygen gas supply volume for lOOccZ,
ウェハ 7:直径約 300mm、 SOD膜 33が約 300nmの厚さで形成されて!ヽる。  Wafer 7: A 300 mm diameter, SOD film 33 is formed with a thickness of about 300 nm!
[0123] この結果、ウェハ 7の機械的強度を示すヤング率は 8GPaになった。誘電率は 2. 3 になった。 As a result, the Young's modulus indicating the mechanical strength of the wafer 7 was 8 GPa. The dielectric constant was 2.3.
[0124] (実施例 7) [0124] (Example 7)
図 1又は図 17などに示す半導体製造装置を用いて、以下の条件で HfO膜 33の  Using the semiconductor manufacturing equipment shown in Fig. 1 or 17, etc., the HfO film 33 is
2 処理を経て、実際に半導体デバイスを製造した。  2 After processing, a semiconductor device was actually manufactured.
[0125] 第一チャンバ一 1内のランプ 3 :波長が約 308nmの XeClランプ 4灯、照度が約 10 mW/cm2,照射時間約 4分、 [0125] Lamp 3 in the first chamber 1: 4 XeCl lamps with a wavelength of about 308 nm, illuminance of about 10 mW / cm 2 , irradiation time of about 4 minutes,
第二チャンバ一 2内のランプ:波長が約 172nmの Xeランプ 4灯、照度が約 4mWZ cm2,照射時間約 1分、 Lamp in the second chamber 1-2: 4 Xe lamps with a wavelength of about 172 nm, illuminance of about 4 mWZ cm 2 , irradiation time of about 1 minute,
第一チャンバ一 1及び第二チャンバ一 2 : lTorrの減圧状態、温度が約 500°C、窒 素ガスを含む種々の不活性ガス雰囲気、さら〖こ、クリーニング条件が lTorrの減圧下 にお!/ヽて酸素ガス供給量を lOOccZ分、  1st chamber 1 and 1st chamber 2: lTorr depressurized state, temperature is about 500 ° C, various inert gas atmospheres containing nitrogen gas, cleaning, cleaning conditions are lTorr depressurized! / Large oxygen gas supply volume for lOOccZ,
ウェハ 7 :直径約 300mmであり、厚さ約 lnmの SiOリッチの境界層と、境界層上に 形成された約 5nmの厚さの HfO膜とが形成されて 、る。 Wafer 7: SiO-rich boundary layer with a diameter of about 300mm and a thickness of about lnm, and on the boundary layer The formed HfO film having a thickness of about 5 nm is formed.
2  2
[0126] その結果、境界層中のチャージ密度を、 1 X 1012Zcm3に減少させることができ、ま た HfO膜のリーク電流も低減できた。 As a result, the charge density in the boundary layer could be reduced to 1 × 10 12 Zcm 3 and the leakage current of the HfO film could be reduced.
2  2
[0127] (実施例 8)  [Example 8]
図 6又は図 17などに示す半導体製造装置を用いて、実際に半導体デバイスを製造 した。本実施例では、図 13に示す Cu配線層 21上に形成されたノリア一絶縁膜 (Si OC膜) 22を高密度にする例について説明する。  A semiconductor device was actually manufactured using the semiconductor manufacturing apparatus shown in FIG. In this embodiment, an example in which the noria one insulating film (SiOC film) 22 formed on the Cu wiring layer 21 shown in FIG.
[0128] ランプ:波長が約 222nmである KrClランプ 4灯、照度が約 4 [0128] Lamp: 4 KrCl lamps with a wavelength of about 222 nm, illuminance of about 4
2 〜15mWZcm2、照 射時間約 1〜2分、ウェハ 7までの距離が約 10〜20cm、 2 to 15mWZcm 2 , irradiation time about 1 to 2 minutes, distance to wafer 7 about 10 to 20cm,
チャンバ一: lTorrの減圧状態、温度力約 300〜400°C、窒素ガスを含む種々の 不活性ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供 給量を lOOccZ分、  Chamber 1: lTorr decompression state, temperature power of about 300-400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount of lOOccZ for cleaning conditions of lTorr decompression,
ウェハ 7 :直径約 300mmであり、図 13に示すように、 Cu配線層 21上に、厚さが約 3 Onmのバリアー膜であるところの SiOC膜 22が形成されている。  Wafer 7: Diameter is about 300 mm, and as shown in FIG. 13, a SiOC film 22, which is a barrier film having a thickness of about 3 Onm, is formed on the Cu wiring layer 21.
[0129] こうして改質した SiOC膜 22に対して、約 400°Cの温度で、 3時間の加熱処理を行 つても、 SiOC膜 22が高密度であるので、 SiOC膜 22からほとんどリーク電流が流れ なかった。  [0129] Even if the modified SiOC film 22 is subjected to heat treatment at a temperature of about 400 ° C for 3 hours, the SiOC film 22 has a high density, so that almost no leakage current flows from the SiOC film 22. It did not flow.
[0130] (実施例 9)  [0130] (Example 9)
図 6又は図 17などに示す半導体製造装置を用いて、実際に半導体デバイスを製造 した。本実施例では、図 14に示す Cu配線層 21上に Low— k膜 (SiOC膜) 22を介し て形成されたノリア一絶縁膜 23を開口して力ら堆積した PE— CVDSiN膜 24を、高 密度にする例について説明する。  A semiconductor device was actually manufactured using the semiconductor manufacturing apparatus shown in FIG. In this example, a PE-CVDSiN film 24 deposited by force by opening a Noria insulating film 23 formed via a low-k film (SiOC film) 22 on the Cu wiring layer 21 shown in FIG. An example of increasing the density will be described.
[0131] ランプ:波長が約 308nmである XeClランプ 4灯、照度が約 4〜15mWZcm2、照射 時間約 1〜2分、ウェハ 7までの距離が約 10〜20cm、 [0131] Lamp: 4 XeCl lamps with a wavelength of about 308 nm, illuminance of about 4-15 mWZcm 2 , irradiation time of about 1-2 minutes, distance to wafer 7 of about 10-20 cm,
チャンバ一: lTorrの減圧状態、温度力約 300〜400°C、窒素ガスを含む種々の 不活性ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供 給量を lOOccZ分、  Chamber 1: lTorr decompression state, temperature power of about 300-400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount of lOOccZ for cleaning conditions of lTorr decompression,
ウェハ 7 :直径約 300mmであり、図 14に示すように、基板側から Cu配線層 21、厚 さが約 30nmの Low— k膜であるところの SiOC膜 22、ノ リア一絶縁膜 23、 PE-CV DSiN膜 24が形成されて!、る。 Wafer 7: Diameter is about 300mm, as shown in Fig. 14, Cu wiring layer 21, thickness from substrate side A SiOC film 22, a NORI insulation film 23, and a PE-CV DSiN film 24, which are low-k films with a thickness of about 30 nm, are formed!
[0132] こうして改質した PE— CVDSiN膜 24に対して、図 15に示すように、拡散防止メタ ル 25, 26であるタンタル/窒化タンタル (TaZTaN)膜を形成し、ビア内に Cu配線 層 27を形成したウェハ 7に対して、約 400°Cの温度で、 3時間の加熱処理を行っても 、ビアホールの側面を形成する PE— CVDSiN 24が高密度であるので、 SiOC膜 22 に対して拡散防止メタル 25, 26内の Taが拡散しな力つた。  [0132] As shown in Fig. 15, a tantalum / tantalum nitride (TaZTaN) film, which is a diffusion prevention metal 25, 26, is formed on the PE-CVDSiN film 24 thus modified, and a Cu wiring layer is formed in the via. Even if the wafer 7 on which 27 is formed is heated at a temperature of about 400 ° C. for 3 hours, PE—CVDSiN 24 forming the side surface of the via hole has a high density. As a result, Ta in diffusion prevention metal 25 and 26 did not diffuse.
[0133] (実施例 10)  [Example 10]
ところで、シヤロートレンチ構造の素子分離(Shallow Trench Isolation: STI)領域を 有する DRAMでは、ワードラインにネガティブバイアスをかけると、ゲート ドレイン 間のリーク電流が大きくなるため、データのリテンション不良が発生している。また、 2 50°Cのパッケージ処理を行ったときにも、これらの現象が起きることが知られて 、る。  By the way, in a DRAM having a shallow trench isolation (Shallow Trench Isolation: STI) region, if a negative bias is applied to a word line, the leakage current between the gate and the drain increases, which causes a data retention failure. Yes. It is also known that these phenomena occur when packaging at 250 ° C.
[0134] このような現象の原因は、カバー SiN膜中の水素が起因していることがわかってき た。この水素がゲートとドレインとの重なりあう領域のチャネル領域の禁制帯中にトラッ プを発生させるものと思われる。  [0134] It has been found that this phenomenon is caused by hydrogen in the cover SiN film. This hydrogen is thought to generate traps in the forbidden band of the channel region where the gate and drain overlap.
[0135] 本実施例では、図 6又は図 17などに示す半導体製造装置を用いて、実際に半導 体デバイスを製造した。ここでは、図 16に示すシリコンウェハ 81に形成したトランジス タ 82上のカバー SiO膜 83を覆うカバー PE— CVDSiN膜 84を、高密度にする例に  In this example, a semiconductor device was actually manufactured using the semiconductor manufacturing apparatus shown in FIG. 6 or FIG. In this example, the cover PE-CVD SiN film 84 covering the cover SiO film 83 on the transistor 82 formed on the silicon wafer 81 shown in FIG.
2  2
ついて説明する。  explain about.
[0136] ランプ:波長が約 308nmである XeClランプ 4灯、照度が約 4〜15mWZcm2、照射 時間約 1〜2分、ウェハ 7までの距離が約 10〜20cm、 [0136] Lamp: 4 XeCl lamps with a wavelength of about 308 nm, illuminance of about 4-15 mWZcm 2 , irradiation time of about 1-2 minutes, distance to wafer 7 of about 10-20 cm,
チャンバ一: lTorrの減圧状態、温度力約 300〜400°C、窒素ガスを含む種々の 不活性ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供 給量を lOOccZ分、  Chamber 1: lTorr decompression state, temperature power of about 300-400 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply amount of lOOccZ for cleaning conditions of lTorr decompression,
ウェハ 7 :直径約 300mmであり、図 15に示すように、トランジスタ 82等が形成されて いる。  Wafer 7: Diameter is about 300 mm, and transistor 82 and the like are formed as shown in FIG.
[0137] こうして改質した、カバー PE— CVDSiN膜 84内の水素濃度を測定した結果、改質 前には約 30%あつたのに対して、改質後には約 10%になった。ちなみに、カバー P E - CVDSiN膜 84の CVD工程での圧力を変更することによって、カバー LP - CV DSiN膜に代えると、改質前には約 25%あつたのに対して、改質後には約 1%になつ た。 [0137] As a result of measuring the hydrogen concentration in the cover PE-CVDSiN film 84 thus modified, it was about 30% before the reforming and about 10% after the reforming. By the way, cover P By changing the pressure in the CVD process of the E-CVDSiN film 84, replacing it with the cover LP-CV DSiN film, it was about 25% before modification, but about 1% after modification. Natsu.
[0138] (実施例 11)  [Example 11]
本実施例では、実施例 4の変形例について説明する。図 6又は図 17などに示す半 導体製造装置を用いて、以下の条件で HfO膜 33の処理を経て、実際に半導体デ  In the present embodiment, a modification of the fourth embodiment will be described. Using the semiconductor manufacturing apparatus shown in FIG. 6 or FIG. 17 and the like, the HfO film 33 is processed under the following conditions, and the semiconductor device is actually processed.
2  2
バイスを製造した。  A vice was manufactured.
[0139] ランプ:波長が約 282nmの XeBrランプ 4灯、照度が約 5〜13mWZcm2、照射時 間約 3分、 [0139] Lamp: 4 XeBr lamps with a wavelength of about 282nm, illuminance of about 5-13mWZcm 2 , irradiation time of about 3 minutes,
チャンバ一: lTorrの減圧状態、温度が約 250°C、窒素ガスを含む種々の不活性 ガス雰囲気、さらに、クリーニング条件が lTorrの減圧下において酸素ガス供給量を lOOcc/分、  Chamber 1: lTorr decompression state, temperature is about 250 ° C, various inert gas atmospheres containing nitrogen gas, and oxygen gas supply rate is lOOcc / min under cleaning conditions of lTorr decompression,
ウェハ 7 :直径約 300mm、サイドウォールとなる LP— SiN膜が約 300nmの厚さで 形成されている。  Wafer 7: LP-SiN film with a diameter of about 300 mm and sidewalls is formed with a thickness of about 300 nm.
[0140] 半導体製造装置の処理前後の機械的強度を測定した結果、実施例 4と同様に、処 理前には 2 X 109dyneZcm2の引っ張り応力であつたのに対して、処理後には 2 X 1 01GdyneZcm2の引っ張り応力であった。この結果、ソース ドレイン電流が増大した 図面の簡単な説明 [0140] As a result of measuring the mechanical strength of the semiconductor manufacturing apparatus before and after the treatment, the tensile stress of 2 X 10 9 dyneZcm 2 was obtained before the treatment as in Example 4, whereas after the treatment, The tensile stress was 2 X 1 0 1G dyneZcm 2 . As a result, the source-drain current increased.
[0141] [図 1]本発明の実施形態 1の半導体製造装置の模式的な構成図である。 FIG. 1 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 1 of the present invention.
[図 2]図 1の第一チャンバ一 1の模式的な構成図である。  2 is a schematic configuration diagram of the first chamber 11 in FIG.
[図 3]照射光の波長と物質の結合エネルギーとの関係を示す図である。  FIG. 3 is a diagram showing the relationship between the wavelength of irradiated light and the binding energy of a substance.
[図 4]照射光の波長と吸収端と結合エネルギーとの関係を示す図である。  FIG. 4 is a diagram showing the relationship between the wavelength of irradiated light, the absorption edge, and the binding energy.
[図 5]図 2に示すウェハ 7の一部の模式的な断面図である。  5 is a schematic cross-sectional view of a part of the wafer 7 shown in FIG.
[図 6]本発明の実施形態 2の半導体製造装置の模式的な構成図である。  FIG. 6 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 2 of the present invention.
[図 7]図 6のチャンバ一 15の模式的な構成図である。  7 is a schematic configuration diagram of the chamber 15 in FIG. 6.
[図 8]図 2に示すウェハ 7の一部の模式的な断面図である。  8 is a schematic cross-sectional view of a part of the wafer 7 shown in FIG.
[図 9]図 8に示すウェハ 7の SiN膜 57の一部除去後の模式的な断面図である。 [図 10]本発明の実施形態 4の第一チャンバ一 1の模式的な構成図である。 9 is a schematic cross-sectional view after removing a part of the SiN film 57 of the wafer 7 shown in FIG. FIG. 10 is a schematic configuration diagram of a first chamber 11 according to Embodiment 4 of the present invention.
[図 11]本発明の実施形態 5の半導体製造装置の模式的な構成図である。  FIG. 11 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 5 of the present invention.
[図 12]本発明の実施形態 6の半導体デバイスとなるウェハ 7の一部の模式的な断面 図である。  FIG. 12 is a schematic cross-sectional view of a part of a wafer 7 to be a semiconductor device according to Embodiment 6 of the present invention.
[図 13]本発明の実施例の半導体デバイスの一部の断面図である。  FIG. 13 is a partial cross-sectional view of a semiconductor device according to an example of the present invention.
[図 14]本発明の実施例の半導体デバイスの一部の断面図である。  FIG. 14 is a partial cross-sectional view of a semiconductor device according to an example of the present invention.
[図 15]本発明の実施例の半導体デバイスの一部の断面図である。  FIG. 15 is a partial cross-sectional view of a semiconductor device according to an example of the present invention.
[図 16]本発明の実施例の半導体デバイスの一部の断面図である。  FIG. 16 is a partial cross-sectional view of a semiconductor device according to an example of the present invention.
[図 17]第一チャンバ一 1及び第二チャンバ一 2内に設けたウェハ 7の位置ズレを防止 する防止リング 8Aの模式的な構成図である。  FIG. 17 is a schematic configuration diagram of a prevention ring 8 A for preventing the positional deviation of the wafer 7 provided in the first chamber 11 and the second chamber 12.
[図 18]図 17の変形例を示す図である。  FIG. 18 is a diagram showing a modification of FIG.
[図 19]図 8,図 9に示したウェハ 7の製造工程の変形例を示す図である。  FIG. 19 is a diagram showing a modification of the manufacturing process of the wafer 7 shown in FIGS. 8 and 9.
[図 20]図 8,図 9に示したウェハ 7の製造工程の変形例を示す図である。 20 is a view showing a modification of the manufacturing process of the wafer 7 shown in FIGS. 8 and 9. FIG.
[図 21]図 8,図 9に示したウェハ 7の製造工程の変形例を示す図である。 FIG. 21 is a view showing a modification of the manufacturing process of the wafer 7 shown in FIGS. 8 and 9.
符号の説明 Explanation of symbols
1 第一チャンバ一  1 First chamber
2 第二チャンバ一  2 Second chamber 1
3 ランプ  3 Lamp
4 石英パイプ  4 Quartz pipe
5 不活性ガス  5 Inert gas
7 ウェハ  7 wafers
6 ヒーター  6 Heater
8 ピン  8 pin
9 受光センサー  9 Light sensor
11 配管  11 Piping
12 配管  12 Piping
13 マスフロー  13 Mass flow
14 バルブ フープ 14 Valve hoop
ウエノヽァライメント ロードロックチャンバ一 トランスファーチャンバ一 Weno alignment Load lock chamber 1 Transfer chamber 1

Claims

請求の範囲 The scope of the claims
[1] 絶縁膜に対して第 1の波長の紫外光を照射する第 1照射手段と、  [1] a first irradiation means for irradiating the insulating film with ultraviolet light having a first wavelength;
前記絶縁膜に対して第 1の波長とは異なる第 2の波長の紫外光または可視光を照 射する第 2照射手段と、  A second irradiation means for irradiating the insulating film with ultraviolet light or visible light having a second wavelength different from the first wavelength;
を備える、照射装置。  An irradiation apparatus comprising:
[2] 前記絶縁膜は、低誘電率膜であり、 [2] The insulating film is a low dielectric constant film,
前記光の一方は、絶縁膜内の安定状態にない結合基を切断するために必要な波 長以下の光であり、  One of the lights is light having a wavelength equal to or less than a wavelength necessary for cutting a bonding group that is not in a stable state in the insulating film,
前記光の他方は、吸収端以上の波長の光である、  The other of the lights is light having a wavelength longer than the absorption edge.
請求項 1記載の照射装置。  The irradiation apparatus according to claim 1.
[3] 前記絶縁膜は、配線間絶縁膜又はノリア一絶縁膜であり、 [3] The insulating film is an inter-wiring insulating film or a Noria one insulating film,
前記光の一方は、絶縁膜内の結合基を切断するために必要な波長以下の光であ り、  One of the lights is light having a wavelength equal to or shorter than a wavelength necessary for cutting the bonding group in the insulating film.
前記光の他方は、吸収端以上の波長の光である、  The other of the lights is light having a wavelength longer than the absorption edge.
請求項 1記載の照射装置。  The irradiation apparatus according to claim 1.
[4] 前記絶縁膜は、高誘電率ゲート絶縁膜であり、 [4] The insulating film is a high dielectric constant gate insulating film,
前記光の一方は、遷移金属の酸化に必要な波長または C H結合を切断するのに 必要な波長以下の光であり、  One of the lights is light having a wavelength less than a wavelength necessary for the oxidation of the transition metal or a wavelength necessary for breaking the CH bond,
前記各光の他方は、吸収端以上の波長の光である、  The other of the lights is light having a wavelength longer than the absorption edge.
請求項 1記載の照射装置。  The irradiation apparatus according to claim 1.
[5] 請求項 1から 4のいずれか記載の照射装置と、 [5] The irradiation device according to any one of claims 1 to 4,
前記絶縁膜を有するウェハを搬送する搬送装置と、  A transfer device for transferring a wafer having the insulating film;
を備える、半導体製造装置。  A semiconductor manufacturing apparatus comprising:
[6] 前記第 1及び第 2照射手段は、同一又は異なるチャンバ一に設けられている、 請求項 5記載の半導体製造装置。 6. The semiconductor manufacturing apparatus according to claim 5, wherein the first and second irradiation means are provided in the same or different chambers.
[7] 化学的気相蒸着装置によって製造され、誘電率が 2. 4以下であって、ヤング率が 5[7] Manufactured by chemical vapor deposition equipment, dielectric constant is 2.4 or less, Young's modulus is 5
GPa以上である絶縁膜を備える、半導体デバイス。 A semiconductor device comprising an insulating film having a GPa or higher.
[8] 回転塗布成膜装置によって製造され、誘電率が 2. 3以下であって、ヤング率が 6G Pa以上である絶縁膜を備える、半導体デバイス。 [8] Manufactured by spin coating film forming equipment, dielectric constant is 2.3 or less, Young's modulus is 6G A semiconductor device comprising an insulating film that is at least Pa.
絶縁膜に対して第 1の波長の紫外光を照射する第 1照射工程と、  A first irradiation step of irradiating the insulating film with ultraviolet light having a first wavelength;
前記第 1照射工程の後に第 1の波長とは異なる第 2の波長の紫外光または可視光 を照射する第 2照射工程と、  A second irradiation step of irradiating ultraviolet light or visible light having a second wavelength different from the first wavelength after the first irradiation step;
を含む、照射方法。  Irradiation method including.
PCT/JP2006/308543 2005-10-14 2006-04-24 Irradiation unit, method of irradiation and semiconductor device WO2007043205A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007200961A (en) * 2006-01-24 2007-08-09 Sharp Corp Semiconductor device and manufacturing method thereof
WO2015045712A1 (en) * 2013-09-30 2015-04-02 富士フイルム株式会社 Method for producing metal oxide film, metal oxide film, thin-film transistor, display device, image sensor, and x-ray sensor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06124890A (en) * 1992-08-27 1994-05-06 Semiconductor Energy Lab Co Ltd Fabricating method for film-like semiconductor device
JPH1167759A (en) * 1997-08-25 1999-03-09 Hitachi Ltd Manufacture of semiconductor substrate with high breakdown voltage
JP2003142480A (en) * 2002-08-09 2003-05-16 Semiconductor Energy Lab Co Ltd Method for manufacturing semiconductor device
JP2004095755A (en) * 2002-08-30 2004-03-25 Fujitsu Ltd Method for manufacturing semiconductor device
JP2004140341A (en) * 2002-09-26 2004-05-13 Hitachi Chem Co Ltd Insulating film
JP2004312004A (en) * 2003-04-01 2004-11-04 Air Products & Chemicals Inc Low dielectric constant material and manufacturing method therefor
JP2006004996A (en) * 2004-06-15 2006-01-05 Semiconductor Process Laboratory Co Ltd Interlayer insulating film, diffusion preventing film and source material thereof, film forming method and plasma cvd device for forming film

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3957154B2 (en) * 2002-03-19 2007-08-15 富士通株式会社 Low dielectric constant film forming composition, low dielectric constant film, method for producing the same, and semiconductor device
JP4342974B2 (en) * 2003-02-12 2009-10-14 東京エレクトロン株式会社 Curing apparatus and method, and coating film forming apparatus
US7030468B2 (en) * 2004-01-16 2006-04-18 International Business Machines Corporation Low k and ultra low k SiCOH dielectric films and methods to form the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06124890A (en) * 1992-08-27 1994-05-06 Semiconductor Energy Lab Co Ltd Fabricating method for film-like semiconductor device
JPH1167759A (en) * 1997-08-25 1999-03-09 Hitachi Ltd Manufacture of semiconductor substrate with high breakdown voltage
JP2003142480A (en) * 2002-08-09 2003-05-16 Semiconductor Energy Lab Co Ltd Method for manufacturing semiconductor device
JP2004095755A (en) * 2002-08-30 2004-03-25 Fujitsu Ltd Method for manufacturing semiconductor device
JP2004140341A (en) * 2002-09-26 2004-05-13 Hitachi Chem Co Ltd Insulating film
JP2004312004A (en) * 2003-04-01 2004-11-04 Air Products & Chemicals Inc Low dielectric constant material and manufacturing method therefor
JP2006004996A (en) * 2004-06-15 2006-01-05 Semiconductor Process Laboratory Co Ltd Interlayer insulating film, diffusion preventing film and source material thereof, film forming method and plasma cvd device for forming film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007200961A (en) * 2006-01-24 2007-08-09 Sharp Corp Semiconductor device and manufacturing method thereof
WO2015045712A1 (en) * 2013-09-30 2015-04-02 富士フイルム株式会社 Method for producing metal oxide film, metal oxide film, thin-film transistor, display device, image sensor, and x-ray sensor
JP2015070211A (en) * 2013-09-30 2015-04-13 富士フイルム株式会社 Method of producing metal oxide film, metal oxide film, thin film transistor, display, image sensor, and x-ray sensor

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