CN112397372B - Method for manufacturing semiconductor device, semiconductor device and processing device thereof - Google Patents

Method for manufacturing semiconductor device, semiconductor device and processing device thereof Download PDF

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CN112397372B
CN112397372B CN201910762354.2A CN201910762354A CN112397372B CN 112397372 B CN112397372 B CN 112397372B CN 201910762354 A CN201910762354 A CN 201910762354A CN 112397372 B CN112397372 B CN 112397372B
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semiconductor device
buffer layer
treatment
ultraviolet
ozone plasma
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CN112397372A (en
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刘一剑
平延磊
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

The invention provides a method for manufacturing a semiconductor device, which at least comprises the following steps: providing a semiconductor substrate; forming a transistor on the semiconductor substrate; forming a buffer layer thin film on the semiconductor substrate and the transistor; carrying out combined treatment of ultraviolet irradiation and ozone plasma on the buffer layer film; and forming a stress film layer on the buffer layer. By adopting the method, the H element in the SiOx buffer layer can be removed by using the method of oxidative plasma combined treatment, and meanwhile, for the H element which cannot be removed by the ultraviolet irradiation method, the oxidative plasma can oxidize the H element into OH < - > to be fixed in the buffer layer film, so that the channel defect caused by the release of the H element is avoided. A semiconductor device prepared by the above-described integrated method and a processing apparatus thereof are also provided.

Description

Method for manufacturing semiconductor device, semiconductor device and processing device thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device, the semiconductor device and a processing device.
Background
As the feature size of metal-oxide semiconductor field effect transistors (MOSFETs) becomes smaller, stressed channels in MOSFETs become an increasingly important technology. Thanks to many years of research, the fundamental theory behind the enhancement of carrier mobility due to the presence of stress is well understood. When a stress film is introduced into the process flow of a MOSFET, it is necessary to ensure the reliability of the MOSFET device. In the fabrication of MOSFET devices with stressed thin films, spike annealing or laser annealing is typically used to enhance the stress in the stressed thin film after the stressed thin film is deposited, change the thermal expansion coefficient of the stressed thin film and transfer the stress into the channel. While depositing SiN x Before stressing the film, siO is usually deposited x The film acts as a buffer layer. This is a low cost method of making SiN x And (3) a process flow of the stress film. However, in the above method, siO x The deposition process of the buffer layer inevitably introduces H element, so that the H element is diffused into a device channel in the subsequent process, the B element in the channel is influenced, and the B element is further introducedTo V t A change occurs, i.e., degradation of the PMOS device results. As shown in fig. 1, a schematic diagram of a MOSFET device in the prior art, a well region 102 is formed on a semiconductor substrate 101, wherein the semiconductor substrate 101 may be a silicon substrate. Forming a gate stack and a sidewall 105 on a semiconductor substrate 101, forming a buffer layer 103 on the semiconductor substrate 101, and finally forming a stress film layer 104 on the buffer layer 103, wherein the buffer layer 103 may be SiO x The stress film layer 104 may be SiN x A layer. The MOSFET may be a PMOS, and the buffer layer in the PMOS formed by this process may have H element, which deactivates B element in the channel.
Therefore, in order to solve the above technical problems, a process capable of preventing the H element in the buffer layer from adversely affecting the MOSFET device is needed.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor device, the semiconductor device and a processing device, aiming at solving the problem that SiO arranged below a stress film layer in the prior art x The release of H from the buffer layer causes a problem of channel defects of the semiconductor device.
According to a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, the method at least including the following steps:
providing a semiconductor substrate;
forming a transistor on the semiconductor substrate;
forming a buffer layer on the transistor and the semiconductor substrate;
carrying out combined treatment of ultraviolet irradiation and ozone plasma on the buffer layer; and
and forming a stress film layer on the buffer layer.
Optionally, the uv irradiation and ozone plasma combined treatment includes simultaneously performing uv irradiation and ozone plasma treatment on the buffer layer in the same treatment chamber.
Optionally, the ultraviolet irradiation and ozone plasma combined treatment includes sequentially performing ultraviolet irradiation and ozone plasma treatment on the buffer layer in different machine chambers.
Optionally, the oxidizing source of the ozone plasma comprises O 2 、O 3 And N 2 O, or a combination thereof.
Optionally, the ultraviolet irradiation and ozone plasma combined treatment includes a first step of performing ultraviolet irradiation treatment on the buffer layer in a first machine chamber, and then a second step of performing ozone plasma treatment in another machine chamber; or, the first step of ozone plasma treatment is firstly carried out on the buffer layer in one machine chamber, and then the second step of ultraviolet irradiation treatment is carried out in the other machine chamber.
Optionally, the first step and the second step are performed continuously, or other process steps are added between the first step and the second step.
Optionally, the second step is performed after a pause for a period of time after the first step, and no process treatment is performed on the semiconductor device between the first step and the second step.
Optionally, the time of the pause is between 10s and 1 h.
Optionally, the ultraviolet irradiation is performed by ultraviolet rays generated by ultraviolet lamps, and the number of the ultraviolet lamps includes 10 to 1000.
Optionally, the radiation direction of the ultraviolet rays forms an included angle of 5-90 degrees with the horizontal direction of the semiconductor device substrate.
Optionally, the ultraviolet irradiation is performed at a temperature ranging from room temperature to 600 ℃.
Optionally, the wavelength of the ultraviolet light used for the ultraviolet light irradiation is 500nm to 200nm, and the total power of the ultraviolet light irradiation is in the range of 10W to 10kW.
Optionally, the bias power of the power source used for generating the ozone plasma is in the range of 10W to 10kW.
Optionally, the ozone plasma comprises ozone plasma formed near the surface of the semiconductor device, or ozone plasma or plasma generated particles emitted by a remote plasma source.
Optionally, the distance between the remote plasma source and the upper surface of the semiconductor device is comprised between 10mm and 100 mm.
Optionally, in combination with the treatment process, a substrate bias is applied to the semiconductor device during treatment to generate the ozone plasma.
Optionally, the substrate bias voltage comprises a dc bias voltage, and the voltage of the dc bias voltage is 5V to 500V.
Optionally, the substrate bias voltage comprises a radio frequency bias voltage, and the frequency of the radio frequency bias voltage is 100Hz-40MHz.
The invention also provides a semiconductor device which is manufactured by adopting any one of the methods.
Optionally, the semiconductor device includes: the semiconductor device comprises a gate stack formed on a semiconductor substrate and a side wall surrounding the gate stack.
Optionally, the semiconductor device includes an NMOS transistor and a PMOS transistor, and a shallow trench isolation is further disposed between the NMOS transistor and the PMOS transistor.
The present invention also provides a processing apparatus of a semiconductor device, the processing apparatus including:
a chamber body;
a support base supporting the semiconductor device;
a first bias voltage generator;
a radio frequency coil disposed above the support pedestal, the radio frequency coil being electrically connected to the first bias generator; and
an ultraviolet lamp disposed above the chamber body.
The present invention also provides a processing apparatus for a semiconductor device, the processing apparatus being a remote plasma processing apparatus, the processing apparatus comprising:
a chamber body;
a support base supporting the semiconductor device; and
a remote plasma source disposed above the support pedestal, the remote plasma source comprising: a first bias voltage generator and a radio frequency coil;
the processing apparatus further includes an ultraviolet lamp positioned between the remote plasma source and the support base.
Optionally, the processing apparatus further comprises a second bias generator connected to the support base, the second bias generator being located below the support base.
Optionally, the second bias generator comprises a dc bias source of 5V-500V or an rf bias source.
Optionally, the rf bias source generates rf signals having a frequency between 100Hz and 40MHz and a power between 10W and 10kW.
Optionally, the number of the ultraviolet lamps comprises 10-1000.
Optionally, the radiation direction of the ultraviolet rays generated by the ultraviolet lamp forms an included angle of 5-90 degrees with the horizontal direction of the semiconductor device substrate.
Optionally, the wavelength of the ultraviolet light generated by the ultraviolet lamp is 500nm to 200nm, and the power of the ultraviolet irradiation is 10W to 10kW.
Optionally, the distance from the remote plasma source to the upper surface of the semiconductor device is between 10mm and 100 mm.
In the above manufacturing method, siO is formed x Buffer layer and SiN x Ultraviolet irradiation and ozone plasma treatment are added between the stress film layers, so that the buffer layer is subjected to combined treatment of the ultraviolet irradiation and the ozone plasma. By the above method, siO can be removed by ultraviolet irradiation x H element in the buffer layer, and meanwhile, for H element which can not be removed by the ultraviolet irradiation method, the H element is oxidized into OH-to be fixed in the buffer layer film by using an ozone plasma oxidation mode, so that the channel defect caused by the release of the H element is avoided.
Specifically, in the above-mentioned production method, the odorOxygen plasma treatment has at least two primary functions, one being to clean SiO x Buffer layer and SiN x Stress the interface between the thin film layers to enhance SiO x Buffer layer and SiN x The bonding force between the stress film layers can react with-H in ethoxy left by TEOS to form-OH with bonding energy larger than that of C-H bond, so that H element is fixed in the buffer layer film.
In addition, higher energy plasma species, such as plasma ions and plasma neutrons, can increase the density of the buffer layer film when bombarding the buffer layer, thereby forming a barrier layer to prevent diffusion of H elements.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are schematic and are not to be understood as limiting the invention in any way, and in which:
fig. 1 shows a schematic diagram of a MOSFET device in the prior art.
Fig. 2 shows a schematic diagram of a MOSFET device having a stressed thin-film layer with a porous structure.
Fig. 3-5 are schematic diagrams illustrating a method of fabricating a semiconductor device according to the present invention.
Fig. 6 is a flow chart corresponding to the above manufacturing method.
Fig. 7 is a schematic view showing a first embodiment of the apparatus for processing a semiconductor device in the present invention.
Fig. 8 is a schematic view showing a second embodiment of the processing apparatus for a semiconductor device in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background section, the conventional process of forming a MOSFET introduces H element in the buffer layer to cause deterioration of the MOSFET device.
To solve the above problems, several common solutions are provided. Fig. 2 shows a schematic diagram of a MOSFET device having a stress film layer with a porous structure, and a well region 202 is formed on a semiconductor substrate 201, wherein the semiconductor substrate 201 may be a silicon substrate. Forming a gate stack and a sidewall 205 on a semiconductor substrate 201, forming a buffer layer 203 on the semiconductor substrate 201, and finally forming a stress film layer 204 on the buffer layer 203, wherein the buffer layer 203 may be SiO x The stress film layer 204 may be SiN x And (3) a layer. Unlike fig. 1, the stressed thin film layer 204 is a porous structure, which can allow H element in the buffer layer 203 to be released in an annealing process, so as to avoid H element in the finally formed MOSFET device. However, this process still has difficulty ensuring that all H elements are released.
And another method for releasing the H element in the buffer layer is also provided, the buffer layer is subjected to ultraviolet curing while annealing, and the energy of ultraviolet rays can play a role in breaking hydrogen bonds, hydrogen-oxygen bonds and hydrogen-silicon bonds in the buffer layer, so that the H element in the buffer layer is released. However, the above method also causes a small amount of H element in the buffer layer to be not removed by the uv irradiation, and the H element not removed also affects the B element in the channel and thus causes the MOSFET device to be degraded.
In order to solve the problems of the above-mentioned processes, a method for treating a semiconductor device by using a combination of ultraviolet irradiation and ozone plasma is provided, and will be described in detail with reference to the following examples.
Example one
The present invention provides a method for releasing H element in a buffer layer by using a combination treatment of ultraviolet irradiation and ozone plasma for a semiconductor device, and the present invention is illustrated in the following specific examples.
The present invention provides a method for fabricating a semiconductor device, fig. 3-5 are schematic diagrams illustrating a method for fabricating a semiconductor device according to the present invention, and fig. 6 is a corresponding flowchart of the above-mentioned fabrication method. Referring to fig. 3 to 6, the method for manufacturing a semiconductor device according to the present invention includes the following steps:
step S601, depositing a buffer layer.
As shown in fig. 3, in this step, a well 302 is first formed on the semiconductor substrate 301, and then a gate stack 303 is formed on the semiconductor substrate 301, and sidewalls may also be formed outside the gate stack 303. Finally, a buffer layer 305 is formed on the semiconductor substrate 301. In this embodiment, the semiconductor device is a PMOS, and the semiconductor substrate 301 includes a silicon wafer.
In some specific embodiments, the semiconductor substrate 301 may further include an NMOS, that is, the semiconductor substrate 301 may be divided into a PMOS region and an NMOS region, and the PMOS region and the NMOS region are isolated from each other by the shallow trench isolation 304.
Step S602, carrying out ultraviolet-ozone combined treatment on the buffer layer.
As shown in fig. 4, in this step, an ozone plasma 308 is formed above the buffer layer 305 to perform ozone treatment on the buffer layer 305. An oxidizing source, which may be O, may be introduced into the processing chamber to form the ozone plasma 308 2 、O 3 、N 2 O, and the like. In the above process, no substrate bias is used.
In another embodiment, a bias generator 307 is further disposed below the supporting base 306 of the semiconductor substrate 301. The bias generator 307 may comprise a 5V-500V dc bias source or an RF bias source, which is typically capable of generating RF signals having a frequency of from about 100Hz to about 40MHz and a power of between about 10W-10kW. In this step, an ozone plasma 308 is formed above the buffer layer 305 under the condition that a substrate bias is generated by the bias generator 307. The ozone plasma 308 may be an ozone plasma formed near the surface of the semiconductor substrate 301 or a plasma emitted from a remote plasma source. Wherein the distance from the remote plasma source to the upper surface of the semiconductor substrate 301 may be between 10mm and 100 mm.
In this step, the buffer layer 305 is also subjected to ultraviolet irradiation 309 to subject the buffer layer to a combined ultraviolet-ozone treatment. The ultraviolet irradiation can be realized by arranging ultraviolet lamps above the chamber, the number of the ultraviolet lamps can be 10-1000, the included angle between the ultraviolet rays emitted by the ultraviolet lamps and the horizontal plane of the semiconductor substrate 301 can be 5-90 degrees, the process temperature can be between normal temperature and 600 ℃, the wavelength of the ultraviolet rays can be between 500nm and 200nm, and the power can be 10W-10kW.
In this step, the uv-ozone combined treatment may be simultaneous uv irradiation and ozone plasma treatment in the same treatment chamber, or may be sequential uv irradiation and ozone plasma treatment in different machine chambers. In one embodiment, the first step of the uv irradiation treatment may be performed in one chamber, and then the second step of the ozone plasma treatment may be performed in another chamber; or, the first step of ozone plasma treatment is performed in one machine chamber, and then the second step of ultraviolet irradiation treatment is performed in another machine chamber. In the process of sequentially carrying out the ultraviolet irradiation and the ozone plasma treatment, the two treatment processes can be continuously carried out, other process steps can be added between the two treatment processes, or the first step is followed by a pause for a period of time, namely, no process treatment is carried out on the semiconductor device, wherein the pause time can be 10s to 1 h.
And step S603, depositing a stress film layer.
As shown in fig. 5, in this step, a stress thin film layer 310 is formed on the buffer layer 305. The stress film layer 310 formed as described above is used to induce a corresponding stress in the channel region in the semiconductor substrate 301.
In a specific embodiment, the Si source in the process of forming the stress film layer 310 comprises TEOS or SiH 4 The growth atmosphere for forming the stress film layer 310 comprises N 2 O、NH 4 、N 2 And H 2 One or more of (a).
The method for forming the stress film layer 310 includes PECVD or thermal CVD.
The transistors and the stressed thin film layer 310 may be formed in situ in the same chamber, or the transistors and the stressed thin film layer 310 may be formed separately in different chambers of the same machine, or the transistors and the stressed thin film layer 310 may be formed separately in different chambers of different machines.
The thickness of the stress film layer is
Figure BDA0002170760460000081
Forming the stress film layer at a temperature of 20-600 ℃.
And step S604, carrying out a post-treatment process.
In order to eliminate the above-mentioned adverse effect of the deposited stress film layer 310 on the hole mobility of the PMOS region, in this step, a PR layer is formed on the NMOS region, thereby shielding the stress film layer 310 located on the NMOS region. Then, the PR layer is used as a mask to etch the exposed stress film layer 310 on the PMOS region by using an etching process such as photolithography, so as to remove the stress film layer 310 on the PMOS region.
In this step, the stress thin film layer 310 above the PMOS device is selectively etched and removed, that is, the stress thin film layer 310 above the PMOS device may not be removed, and whether the removal depends on the influence of the stress thin film layer 310 with tensile stress on the performance of the PMOS device.
Step S605, an annealing process is performed.
In this step, the PR layer on the NMOS region is removed first, and then a spike annealing process is performed, so that the stress caused by the deposited stress thin film layer 310 is memorized in the NMOS region, thereby increasing the electron mobility of the channel region in the NMOS region and improving the electrical performance of the NMOS device. Since the stress film layer 310 on the PMOS region is removed during the spike annealing process, the electrical properties of the PMOS region are not changed.
In the above manufacturing methodIn the method, siO is formed x Buffer layer and SiN x Ozone plasma treatment is added between the stress film layers, so that the ultraviolet irradiation-ozone plasma combined manufacturing method is formed. By the above method, siO can be removed by ultraviolet irradiation x And H element in the buffer layer is oxidized into OH-fixed in the buffer layer film in an ozone plasma oxidation mode for the H element which cannot be removed by the ultraviolet irradiation method, so that the channel defect caused by releasing the H element is avoided.
Specifically, in the above-described fabrication method, the ozone plasma treatment has at least two main effects, namely, the ability to clean SiO x Buffer layer and SiN x Stress the interface between the thin film layers to enhance SiO x Buffer layer and SiN x The bonding force between the stress film layers can react with-H in ethoxy left by TEOS to form-OH with bonding energy larger than that of C-H bond, so that H element is fixed in the buffer layer film.
In addition, the higher energy plasma species, such as plasma ions and plasma neutrons, can cause the density of the buffer layer film to increase when bombarding the buffer layer, thereby forming a barrier layer to prevent the diffusion of H element.
As shown in fig. 5, the semiconductor device manufactured by the above manufacturing method includes: a well region 302 formed in a semiconductor substrate 301, a gate stack 303 formed on the semiconductor substrate 301 and a sidewall surrounding the gate stack 303, a buffer layer 305 formed on the semiconductor substrate 301, and a stress thin film layer 310 formed on the buffer layer 305; wherein the buffer layer 305 is subjected to a combined ultraviolet irradiation-ozone plasma treatment. In a particular embodiment, the semiconductor device comprises a PMOS. In another specific embodiment, the semiconductor substrate 301 may further include an NMOS, that is, the semiconductor substrate 301 may be divided into a PMOS region and an NMOS region, and the PMOS region and the NMOS region are isolated by the shallow trench isolation 304.
Example two
The present invention also provides a processing apparatus for implementing the manufacturing method according to the first embodiment, and as shown in fig. 7, the processing apparatus is a schematic diagram of a first embodiment of the processing apparatus for a semiconductor device according to the present invention, and includes:
a chamber body (not shown);
a support base 702 supporting the semiconductor device 701;
a first bias voltage generator 703; and
a radio frequency coil 704, the radio frequency coil 704 being located above the support base 702, the radio frequency coil 704 being electrically connected to the first bias voltage generator 703.
Wherein the rf coil 704 may be disposed around a peripheral wall of the chamber body, and the rf coil 704 may have one or more turns. In one particular embodiment, the first bias generator 703 applies RF power to the RF coil 704 to excite the process gas in the chamber body into a plasma 705, such as an ozone plasma. Wherein the semiconductor device 701 comprises a PMOS formed on a silicon wafer.
In a specific embodiment, the processing device further comprises a second bias generator 706 coupled to the support base 702, the second bias generator 706 being positioned below the support base 702. The second bias generator 706 may include a 5V-500V DC bias source, or an RF bias source, which is typically capable of generating RF signals having a frequency of from about 100Hz to about 40MHz and a power of between about 10W-10kW. In this step, an ozone plasma 705 is formed over the semiconductor device 701 with the second bias generator 706 generating a substrate bias. The ozone plasma 705 may be an ozone plasma formed near the surface of the semiconductor substrate 701.
The processing device also comprises ultraviolet lamps arranged above the chamber main body, the number of the ultraviolet lamps can be 10-1000, the included angle between the ultraviolet rays emitted by the ultraviolet lamps and the horizontal plane of the semiconductor substrate 701 is 5-90 degrees, the process temperature can be between normal temperature and 600 ℃, the wavelength of the ultraviolet rays can be between 500nm and 200nm, and the power can be 10W-10kW.
EXAMPLE III
The present invention also provides a processing apparatus for implementing the manufacturing method according to the first embodiment, as shown in fig. 8, which is a schematic view of a second embodiment of the processing apparatus for a semiconductor device according to the present invention, the processing apparatus is a remote plasma processing apparatus, and the processing apparatus includes:
a chamber body (not shown);
a support base 802 supporting the semiconductor device 801; and
a remote plasma source;
wherein the remote plasma source comprises: a first bias generator 803 and a radio frequency coil 804, the radio frequency coil 804 being located above the support base 802, the radio frequency coil 804 being electrically connected to the first bias generator 803.
The RF coil 804 may be disposed around the outer periphery of the chamber body, and the RF coil 804 may have one or more turns. In one particular embodiment, the first bias generator 803 applies RF power to the RF coil 804, thereby exciting the process gas within the chamber body into a plasma 805, such as an ozone plasma. The ozone plasma 805 is a plasma emitted by a remote plasma source. Wherein the distance from the remote plasma source to the upper surface of the semiconductor substrate 801 may be between 10mm and 100 mm.
In a specific embodiment, the processing device further comprises a second bias generator 806 coupled to the support pedestal 802, the second bias generator 806 being positioned below the support pedestal 802. The second bias generator 806 may include a 5V-500V dc bias source and may also include a radio frequency bias source that is generally capable of generating RF signals having a frequency of from about 100Hz to about 40MHz and a power of between about 10W-10kW. In this step, an ozone plasma 805 is formed over the semiconductor device 801 with the second bias generator 806 generating a substrate bias.
The processing apparatus further includes an ultraviolet lamp 807, the ultraviolet lamp 807 being located between the remote plasma source and the support pedestal 802. The number of the ultraviolet lamps 807 can be 10-1000, the included angle between ultraviolet rays emitted by the ultraviolet lamps and the horizontal plane of the semiconductor substrate 801 is 5-90 degrees, the process temperature can be between normal temperature and 600 ℃, the wavelength of the ultraviolet rays can be between 500nm and 200nm, and the power can be 10W-10kW.
The above-described embodiments are merely illustrative of the principles of the present invention and its efficacy, rather than limiting the invention, and it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the invention, such modifications and variations being within the scope of the appended claims.

Claims (29)

1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate;
forming a transistor on the semiconductor substrate;
forming a buffer layer on the transistor and the semiconductor substrate;
carrying out combined treatment of ultraviolet irradiation and ozone plasma on the buffer layer; wherein, the ultraviolet irradiation treatment is used for removing hydrogen elements in the buffer layer, and the ozone plasma treatment is used for fixing the hydrogen elements which cannot be removed by the ultraviolet irradiation in the buffer layer film in an OH-oxidizing mode; and
and forming a stress film layer on the buffer layer.
2. The method of claim 1, wherein the combined uv irradiation and ozone plasma treatment comprises simultaneously subjecting the buffer layer to uv irradiation and ozone plasma treatment in the same processing chamber.
3. The method of claim 1, wherein the combined UV irradiation and ozone plasma treatment comprises sequentially performing UV irradiation and ozone plasma treatment on the buffer layer in different tool chambers.
4. The method according to any one of claims 1 to 3, which isCharacterized in that the oxidizing source of the ozone plasma comprises O 2 、O 3 And N 2 O, or a combination thereof.
5. The method according to any one of claims 1 to 3, wherein the combined UV irradiation and ozone plasma treatment comprises a first step of performing a UV irradiation treatment on the buffer layer in one chamber of the processing station, and then a second step of performing an ozone plasma treatment in another chamber of the processing station; or, the first step of ozone plasma treatment is firstly carried out on the buffer layer in one machine chamber, and then the second step of ultraviolet irradiation treatment is carried out in the other machine chamber.
6. The method according to claim 5, characterized in that the first step and the second step are carried out continuously or that further process steps are added between the first step and the second step.
7. The method of claim 5, wherein the second step is performed after a time pause after the first step, without any process treatment of the semiconductor device between the first step and the second step.
8. The method of claim 7, wherein the pause is between 10s and 1 h.
9. The method according to any one of claims 1 to 3, wherein the ultraviolet irradiation is performed by ultraviolet lamps, the number of which comprises 10 to 1000.
10. The method according to claim 9, wherein the radiation direction of the ultraviolet rays makes an angle of 5 ° to 90 ° with a horizontal direction of the semiconductor device substrate.
11. A method according to any of claims 1-3, characterized in that the uv irradiation is performed at a temperature in the range between ambient temperature and 600 ℃.
12. A method according to any of claims 1-3, characterized in that the ultraviolet radiation is applied at a wavelength of between 500nm and 200nm and has a total power in the range of 10W to 10kW.
13. A method according to any of claims 1-3, wherein the ozone plasma is generated with a power source bias power in the range of 10W to 10kW.
14. A method according to any of claims 1-3, wherein the ozone plasma comprises an ozone plasma formed near the surface of the semiconductor device, or is an ozone plasma or plasma-generated particles emitted by a remote plasma source.
15. The method of claim 14, wherein the remote plasma source is between 10mm and 100mm from the upper surface of the semiconductor device.
16. A method as claimed in any one of claims 1 to 3, characterized in that, in carrying out the combined treatment process, a substrate bias is applied to the semiconductor device during treatment in order to generate the ozone plasma.
17. The method of claim 16, wherein the substrate bias voltage comprises a dc bias voltage having a voltage of 5V-500V.
18. The method of claim 16, wherein the substrate bias voltage comprises a radio frequency bias voltage having a frequency of 100Hz-40MHz.
19. A semiconductor device, characterized in that it is manufactured by means of a method according to any one of claims 1-18.
20. The semiconductor device according to claim 19, wherein the semiconductor device comprises: the semiconductor device comprises a gate stack formed on a semiconductor substrate and a side wall surrounding the gate stack.
21. The semiconductor device of claim 19, wherein the semiconductor device comprises an NMOS transistor and a PMOS transistor, and wherein a shallow trench isolation is further disposed between the NMOS transistor and the PMOS transistor.
22. A semiconductor device processing apparatus, wherein said processing apparatus is a remote plasma processing apparatus, said processing apparatus comprising:
a chamber body;
a support base supporting the semiconductor device; and
a remote plasma source disposed above the support pedestal, the remote plasma source comprising: a first bias generator and a radio frequency coil; the first bias generator applies rf power to the rf coil for exciting an ozone plasma within the chamber body;
the processing apparatus further comprises an ultraviolet lamp positioned between the remote plasma source and the support base;
wherein the buffer layer is irradiated with ultraviolet rays emitted from the ultraviolet lamp to release hydrogen in the buffer layer,
the ozone plasma treatment buffer layer is used for fixing hydrogen elements which cannot be removed by ultraviolet irradiation in the buffer layer film in a manner of oxidizing the hydrogen elements into OH-.
23. The processing device of claim 22, further comprising a second bias generator coupled to the support base, the second bias generator being positioned below the support base.
24. The processing apparatus as claimed in claim 23, wherein the second bias generator comprises a dc bias source of 5V-500V or an rf bias source.
25. The processing apparatus according to claim 24, wherein the radio frequency bias source generates a radio frequency signal having a frequency between 100Hz and 40MHz and a power between 10W and 10kW.
26. The treatment apparatus of claim 22, wherein the number of ultraviolet lamps comprises 10-1000.
27. The processing apparatus of claim 22, wherein the ultraviolet lamp emits ultraviolet light at an angle of 5 ° to 90 ° with respect to a horizontal direction of the semiconductor device substrate.
28. The treatment apparatus according to claim 22, wherein the ultraviolet lamp generates ultraviolet radiation at a wavelength of between 500nm and 200nm, and the power of the ultraviolet radiation is between 10W and 10kW.
29. The processing apparatus of claim 22 wherein the distance from the remote plasma source to the upper surface of the semiconductor device is between 10mm and 100 mm.
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