WO2007041100A2 - Dispositifs electroniques en boitier et procede de fabrication correspondant - Google Patents

Dispositifs electroniques en boitier et procede de fabrication correspondant Download PDF

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Publication number
WO2007041100A2
WO2007041100A2 PCT/US2006/037480 US2006037480W WO2007041100A2 WO 2007041100 A2 WO2007041100 A2 WO 2007041100A2 US 2006037480 W US2006037480 W US 2006037480W WO 2007041100 A2 WO2007041100 A2 WO 2007041100A2
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WIPO (PCT)
Prior art keywords
electronic
electronic device
module
spacer
electronic devices
Prior art date
Application number
PCT/US2006/037480
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English (en)
Other versions
WO2007041100A3 (fr
Inventor
Robert W. Warren
Steve X. Liang
Tony Lobianco
Gene Gan
Original Assignee
Skyworks Solutions, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Skyworks Solutions, Inc. filed Critical Skyworks Solutions, Inc.
Priority to EP06825130A priority Critical patent/EP1929519A4/fr
Publication of WO2007041100A2 publication Critical patent/WO2007041100A2/fr
Publication of WO2007041100A3 publication Critical patent/WO2007041100A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
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    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
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    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards

Definitions

  • Today's semiconductor packages include a number of different electronic devices. These electronic devices can include, for example, integrated circuits (ICs), microelectronic machines (MEMs), and/or the like.
  • ICs integrated circuits
  • MEMs microelectronic machines
  • the integration of different electronic devices into a device module typically requires a significant amount of horizontal space, and relatively high assembly and processing complexity and cost.
  • Current techniques for integrating different electronic devices into a device module largely focus on minimizing two-dimensional (X, Y) area of the discrete electronic devices.
  • the discrete devices are assembled separately into the modules, where each such module includes a separate lid. Additionally, the assembled discrete devices occupy at least as much area in the two-dimensional (X, Y) portion of the module as the combined two-dimension area of the individual devices.
  • a second electronic device is arranged above a first electronic device.
  • Spacers are arranged between a first and second electronic device to form a uniform and sealed air gap between the electronic devices.
  • the height of the spacers, and the resulting height of the air gap, is selected based upon the type of electronic device.
  • the height of the spacers is selected to reduce radio frequency interference between the first and second electronic devices. In the case of microelectronic machines, the height is selected to allow sufficient clearance for operation of the machines.
  • Figure 1 illustrates an exemplary electronic module in accordance with the present invention
  • Figures 2a-2h illustrate an exemplary process for forming the electronic module of the present invention.
  • FIG. 1 illustrates an exemplary electronic module 100 in accordance with the present invention.
  • the electronic module 100 includes a substrate 102 and two or more electronic devices, each of which comprise a wafer, active device, contact pads, and gold or copper balls.
  • the substrate 102 includes one or more thermal vias 106a-106d, one or more input/output (I/O) lines 104a and 104b, and integrated transmission lines and inductors.
  • Substrate 102 can be a lead free (LF) laminate or ceramic substrate.
  • a first electronic device includes a wafer 122, active device 124, gold or copper balls 126a and 126b, and contact pads 128a and 128b.
  • the contact pads 128a and 128b are respectively coupled to the I/O lines 104a and 104b by bonding wires 160a and 160b.
  • a second electronic device is arranged on spacers 123a and 123b above the first electronic device, thereby forming a uniform and sealed air gap between the first and second electronic devices.
  • an adhesive layer 131 couples the spaces 123a and 123b to the second electronic device.
  • the second electronic device includes a wafer 132, active device 134, gold or copper balls 136a and 136b, and contact pads 138a and 138b.
  • the contact pads 138a and 138b are respectively coupled to the I/O lines 104a and 104b by bonding wires 162a and 162b.
  • Module 100 also includes a third electronic device arranged above the second electronic device on spacers 133a and 133b. Specifically, spacers 133a and 133b are provided on wafer 132 of the second electronic device and the third electronic device is coupled to the spacers 133a and 133b by an adhesive layer 141.
  • the third electronic device includes an active device 144 and contact pads 148a and 148b on wafer 142. Gold or copper balls 146a and 146b are respectively coupled to bonding wires 164a and 164b, which in turn are coupled to I/O lines 104a and 104b, respectively.
  • a lid 150 is arranged above the uppermost electronic device, which in the illustrated embodiment is the third electronic device.
  • Lid 150 can be composed of silicon, glass, ceramic or the like material.
  • Lid 150 includes an adhesive layer 151 on the side facing the third electronic device.
  • Spacers 143a and 143b are arranged on wafer 142 of the third electronic device and are coupled to the adhesive layer 151.
  • Figure 1 illustrates an electronic module with three electronic devices, the electronic module can have more or less than three electronic devices.
  • Active devices 124, 134 and 144 can be integrated circuits or microelectronic machines (MEMS).
  • MEMS microelectronic machines
  • active devices 134 and 144 can be a transmitter and receiver filter
  • active device 124 can be a switch.
  • I/O lines I/O lines
  • the spacers can be composed of polymer and have dimensions between 30 and 200 ⁇ m wide, and between 10 and 200 ⁇ m high.
  • the active devices 124, 134 and 144 are radio frequency devices, the height of the spacers and the resulting uniform and sealed air gap are selected to minimize interference between the active devices.
  • the height of the spacers and the resulting uniform and sealed air gap are selected to provide sufficient clearance for the operation of the microelectronic machines.
  • the process involves a wafer 200 with one or more active devices 134 and 144, and corresponding contact pads.
  • two or more spacers 133a and 133b are arranged on the wafer 200 by spin or spray coating, and photo development or screen printing ( Figure 2a). Since wafer 200 includes a second active device 144, a second set of spacers 148a and 148b (not illustrated) are formed on the wafer. A set of spaces can be formed for each active device upon which another active device will be stacked in the electronic module.
  • the device wafer is thinned from a full wafer thickness to a thickness between 50 and 200 ⁇ m using any conventional semiconductor back lapping process to form wafer 210 (Figure 2b).
  • an adhesive 220 such as a B-stage adhesive film, is formed on the side of the wafer 210 opposite to the active devices 134 and 144, using, for example, a lamination or coating process.
  • the individual electronic devices are formed by a die singulation process ( Figure 2d).
  • the first electronic device As illustrated in Figure 2e, the first electronic device, with the first active device 124, is attached to substrate 102 using conventional die placement equipment. Spacers 123a and 123b are formed by spin or spray coating, and photo development or screen printing. Bonding wires 160a and 160b are respectively placed on gold or copper balls 126a and 126b, and on I/O lines 104a and 104b. The gold or copper balls 126a and 126b are heated, thereby mechanically and electrically coupling contact pads 128a and 128b to I/O lines 104a and 104b, respectively.
  • the second electronic device is arranged above the first electronic device in such a way that the adhesive on the bottom of the second electronic device mates with the spacers 123a and
  • the second electronic device is wire bonded to the I/O lines 104a and 104b in a similar manner to that described above in connection with the first electronic device.
  • the third electronic device is arranged above the second electronic device in a similar manner to that described above in connection with the second electronic device, and the third electronic device is wire bonded to the I/O lines 104a and 104b.
  • Lid 150 is arranged above the uppermost electronic device, which in the present description is the third electronic device, with adhesive layer 151 adjoining spacers 143a and 143b ( Figure 2h).
  • the entire module is heated to a predetermined temperature (e.g., 150° C) in a controlled environment for a predetermined amount of time (e.g., 1 hour) to cure the adhesive.
  • a predetermined temperature e.g. 150° C
  • a predetermined amount of time e.g. 1 hour

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Micromachines (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Casings For Electric Apparatus (AREA)

Abstract

La présente invention concerne un module électronique et un procédé de formation d'un module électronique. Des espaces pour l'air uniformes et hermétiques sont formés dans la direction verticale entre au moins deux modules électroniques. Les espaces pour l'air uniformes et hermétiques sont formés par l'agencement d'espaceurs entre les dispositifs électroniques, la hauteur des espaceurs étant sélectionnée en fonction des caractéristiques de fonctionnement du type particulier des dispositifs électroniques.
PCT/US2006/037480 2005-09-29 2006-09-26 Dispositifs electroniques en boitier et procede de fabrication correspondant WO2007041100A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06825130A EP1929519A4 (fr) 2005-09-29 2006-09-26 Dispositifs electroniques en boitier et procede de fabrication correspondant

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/242,431 US20070070608A1 (en) 2005-09-29 2005-09-29 Packaged electronic devices and process of manufacturing same
US11/242,431 2005-09-29

Publications (2)

Publication Number Publication Date
WO2007041100A2 true WO2007041100A2 (fr) 2007-04-12
WO2007041100A3 WO2007041100A3 (fr) 2007-10-04

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PCT/US2006/037480 WO2007041100A2 (fr) 2005-09-29 2006-09-26 Dispositifs electroniques en boitier et procede de fabrication correspondant

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US (1) US20070070608A1 (fr)
EP (1) EP1929519A4 (fr)
KR (1) KR20080064134A (fr)
TW (1) TW200731501A (fr)
WO (1) WO2007041100A2 (fr)

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Publication number Priority date Publication date Assignee Title
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KR20080064134A (ko) 2008-07-08
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TW200731501A (en) 2007-08-16
EP1929519A2 (fr) 2008-06-11
US20070070608A1 (en) 2007-03-29

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