Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/22—Secondary treatment of printed circuits
  • H05K3/28—Applying non-metallic protective coatings
  • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3157—Partial encapsulation or coating
  • H01L23/3192—Multilayer coating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
  • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
  • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
  • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
  • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
  • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
  • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
  • H01L2224/241—Disposition
  • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
  • H01L2224/82009—Pre-treatment of the connector or the bonding area
  • H01L2224/8203—Reshaping, e.g. forming vias
  • H01L2224/82035—Reshaping, e.g. forming vias by heating means
  • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01005—Boron [B]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01006—Carbon [C]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01013—Aluminum [Al]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01023—Vanadium [V]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01029—Copper [Cu]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01033—Arsenic [As]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01082—Lead [Pb]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/013—Alloys
  • H01L2924/014—Solder alloys
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/181—Encapsulation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/35—Mechanical effects
  • H01L2924/351—Thermal stress
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/01—Dielectrics
  • H05K2201/0137—Materials
  • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
  • H05K2203/1305—Moulding and encapsulation
  • H05K2203/1311—Foil encapsulation, e.g. of mounted components
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
  • H05K2203/1305—Moulding and encapsulation
  • H05K2203/1322—Encapsulation comprising more than one layer
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
  • Y10T156/10—Methods of surface bonding and/or assembly therefor

Definitions

• the invention relates to a hermetically sealed package and a method for producing a hermetically sealed package according to claims 1 and 27.
• Encapsulated components can be damaged by mechanical action and environmental influences and put out of action.
• the environmental influences include harmful gases such as oxygen, liquids such as water, organic and inorganic acids or electromagnetic fields.
• the pollutants especially under the influence of elevated temperatures, exert their detrimental effect by destroying packaging materials such as molding compounds, epoxies or polyimides, or the components themselves.
• the elevated temperature promotes the diffusion process of the pollutants through the packaging material or along the boundary surfaces of the pollutants Packagematerials.
• electromagnetic fields can freely penetrate to the component and damage it.
• Typical packages include plastic seals, which, however, do not hermetically protect the component from environmental influences.
• Hermetically sealed packages for protection against environmental influences include in particular metal or ceramic housing.
• Conventional hermetically sealed housings consist of a housing bottom and a lid or cap. By welding or soldering the lid to the case bottom, the case is hermetically sealed.
• the housing bottom and the cover can claim large parts of the surface of a printed circuit board or a module on which the component is mounted.
• the invention is therefore based on the object to provide an improved hermetic sealing of a device.
• This object is solved by the subject matter of the independent patent claims. Preferred embodiments are indicated by the independent claims.
• An embodiment of the present invention provides a method of manufacturing a package.
• the method includes providing a substrate, wherein one or more components are disposed on an upper surface of the substrate.
• the method further includes forming a hermetically sealing protective layer on the one or more devices and on the top surface of the substrate, the hermetically sealed protective layer having the following properties: gas impermeable, liquid impermeable, electromagnetic wave impermeable, temperature resistant, electrically insulating, and process resistant ,
• forming the hermetically sealing protective layer comprises forming a plurality of stacked sublayers. This has the advantage that partial layers with different functionality can be formed.
• the formation of a plurality of sublayers arranged one above the other comprises the lamination of a film of electrically insulating plastic material, wherein preferably a film of a plastic material on polyimide, polyamide, polyethylene, polyphenol, polyetheretherketone and / or epoxide-based is used.
• the formation of a plurality of sublayers arranged one above the other comprises the formation of a metal partial layer comprising a metal, the sublayer comprising a metal protecting the one or more components from electromagnetic radiation.
• the metal is going to be selected from a group consisting of aluminum, copper, titanium, and nickel.
• the formation of a plurality of sublayers arranged one above another comprises the formation of an inorganic sublayers comprising an inorganic material.
• the inorganic material preferably includes silica.
• forming a plurality of stacked sub-layers includes forming an organic sub-layer comprising an organic material.
• the organic material contains parylene.
• forming the hermetically sealing protective layer comprises forming a hermetically sealing protective layer comprising a filler material.
• the filler preferably contains silica or carbon.
• providing a substrate comprises providing a substrate consisting of an insulating layer, a first metal layer deposited on a lower surface of the insulating layer, and a second structured metal layer deposited on a surface of the insulating layer facing away from the lower surface.
• Forming the hermetically sealing protective layer may include a physical deposition method such as a sputtering process or a sputtering process.
• the forming of the hermetically sealing protective layer may also include a spraying process or a casting process.
• Forming the hermetically sealing protective layer may include a chemical deposition method such as a CVD method or an LPCVD method.
• the method of manufacturing a package further comprises exposing one or more contact surfaces on the surface of the substrate and surfaces of the one or more devices by opening respective windows in the hermetically sealed protective layer, and contacting each exposed contact surface with a surface Contact layer of electrically conductive material.
• the opening of respective windows can be done by a photolithographic process, laser ablation, an etching process or a mechanical process.
• a contact layer of a plurality of superposed sub-layers of different, electrically conductive material is used.
• the present invention provides a package, wherein the package comprises a substrate, one or more devices are formed on a surface of the substrate, and wherein a hermetically sealing protective layer is formed on the one or more devices and on the surface of the substrate which has the following properties: impermeable to gas, impermeable to liquids, impermeable to electromagnetic waves, temperature resistant, electrically insulating and process resistant.
• the hermetically sealing protective layer comprises a plurality of sublayers arranged one above the other.
• one of the multiple partial layers is formed from a foil made of electrically insulating plastic.
• the film is preferably formed of a plastic material on polyimide, polyamide, polyethylene, polyphenol, polyetheretherketone and / or epoxy-based.
• one of the plurality of sublayers is a metal layer comprising a metal.
• the metal is preferably selected from a group consisting of aluminum, copper, titanium and nickel.
• one of the plurality of sublayers is an inorganic layer comprising an inorganic material.
• the inorganic material preferably comprises silicon oxide.
• one of the plurality of sublayers is a layer comprising an organically modified ceramic.
• one of the plurality of sublayers is an organic layer comprising an organic material, wherein the inorganic material is preferably parylene.
• the hermetically sealing protective layer contains a filler material.
• the filler material advantageously contains silicon oxide or carbon.
• the substrate consists of an insulating layer, a first metal layer deposited on a lower surface of the insulating layer, and a second structured metal layer deposited on a surface of the insulating layer facing away from the lower surface.
• contact pads are disposed on the surface of the substrate and on surfaces of the one or more components.
• the hermetically sealing protective layer has at each contact surface a window in which this contact surface is contacted free of the hermetically sealing protective layer and areally with a contact layer of electrically conductive material.
• the contact layer may comprise a plurality of individual layers of different, electrically conductive material arranged one above the other. Description of preferred embodiments of the invention:
• Figure 1 shows a cross section of a package according to an embodiment of the invention.
• FIG. 2 shows a cross section of a package in one stage of the manufacturing process according to an embodiment of the invention.
• FIG. 3 shows a cross-section of a package according to an embodiment of the invention.
• Figure 1 shows a cross section of a package according to an embodiment of the invention.
• components 3 are arranged on an upper surface 2 of the substrate 1.
• the substrate 1 has, for example, a DCB substrate which consists of an insulating layer 7, preferably of a ceramic material, of a first metallic layer 6 applied on a lower surface 101 of the insulating layer 7, preferably of copper and one on the lower surface 101 submitten upper surface 102 of the insulating layer 7 applied second metallic layer 12, preferably made of copper.
• the second metallic layer 12 on the upper surface 102 of the insulating layer 7 is partially removed down to the upper surface 102.
• components 3 are arranged on the side facing away from the first metallic layer 6 surface 103 of the second metal layer 12.
• the overall upper surface, generally designated 2, of the substrate 1 equipped with the devices 3 is provided by the exposed portions of the upper surface 102 of the insulating layer 7 and the upper surface 103 of the second metallic layer 12.
• the components 3 may be the same or different from one another.
• the components are power semiconductor chips.
• a hermetically sealing layer 4 is arranged, which bears tightly against surfaces and side surfaces of the components 3.
• the hermetically sealing layer 4 is further arranged on areas of the upper surface 2 of the substrate 1 located between the components 3 and closely abuts against the upper surface 2 of the substrate 1.
• the hermetic sealing layer 4 seals each individual component 3 hermetically against environmental influences.
• the hermetic protective layer 4 is in particular gas-impermeable, liquid-impermeable, impermeable to electromagnetic waves, temperature-resistant, electrically insulating and process-resistant.
• the hermetic protective layer 4 is temperature resistant to the permanent influence of temperatures of up to 15O 0 C.
• the hermetic protective layer 4 temperature-resistant to the lasting effect of temperatures up to 200 0 C.
• the hermetic protective layer 4 against the process resistance of acids, bases and solvents.
• the hermetic sealing layer 4 may include inorganic materials, organic materials, metals, polymers or organically modified ceramics.
• the hermetic sealing layer 4 may also contain other suitable materials that protect against environmental influences.
• metals are particularly suitable aluminum, copper, titanium or nickel.
• the metals can be applied, for example, by a sputtering process or by a vapor deposition process.
• Particularly suitable polymers are thermoset polymers or thermoplastic polymers.
• the hermetically sealing protective layer 4 may further contain one or more fillers.
• the filling material and by the variation of the filling material portion of the hermetically sealing protective layer 4 for example the thermal expansion coefficient of the hermetically sealing protective layer 4 to the thermal expansion coefficient of the substrate 1 or the components 3 are adjusted. As a result, thermal stresses that occur as a result of temperature influences can be reduced. Thermal stresses can lead to cracks or damage to the hermetically sealing protective layer 4, or reduce the adhesion of the hermetically sealing protective layer 4 on the components 3 and the substrate 1.
• the hermetically sealing protective layer 4 may comprise a plurality of sublayers 5 arranged one above the other.
• the individual partial layers 5 preferably have different functional materials.
• a first sub-layer 5-1 is electrically insulating
• a second sub-layer 5-2 impermeable to electromagnetic waves
• a third sub-layer 5-3 liquid-impermeable and gas-impermeable.
• a fourth sub-layer 5-4 protects the components 3 from mechanical damage.
• a first sub-layer 5-1 includes a vacuum-laminated film consisting of electrically insulating plastic material.
• the film may have an adhesive coating to improve the adhesion on the upper surface 2 of the substrate 1 and on the components 3.
• the thickness of the film can be 25 to 500 microns.
• a second sub-layer 5-2 is formed as a metal layer.
• the metal layer is tightly applied to the first sub-layer 5-1 and has a thickness sufficient to protect the devices 3 from electromagnetic waves.
• the metal layer preferably comprises aluminum, copper, titanium or nickel.
• the metal layer may be applied to the laminated film by a sputtering process or a vapor deposition process.
• a third sub-layer 5-3 is formed as an organic layer and preferably comprises parylene. The organic layer is tightly applied to the second sub-layer 5-2 and has a thickness sufficient to protect the devices 3 and sub-layers 5-1 and 5-2 disposed therefrom from liquids and gases.
• a fourth sub-layer 5-4 which is preferably a package layer, preferably comprises synthetic resin or another suitable molding material.
• the fourth sub-layer 5-4 protects the components 3 from mechanical damage.
• the order and the number of sublayers 5 arranged one above the other can also vary.
• the second sub-layer 5-2 may be formed as an organic layer
• the third sub-layer 5-3 as a metal layer.
• Figure 2 shows a cross section of a package at a stage of the manufacturing process according to an embodiment of the invention.
• Contact surfaces 8 on surfaces of the devices 3 and on the upper surface 2 of the substrate 1 are exposed by opening windows 9 in the hermetically sealing layer 4.
• the windows 9 are opened by a structuring process.
• the hermetically sealing layer 4 is removed in the area of the contact surfaces 8 by means of laser ablation.
• the structuring can also be done by a photolithographic process.
• a photoresist can be applied to the hermetically sealing layer 4, dried and subsequently exposed.
• Suitable photoresists are conventional positive or negative resists (coating materials).
• the photoresist can be applied, for example, by a spraying or dipping process. But also electro-deposition for applying the photoresist is conceivable.
• Individual partial layers 5 of the hermetically sealing layer 4 can be structured by different structuring processes. For example, a partial layer 5 formed as a metallic layer can be patterned by means of a plasma etching process, and a partial layer 5 formed from electrically insulating plastic material can be structured by means of a photolithographic process.
• FIG. 3 shows a cross-section of the package shown in FIG. 2 after application of a structured contact layer 10 of electrically conductive material 10, preferably a metal, to the exposed contact areas 8.
• the application of the electrically conductive material 10 to the exposed contact areas 8 may involve the application of a mask on the hermetically sealing layer 4, which leaves the contact surfaces 8. Then, the electrically conductive material is applied over the entire surface of the hermetically sealing layer 4 and on the exposed contact surfaces 8. Thereafter, the mask with the contact layer 10 located thereon is removed, so that only the surface contacted contact surfaces 8 remain on the mask-free areas.
• the contact layer 10 may also comprise a plurality of superimposed individual layers 11-1, 11-2 made of different electrically conductive material.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Physics & Mathematics (AREA)
• Chemical & Material Sciences (AREA)
• Ceramic Engineering (AREA)
• Materials Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Laminated Bodies (AREA)
• Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (2)

Family

ID=37681045

Family Applications (1)

Country Status (4)

Families Citing this family (19)

Family Cites Families (13)

• 2005
  • 2005-08-10 DE DE102005037869A patent/DE102005037869B4/de not_active Expired - Fee Related
• 2006
  • 2006-07-28 WO PCT/EP2006/064787 patent/WO2007017404A2/de not_active Ceased
  • 2006-07-28 JP JP2008525534A patent/JP5174664B2/ja not_active Expired - Fee Related
  • 2006-07-28 US US11/990,263 patent/US7897881B2/en not_active Expired - Fee Related

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