WO2007001855A3 - Procede de fabrication d'un dispositif semi-conducteur a grille metallique - Google Patents

Procede de fabrication d'un dispositif semi-conducteur a grille metallique Download PDF

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Publication number
WO2007001855A3
WO2007001855A3 PCT/US2006/023121 US2006023121W WO2007001855A3 WO 2007001855 A3 WO2007001855 A3 WO 2007001855A3 US 2006023121 W US2006023121 W US 2006023121W WO 2007001855 A3 WO2007001855 A3 WO 2007001855A3
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
over
gate
polysilicon gate
sidewall spacer
Prior art date
Application number
PCT/US2006/023121
Other languages
English (en)
Other versions
WO2007001855A2 (fr
Inventor
Thomas W Andre
Chitra K Subramanian
Original Assignee
Freescale Semiconductor Inc
Thomas W Andre
Chitra K Subramanian
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Thomas W Andre, Chitra K Subramanian filed Critical Freescale Semiconductor Inc
Publication of WO2007001855A2 publication Critical patent/WO2007001855A2/fr
Publication of WO2007001855A3 publication Critical patent/WO2007001855A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1695—Protection circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/02—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using magnetic or inductive elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Une grille (18) de silicium polycristallin comportant des motifs est prévue sur une couche métallique (16), laquelle se situe sur une couche diélectrique (14) de grille, elle-même placée sur un substrat (12) semi-conducteur. Une couche mince (20) de matière est déposée sur la grille (18) de silicium polycristallin, et la couche métallique (16) exposée est ensuite attaquée afin de former un espaceur (22) de paroi latérale sur la grille (18) et d'exposer à nouveau la partie précédemment exposée de la couche métallique (16). La couche métallique (16) réexposée est attaquée à l'aide d'un agent d'attaque chimique sélectif par rapport à la matière diélectrique de grille et à l'espaceur (22). Même si l'attaque est sensiblement anisotrope, elle comporte un composant anisotrope qui attaquerait la paroi latérale de la grille (18) si celle-ci n'était pas protégée par l'espaceur (22). Après l'élimination du métal (16) réexposé, un transistor est formé, la couche métallique (12, 24) servant de grille du transistor.
PCT/US2006/023121 2005-06-24 2006-06-13 Procede de fabrication d'un dispositif semi-conducteur a grille metallique WO2007001855A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/166,139 US7224630B2 (en) 2005-06-24 2005-06-24 Antifuse circuit
US11/166,139 2005-06-24

Publications (2)

Publication Number Publication Date
WO2007001855A2 WO2007001855A2 (fr) 2007-01-04
WO2007001855A3 true WO2007001855A3 (fr) 2007-05-31

Family

ID=37567170

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/023121 WO2007001855A2 (fr) 2005-06-24 2006-06-13 Procede de fabrication d'un dispositif semi-conducteur a grille metallique

Country Status (7)

Country Link
US (2) US7224630B2 (fr)
EP (2) EP1897129A4 (fr)
JP (1) JP2008547222A (fr)
KR (1) KR101334819B1 (fr)
CN (1) CN101553878B (fr)
TW (1) TW200710863A (fr)
WO (1) WO2007001855A2 (fr)

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US7777261B2 (en) * 2005-09-20 2010-08-17 Grandis Inc. Magnetic device having stabilized free ferromagnetic layer
US7973349B2 (en) * 2005-09-20 2011-07-05 Grandis Inc. Magnetic device having multilayered free ferromagnetic layer
US7486535B2 (en) * 2007-03-28 2009-02-03 Freescale Semiconductor, Inc. Method and device for programming anti-fuses
US7957179B2 (en) * 2007-06-27 2011-06-07 Grandis Inc. Magnetic shielding in magnetic multilayer structures
US7872934B2 (en) * 2007-12-14 2011-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for writing data into memory
US8735885B2 (en) * 2007-12-14 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Antifuse memory device
US7894248B2 (en) * 2008-09-12 2011-02-22 Grandis Inc. Programmable and redundant circuitry based on magnetic tunnel junction (MTJ)
JP5571303B2 (ja) * 2008-10-31 2014-08-13 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
US7750694B1 (en) * 2008-11-11 2010-07-06 Altera Corporation Power on reset circuitry for manufacturability and security using a fuse
JP2010182365A (ja) * 2009-02-04 2010-08-19 Elpida Memory Inc アンチヒューズ回路及び半導体記憶装置
KR101086858B1 (ko) * 2009-04-15 2011-11-25 주식회사 하이닉스반도체 라이트 전압을 생성하는 비휘발성 반도체 메모리 회로
IN2012DN01702A (fr) 2009-07-31 2015-06-05 Stafford Simon
US8116130B1 (en) * 2009-09-01 2012-02-14 Altera Corporation Integrated circuits with nonvolatile memory elements
US8547736B2 (en) * 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
KR101710056B1 (ko) * 2010-08-11 2017-02-27 삼성전자주식회사 퓨즈 회로, 이를 포함하는 퓨즈 어레이 및 반도체 메모리 장치
KR101811303B1 (ko) 2011-07-26 2017-12-26 에스케이하이닉스 주식회사 반도체 집적회로 및 그의 구동 방법
US9093149B2 (en) 2012-09-04 2015-07-28 Qualcomm Incorporated Low cost programmable multi-state device
US9336847B2 (en) * 2014-04-21 2016-05-10 Qualcomm Incorporated Method and apparatus for generating a reference for use with a magnetic tunnel junction
US9455015B2 (en) * 2014-10-10 2016-09-27 Everspin Technologies, Inc. High temperature data retention in magnetoresistive random access memory
US9614144B1 (en) 2015-12-21 2017-04-04 International Business Machines Corporation Otp mram
CA2952941C (fr) * 2016-01-08 2018-12-11 Sidense Corp. Generation de valeur de fonction physique non clonable au moyen d'un reseau de memoires antifusibles
JP7086961B2 (ja) * 2016-08-29 2022-06-20 スカイワークス ソリューションズ，インコーポレイテッド ヒューズ状態検出回路、デバイス及び方法
JP6622745B2 (ja) * 2017-03-30 2019-12-18 キヤノン株式会社 半導体装置、液体吐出ヘッド用基板、液体吐出ヘッド、及び液体吐出装置
US10276239B2 (en) * 2017-04-27 2019-04-30 Ememory Technology Inc. Memory cell and associated array structure
CN108564978B (zh) * 2018-04-20 2021-09-24 电子科技大学 一种具有冗余结构的读电路
KR20220144019A (ko) 2021-04-16 2022-10-26 삼성전자주식회사 메모리 셀의 크기 및 초기 쓰기 전압의 값에 기반하여 최적의 쓰기 전압을 생성하는 메모리 장치
US20230267982A1 (en) 2022-02-24 2023-08-24 Everspin Technologies, Inc. Low resistance mtj antifuse circuitry designs and methods of operation
CN114627945B (zh) * 2022-05-12 2023-06-09 杭州晶华微电子股份有限公司 eFuse存储单元和eFuse系统

Citations (2)

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Publication number Priority date Publication date Assignee Title
US20050009358A1 (en) * 2003-07-10 2005-01-13 Applied Materials, Inc. Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode
US20050051854A1 (en) * 2003-09-09 2005-03-10 International Business Machines Corporation Structure and method for metal replacement gate of high performance

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US6661693B2 (en) * 1995-08-31 2003-12-09 Micron Technology Circuit for programming antifuse bits
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Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US20050009358A1 (en) * 2003-07-10 2005-01-13 Applied Materials, Inc. Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode
US20050051854A1 (en) * 2003-09-09 2005-03-10 International Business Machines Corporation Structure and method for metal replacement gate of high performance

Also Published As

Publication number Publication date
US20060291315A1 (en) 2006-12-28
EP2421003A2 (fr) 2012-02-22
US7224630B2 (en) 2007-05-29
CN101553878B (zh) 2012-03-14
EP2421003B1 (fr) 2013-11-13
EP1897129A4 (fr) 2010-10-20
KR101334819B1 (ko) 2013-11-29
KR20080034848A (ko) 2008-04-22
US20070188190A1 (en) 2007-08-16
CN101553878A (zh) 2009-10-07
EP2421003A3 (fr) 2012-03-07
EP1897129A2 (fr) 2008-03-12
JP2008547222A (ja) 2008-12-25
US7532533B2 (en) 2009-05-12
TW200710863A (en) 2007-03-16
WO2007001855A2 (fr) 2007-01-04

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