WO2006117854A1 - Dispositif semi-conducteur et procede de fabrication de celui-ci - Google Patents

Dispositif semi-conducteur et procede de fabrication de celui-ci Download PDF

Info

Publication number
WO2006117854A1
WO2006117854A1 PCT/JP2005/008059 JP2005008059W WO2006117854A1 WO 2006117854 A1 WO2006117854 A1 WO 2006117854A1 JP 2005008059 W JP2005008059 W JP 2005008059W WO 2006117854 A1 WO2006117854 A1 WO 2006117854A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
region
semiconductor device
wiring layer
word
Prior art date
Application number
PCT/JP2005/008059
Other languages
English (en)
Japanese (ja)
Inventor
Hiroshi Murai
Original Assignee
Spansion Llc
Spansion Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc, Spansion Japan Limited filed Critical Spansion Llc
Priority to PCT/JP2005/008059 priority Critical patent/WO2006117854A1/fr
Priority to JP2007514423A priority patent/JP4927716B2/ja
Publication of WO2006117854A1 publication Critical patent/WO2006117854A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device that is a nonvolatile memory using a transistor having a plurality of charge storage regions and a manufacturing method thereof.
  • Nonvolatile memories which are semiconductor devices capable of rewriting data, have been widely used.
  • technological development is being promoted for the purpose of miniaturizing memory cells and reducing fluctuations in electrical characteristics of transistors constituting the memory due to high storage capacity.
  • Non-volatile memories include MONOS (Metal Oxide Nitride Oxide Silicon) type and SONOS (Silicon Oxide Nitride Oxide Silicon) type flash memories that store charges in an ONO (Oxide / Nitride / Oxide) film.
  • ONO Oxide / Nitride / Oxide
  • Patent Document 1 discloses a transistor having two charge storage regions between a gate electrode and a semiconductor substrate. This transistor operates symmetrically by switching the source and drain. Thus, the source region and the drain region are not distinguished. Furthermore, the bit line force S doubles as a source region and a drain region, and has a structure embedded in a semiconductor substrate. Thereby, miniaturization of the memory cell is achieved.
  • FIG. 1 is a top view of a conventional memory cell.
  • Bit lines 44 embedded in the semiconductor substrate extend in the vertical direction.
  • An ONO film (not shown) is formed on the semiconductor substrate.
  • the word line 46 is formed on the ONO film and extends in the width direction of the bit line 44! /.
  • bit line 44 is formed of, for example, a diffusion layer formed by ion implantation of arsenic, the resistance is relatively high. If the resistance of the bit line 44 is high, the write / erase characteristics deteriorate. Therefore, a contact hole 48 is provided for every plurality of word lines 46 and bit lines 44 and wiring layers (shown in the figure) Not connected). Since the wiring layer is made of metal and has low resistance, it is possible to prevent the write / erase characteristics from being deteriorated.
  • a contact hole 48 that connects the bit line 44 and the wiring layer is provided in the bit line contact region 28.
  • the bit line contact region 28 extends in the longitudinal direction of the word line 46. Between the bit line contact regions 28, a word line region 26 without a contact hole 18 connecting the bit line 44 and the wiring layer is provided across a plurality (two in the figure) of word lines 46.
  • the bit line 44 includes a source region and a drain region of the transistor 50.
  • Word line 46 also includes the gate electrode of transistor 50! /. It functions as a non-volatile memory by storing charge in the ONO film under the word line 46 (gate electrode) between the bit lines 44 (source region and drain region).
  • the ONO film of the transistor 50 has two charge storage regions.
  • Patent Document 1 US Patent No. 6011725
  • An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can secure a margin for alignment of a contact hole and a bit line and can miniaturize a memory cell.
  • the present invention provides a bit line embedded in a substrate, a word line that intersects the bit line and extends in a width direction of the bit line, intersects the word line, and the bit line A wiring layer extending in the longitudinal direction; and a bit line contact region extending between the word lines extending in the longitudinal direction of the word lines and arranged with a plurality of the word lines.
  • every other wiring layer The semiconductor device is connected to the bit line.
  • the bit line connected to the wiring layer is connected to the bit line under the wiring layer.
  • the line can be expanded. Thereby, it is possible to secure a margin for alignment of the contact hole and the bit line. Therefore, it is possible to provide a semiconductor device in which the interval between the bit lines can be narrowed and the memory cell can be miniaturized.
  • the bit line connected to the wiring layer has a contact pad wider in the bit line contact region than a width of the bit line in the word line region.
  • a semiconductor device can be obtained.
  • the bit line since the bit line has the contact pad in the bit line contact region, it is possible to further secure an alignment margin between the contact hole and the bit line.
  • a semiconductor device capable of further miniaturizing the memory cell can be provided.
  • the present invention may be a semiconductor device in which the contact pads adjacent in the width direction of the bit line are electrically isolated.
  • the electrical isolation may be a semiconductor device in which elements are isolated in a trench isolation region. According to the present invention, even if the contact hole loses the contact pad force, the contact hole is formed on the trench isolation region and no junction current flows. Therefore, it is possible to secure a further alignment margin between the contact hole and the bit line. Thus, a semiconductor device capable of further miniaturizing the memory cell can be provided.
  • the wiring layer that is separated from the bit line in the first bit line contact region has the bit line contact region in the second bit line contact region adjacent to the word line region.
  • a semiconductor device connected to a line can be obtained.
  • the present invention provides a semiconductor device in which the bit line is connected to one wiring layer only in one bit line contact region, and extends to the word line region on both sides of the bit line contact region. Can do.
  • the present invention may be a semiconductor device in which the bit lines adjacent in the longitudinal direction of the bit line are electrically isolated in the bit line contact region.
  • the electrical isolation may be a semiconductor device in which elements are isolated in a trench isolation region.
  • the two bit lines connected to the transistors provided in the word line region are respectively connected to the bit line contact regions formed on opposite sides of the word line region.
  • the semiconductor device can be connected to the wiring layer.
  • the present invention can be a semiconductor device in which the bit line also serves as a source region and a drain region, and the word line serves as a gate electrode provided on an ONO film formed on the semiconductor substrate.
  • the present invention includes a step of forming a bit line embedded in a semiconductor substrate, a step of forming a word line that intersects the bit line and extends in the width direction of the bit line, and the word Forming a wiring layer that intersects the line and extends in the longitudinal direction of the bit line, and the step of forming the wiring layer includes placing the wiring layer in the longitudinal direction of the word line.
  • a method of manufacturing a semiconductor device comprising a step of connecting to every other bit line in a bit line contact region provided between word line regions extending and arranging a plurality of the word lines. According to the present invention, every other bit line is connected to the bit line in the bit line contact area, so that it is connected to the bit line! / ,!
  • the bit lines connected to the layers can be expanded. Thereby, it is possible to secure a margin for alignment of the contact hole and the bit line. Therefore, it is possible to provide a method for manufacturing a semiconductor device capable of reducing the interval between bit lines and miniaturizing memory cells.
  • the step of forming the bit line includes a step of forming a contact pad, and the contact pad is included in the bit line to be connected to the wiring layer in the bit line contact region.
  • the present invention can be a semiconductor device manufacturing method including a step of forming a trench isolation region in a region where the contact pads adjacent to each other are to be formed. In the present invention Therefore, even if the contact hole is removed from the contact pad, the contact hole is formed on the trench isolation region and no junction current flows. Therefore, it is possible to further secure a contact hole and bit line alignment margin. As a result, it is possible to provide a method for manufacturing a semiconductor device capable of further miniaturizing a memory cell.
  • the present invention can be a method for manufacturing a semiconductor device, wherein the step of forming the bit line includes a step of implanting ions into the bit line and the trench isolation region adjacent to the bit line. According to the present invention, even when the trench isolation region and the bit line are misaligned, the trench isolation region and the bit line can be formed in contact with each other. As a result, the junction current can be prevented more reliably. Thus, it is possible to provide a method for manufacturing a semiconductor device capable of further miniaturizing a memory cell.
  • the present invention includes a step of forming an ONO film on the semiconductor substrate, and the step of forming the word line is a step of forming the word line including a gate electrode on the ONO film. It can be set as the manufacturing method of a semiconductor device.
  • every other wiring layer is connected to the bit line in the bit line contact region, so that the wiring layer is connected to the wiring layer under the wiring layer not connected to the bit line.
  • the bit line can be expanded. This increases the margin for aligning contact holes and bit lines. Therefore, it is possible to provide a semiconductor device capable of reducing the interval between bit lines and miniaturizing memory cells.
  • FIG. 1 is a top view of a memory cell of a flash memory according to the prior art.
  • FIG. 2 is a top view (part 1) of the memory cell of the flash memory according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a memory cell of the flash memory according to the first embodiment.
  • FIG. 4 is a top view (part 2) of the memory cell of the flash memory according to the first embodiment.
  • FIG. 5 is a diagram comparing the bit lines of the flash memory according to the prior art and the first embodiment, (a) is a top view of the bit line of the prior art, and (b) is the bit of the first embodiment. It is a top view of the line.
  • FIG. 6 is a top view (part 1) illustrating the method for manufacturing the flash memory according to the first embodiment.
  • FIG. 7 is a sectional view (No. 1) showing the method for manufacturing the flash memory according to the first embodiment.
  • FIG. 8 is a top view (part 2) illustrating the method for manufacturing the flash memory according to the first embodiment.
  • FIG. 9 is a sectional view (No. 2) showing the method for manufacturing the flash memory according to the first embodiment.
  • FIG. 10 is a top view (part 3) illustrating the method for manufacturing the flash memory according to the first embodiment.
  • FIG. 11 is a sectional view (No. 3) showing the method for manufacturing the flash memory according to the first embodiment.
  • FIG. 12 is a top view (part 1) illustrating the method for manufacturing the flash memory according to the second embodiment.
  • FIG. 13 is a top view (No. 2) showing the method for manufacturing the flash memory according to the second embodiment.
  • FIG. 14 is a cross-sectional view showing the method for manufacturing the flash memory according to the second embodiment.
  • FIG. 15 is a top view (No. 3) showing the method for manufacturing the flash memory according to the second embodiment.
  • FIG. 2 is a top view (a protective film, a wiring layer, and an interlayer insulating film are not shown) of the memory cell of the flash memory according to the first embodiment.
  • FIG. 2 does not show the wiring layer 22 for easy understanding of the arrangement and shape of the bit line 14.
  • 3A is a cross-sectional view taken along the line AA of the bit line contact region 28 in FIG. 4, and
  • FIG. 3B is a cross-sectional view taken along the line BB of the region 22 of the wiring layer in FIG.
  • FIG. 4 is a top view illustrating the wiring layer 22 in FIG.
  • a bit line 14 is embedded in the semiconductor substrate 10.
  • An ONO film 12 is formed on the semiconductor substrate 10.
  • the word line 16 is formed on the ONO film 12 and intersects the bit line 14 and extends in the longitudinal direction of the bit line 14.
  • a plurality (two in FIG. 2) of word lines 16 are arranged in the word line area 26.
  • the bit line contact region 28 extends in the longitudinal direction of the word line 16 and is provided between the word line regions 26.
  • the bit line 14 includes a source region and a drain region of the transistor 52.
  • Word line 16 includes the gate electrode of transistor 52. It functions as a nonvolatile memory by accumulating charges in the ONO film 12 under the word line 16 (gate electrode) between the bit lines 14 (source region and drain region). Further, the ONO film 12 of the transistor 52 can have two charge storage regions as in the prior art.
  • every other wiring layer 22 has a contact hole 18 connected to the bit line 14.
  • the bit line 14 connected to the wiring layer 22 through the contact hole 18 has a contact pad 15 having a width wider than the width of the bit line 14 in the word line region 26 in the bit line contact region 28. Further, adjacent contact pads 15 are electrically separated by the semiconductor substrate 10.
  • FIG. 5 is a top view of the prior art bit line 44 (FIG. 5 (a)) and the bit line 14 of the first embodiment (FIG. 5 (b)).
  • the bit line 14 of the first embodiment has a contact pad 15. This is due to the following reasons. From FIG. 2, in the bit line contact region 28, a contact hole 18 is formed in each wiring layer 22. For this reason, the bit line 14 connected to the wiring layer 22 can be expanded under the wiring layer 22 where the contact hole 18 is not formed. Therefore, in the bit line contact region 28, the bit line 14 connected to the wiring layer 22 through the contact hole 18 can have a wide contact pad 15.
  • the contact hole 18 is prevented from losing the bit line 14 (contact pad 15) force.
  • the interval between the bit lines 14 can be made smaller than that of the prior art.
  • the bit line interval can be about 1Z2 as compared with the prior art. Therefore, the memory cell can be miniaturized.
  • the reason why the contact pad 15 can be provided in the bit line contact region 28 is as follows.
  • the wiring layer 22 separated from the bit line 14 in the bit line contact region 28a (first bit line contact region) is adjacent to the bit line contact region 28b (second bit line contact) across the word line region 26. In the area, it is connected to bit line 14.
  • the bit line 14 is connected to one wiring layer 22 only in one bit line contact region 28, and extends to the word line regions 26 on both sides of the bit line contact region 28. Accordingly, the bit line 14 does not need to extend to the bit line contact region 28 that is not connected to the wiring layer 22. That is, the bit line 14 adjacent in the longitudinal direction of the bit line 14 is electrically isolated in the bit line contact region 28.
  • the bit line 14 of the first embodiment can be shortened.
  • the bit line 14 connected to the wiring layer 22 can expand the contact pad 15 to the bottom of the wiring layer 22 in the region 28.
  • the current flowing through the transistor 50 is supplied from the bit line contact regions 28a and 28b. Since the transistor is located in the bit line contact region 28a, the current is supplied mainly from the bit line contact region 28a as shown by the arrow in FIG. In contrast, in the first embodiment, the current flowing through the transistor 52 is supplied from the bit line contact region 28a and reaches the bit line contact region 28b as shown by the arrow in FIG. That is, the two bit lines 14 connected to the transistors 52 provided in the word line region 26 are respectively connected to the wiring layer 22 in the bit line contact regions 28 formed on opposite sides of the word line region 26. It is connected.
  • bit line 14 does not need to extend to the bit line contact region 28 that is not connected to the wiring layer 22. Therefore, in the bit line contact region 28, the bit line 14 connected to the wiring layer 22 can expand the contact pad 15 in the region 28 to below the wiring layer 22.
  • a method for manufacturing the flash memory according to the first embodiment will be described with reference to FIGS.
  • a tunnel oxide film made of an oxide silicon film, a trap layer made of a silicon nitride film, an acid film A top oxide film made of a silicon film is formed using, for example, a CVD method.
  • a photoresist 24 is coated on the ONO film 12, and a predetermined area is opened using a normal exposure technique. For example, arsenic is ion-implanted using the photoresist 24 as a mask, and heat treatment is performed to form the bit line 14 embedded in the semiconductor substrate 10.
  • FIG. 6 and 7 are views at this time, FIG. 6 is a top view, FIG. 7A is a cross-sectional view taken along the line AA of the bit line contact region 28, and FIG. 7B is a wiring layer 22 B-B cross-sectional view of the region where The Simultaneously with the formation of the bit line 14, the contact pad 15 is formed.
  • the contact pad 15 is included in the bit line 14 to be connected to the wiring layer 22 in the bit line contact region 28. Further, the contact pad 15 is wider in the bit line contact region 28 than the width of the bit line 14 in the word line region 26. wide.
  • the region where the adjacent contact pads 15 are to be formed is element-isolated by the semiconductor substrate 10.
  • FIG. 9 (a) is an A-A cross-sectional view of the bit line contact region 28
  • Fig. 9 (b) is a BB cross-sectional view of the region of the word line 16
  • Fig. 9 (c) is FIG. 5 is a cross-sectional view taken along the line C-C in a region where a wiring layer 22 is formed.
  • Photoresist 24 is removed.
  • a polycrystalline silicon film is formed on the ONO film 12, and a predetermined region is removed using a normal exposure technique and etching technique.
  • a word line 16 intersecting the bit line 14 is formed.
  • FIG. 9 (a) is an A-A cross-sectional view of the bit line contact region 28
  • Fig. 9 (b) is a BB cross-sectional view of the region of the word line 16
  • Fig. 9 (c) is FIG. 5 is a cross-sectional view taken along the line C-C in a region where a wiring layer 22 is formed.
  • Photoresist 24 is
  • the semiconductor substrate 10 between the bit lines 14 below the word lines 16 becomes a channel.
  • the bit line 14 below the word line 16 becomes a source region and a drain region.
  • the word line 16 on the channel becomes the gate electrode.
  • a plurality (two in FIG. 10) of word lines 16 are arranged in the word line area 26.
  • Fig. 10 is a top view (interlayer insulating film not shown)
  • Fig. 11 (a) is a cross-sectional view of the bit line contact region 28 taken along the line A-A
  • Fig. 11 (b) is a region B where the wiring layer 22 is formed.
  • a silicon oxide film such as BPSG (Boro-Phospho Silicated Glass), for example, is formed on the ONO film 12 and the word line 16 as the interlayer insulating film 20 by the CVD method.
  • a contact hole 18 is formed in a predetermined region of the interlayer insulating film 20 using a normal exposure technique and etching technique.
  • the contact hole 18 is filled with TiZWN or TiZTiN and W, for example.
  • a wiring layer 22 intersecting the word line 16 is formed using, for example, A1.
  • the wiring layer 22 extends in the longitudinal direction of the word line 16 and in the bit line contact region 28 provided between the single line regions 26 where the plurality of word lines 16 are arranged, every other bit line Connect with 14.
  • a protective film 34 is formed on the interlayer insulating film 20 and the wiring layer 22.
  • FIG. 12 to 15 show a memory cell of a flash memory according to the second embodiment and a manufacturing method thereof.
  • FIG. 12, 13 and 15 are top views
  • FIG. 14 is a cross-sectional view taken along line AA in FIG.
  • a normal STI (Shallow Trench Isolation) method is used in a predetermined region of a P-type silicon semiconductor substrate 10 to form a trench isolation region 30 in the semiconductor substrate 10.
  • the trench isolation region 30 is a region in which a trench (trench) portion is formed in the semiconductor substrate 10 and an oxide silicon film is formed and buried in the trench portion. Since the semiconductor is removed and a silicon oxide film is formed, the leakage current can be suppressed.
  • the trench isolation region 30 is formed by the following method, for example.
  • the semiconductor substrate 10 in a predetermined region is etched by a dry etching method to form a groove. Thereafter, a silicon oxide film is formed on the entire surface by thermal oxidation or CVD. Flatten by CMP (Chemical Mechanical Polish) method or selective etching. As a result, the silicon oxide film is buried in the trench, and the trench isolation region 30 is formed.
  • a trench isolation region 30 is formed in the bit line contact region 28 in a region where the contact hole 18 is not formed in the wiring layer 22. That is, a trench isolation region is formed in a region where a space between adjacent contact pads 35 is to be formed.
  • the ONO film 12 is formed on the semiconductor substrate 10 in the same manner as in the first embodiment.
  • a photoresist 32 is formed on the ON O film 12.
  • the opening of the photoresist 32 is formed continuously in the extending direction of the word line 16 in the bit line contact region 28 and continuously in the extending direction of the wiring layer 22 in the region where the wiring layer 22 is formed. Formed.
  • the openings of the photoresist 32 have a lattice shape.
  • arsenic is ion-implanted into the semiconductor substrate 10 to form the bit line 34.
  • arsenic implanted into the trench isolation region 30 does not become active. Therefore, the bit line 34 can be formed in contact with the trench isolation region 30.
  • FIG. 15 is a top view of the memory cell of the completed flash memory, and the protective film, wiring layer, interlayer insulating film, and word line are not shown.
  • the bit line 34 has a contact node 35.
  • Example 1 is the same as Example 1 except that a trench isolation region 30 is provided between adjacent contact pads 35. That is, between the contact pads 35 adjacent in the width direction of the bit line and between the bit lines 34 adjacent in the longitudinal direction of the bit line 34. Are electrically isolated in the trench isolation region 30.
  • junction leakage does not flow between the bit line 34 and the semiconductor substrate 10. Thereby, the interval between the bit lines 34 can be further reduced as compared with the first embodiment, and the memory cell can be miniaturized.
  • the step of forming the bit line 34 is performed by implanting, for example, arsenic ions into the bit line 34 and the trench isolation region 30 adjacent to the bit line 34. Is forming.
  • the bit line 34 and the trench isolation region 30 can be formed in contact with each other. Therefore, even if the trench isolation region 30 and the bit line 34 are misaligned, it is possible to prevent a junction current from flowing between the bit line 34 and the semiconductor substrate 10.
  • the opening of the photoresist 32 has a lattice shape, but the opening preferably includes at least the bit line 34 and the trench isolation region 30 adjacent to the bit line 34.
  • the trench isolation region 30 adjacent to the bit line 34 is, for example, a range with a margin of alignment between the trench isolation region 30 and the bit line 34.

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L’invention concerne un dispositif semi-conducteur avec une ligne de bits (14) incorporée à un substrat semi-conducteur (10) ; une ligne de mots (16) qui croise la ligne de bits (14) et s’étend dans le sens de la largeur de ladite ligne de bits ; une couche de câblage (22) qui croise la ligne de mots (16) et s’étend dans le sens longitudinal de ladite ligne de bits ; et une zone de contact de ligne de bits (28) qui s’étend dans le sens longitudinal de ladite ligne de mots et est disposée entre les zones de lignes de mots (26) où sont disposées la pluralité de lignes de mots. Dans ladite zone de contact de lignes de mot, la couche de câblage est connectée à une ligne de bits sur deux. L’invention concerne également un procédé de fabrication dudit dispositif à semi-conducteur. En particulier, l’invention concerne ledit dispositif semi-conducteur, dans lequel une marge d’alignement pour l’orifice de contact et ladite ligne de bits est assurée et dans lequel une cellule de mémoire est microminiaturisée, ainsi qu’un procédé de fabrication de celui-ci.
PCT/JP2005/008059 2005-04-27 2005-04-27 Dispositif semi-conducteur et procede de fabrication de celui-ci WO2006117854A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2005/008059 WO2006117854A1 (fr) 2005-04-27 2005-04-27 Dispositif semi-conducteur et procede de fabrication de celui-ci
JP2007514423A JP4927716B2 (ja) 2005-04-27 2005-04-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/008059 WO2006117854A1 (fr) 2005-04-27 2005-04-27 Dispositif semi-conducteur et procede de fabrication de celui-ci

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/414,647 Continuation US7645693B2 (en) 2005-04-27 2006-04-27 Semiconductor device and programming method therefor

Publications (1)

Publication Number Publication Date
WO2006117854A1 true WO2006117854A1 (fr) 2006-11-09

Family

ID=37307661

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/008059 WO2006117854A1 (fr) 2005-04-27 2005-04-27 Dispositif semi-conducteur et procede de fabrication de celui-ci

Country Status (2)

Country Link
JP (1) JP4927716B2 (fr)
WO (1) WO2006117854A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7645693B2 (en) * 2005-04-27 2010-01-12 Spansion Llc Semiconductor device and programming method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0836890A (ja) * 1994-07-25 1996-02-06 Sony Corp 半導体不揮発性記憶装置
JPH10125806A (ja) * 1996-10-21 1998-05-15 Samsung Electron Co Ltd Ｎｏｒ形マスクｒｏｍ
JPH10334684A (ja) * 1997-05-24 1998-12-18 Samsung Electron Co Ltd 半導体ロム装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0836890A (ja) * 1994-07-25 1996-02-06 Sony Corp 半導体不揮発性記憶装置
JPH10125806A (ja) * 1996-10-21 1998-05-15 Samsung Electron Co Ltd Ｎｏｒ形マスクｒｏｍ
JPH10334684A (ja) * 1997-05-24 1998-12-18 Samsung Electron Co Ltd 半導体ロム装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7645693B2 (en) * 2005-04-27 2010-01-12 Spansion Llc Semiconductor device and programming method therefor

Also Published As

Publication number Publication date
JPWO2006117854A1 (ja) 2008-12-18
JP4927716B2 (ja) 2012-05-09

Similar Documents

Publication Publication Date Title
JP4325972B2 (ja) 不揮発性半導体記憶装置を含む半導体集積回路装置の製造方法
US7005328B2 (en) Non-volatile memory device
US20060108627A1 (en) NAND flash memory devices including multi-layer memory cell transistor structures and methods of fabricating the same
US7416935B2 (en) Method of manufacturing nonvolatile semiconductor memory device having adjacent selection transistors connected together
JP4818061B2 (ja) 不揮発性半導体メモリ
US7126203B2 (en) Semiconductor device having a capacitance device
JP2006186378A (ja) ツインビットセル構造のｎｏｒ型フラッシュメモリ素子及びその製造方法
WO2007013155A1 (fr) Dispositif semi-conducteur et son procédé de fabrication
US20100012999A1 (en) Semiconductor memory device and method of manufacturing the same
JP2006526284A (ja) ビット線構造およびその製造方法
US7812399B2 (en) Semiconductor device comprising multi-layer rectangular gate electrode surrounded on four sides by sidewall spacer and implantation regions
EP1898460B1 (fr) Dispositif semi-conducteur et son procédé de fabrication
JP5053084B2 (ja) 半導体装置およびその製造方法
US7602005B2 (en) Memory devices including spacer-shaped electrodes on pedestals and methods of manufacturing the same
JP2006054243A (ja) 半導体記憶装置及びその製造方法
US7645693B2 (en) Semiconductor device and programming method therefor
JPWO2006035503A1 (ja) 半導体装置および半導体装置の製造方法
JP4944766B2 (ja) 半導体装置及びその製造方法
JP4927716B2 (ja) 半導体装置
US8093645B2 (en) Non-volatile semiconductor memory device
US7902592B2 (en) Semiconductor device and method for manufacturing
JP2009164349A (ja) 不揮発性半導体記憶装置及びその製造方法
US20090140316A1 (en) Semiconductor memory device and method of fabricating the same
JP5099691B2 (ja) 半導体装置
KR100940644B1 (ko) 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007514423

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

NENP Non-entry into the national phase

Ref country code: RU

WWW Wipo information: withdrawn in national office

Country of ref document: RU

122 Ep: pct application non-entry in european phase

Ref document number: 05736685

Country of ref document: EP

Kind code of ref document: A1