WO2006114886A1 - マスク形成方法、及び三次元微細加工方法 - Google Patents
マスク形成方法、及び三次元微細加工方法 Download PDFInfo
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- WO2006114886A1 WO2006114886A1 PCT/JP2005/007792 JP2005007792W WO2006114886A1 WO 2006114886 A1 WO2006114886 A1 WO 2006114886A1 JP 2005007792 W JP2005007792 W JP 2005007792W WO 2006114886 A1 WO2006114886 A1 WO 2006114886A1
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- mask
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000010438 heat treatment Methods 0.000 claims abstract description 21
- 238000010894 electron beam technology Methods 0.000 claims description 48
- 239000013078 crystal Substances 0.000 claims description 45
- 239000004065 semiconductor Substances 0.000 claims description 27
- 150000001875 compounds Chemical class 0.000 claims description 17
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 11
- 239000002253 acid Substances 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 10
- 230000007704 transition Effects 0.000 claims description 10
- 238000010884 ion-beam technique Methods 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 6
- 238000003672 processing method Methods 0.000 claims description 6
- CPELXLSAUQHCOX-UHFFFAOYSA-M Bromide Chemical compound [Br-] CPELXLSAUQHCOX-UHFFFAOYSA-M 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 64
- 239000010408 film Substances 0.000 description 51
- 239000000758 substrate Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- 238000001179 sorption measurement Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000001338 self-assembly Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 238000001803 electron scattering Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000002105 nanoparticle Substances 0.000 description 3
- 238000002128 reflection high energy electron diffraction Methods 0.000 description 3
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 2
- -1 PBr Chemical class 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- KLRHPHDUDFIRKB-UHFFFAOYSA-M indium(i) bromide Chemical compound [Br-].[In+] KLRHPHDUDFIRKB-UHFFFAOYSA-M 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 150000001649 bromium compounds Chemical class 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 239000004038 photonic crystal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
- B81C1/00428—Etch mask forming processes not provided for in groups B81C1/00396 - B81C1/0042
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02642—Mask materials other than SiO2 or SiN
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/0042—Photosensitive materials with inorganic or organometallic light-sensitive compounds not otherwise provided for, e.g. inorganic resists
- G03F7/0043—Chalcogenides; Silicon, germanium, arsenic or derivatives thereof; Metals, oxides or alloys thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S430/00—Radiation imagery chemistry: process, composition, or product thereof
- Y10S430/143—Electron beam
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S430/00—Radiation imagery chemistry: process, composition, or product thereof
- Y10S430/145—Infrared
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S430/00—Radiation imagery chemistry: process, composition, or product thereof
- Y10S430/146—Laser beam
Definitions
- the present invention relates to Al Ga in As P or Al Ga In N As (0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1
- the pattern transfer type photolithographic technology which is currently becoming the mainstream, is aiming for high accuracy by using, for example, extreme ultraviolet light and X-rays, It is approaching the limit in terms of mask creation, photoresist resolution, process control, etc.
- Patent Document 1 by irradiating a Ga ion beam to the natural oxide film without removing the natural oxide film on the surface of the GaAs layer. After selectively replacing or forming the capsule with Ga 2 O or Ga 2 O, bromide
- Patent Document 1 Japan 'Japanese Unexamined Patent Publication No. 2003-51488 (paragraph number 0012, etc.)
- the resolution that has been used as a standard for miniaturization heretofore refers to the resolution after exposure on an organic resist that has been standardized in the lithography process, and functions as an original device. This is not the resolution of the semiconductor itself that has undergone final processing. This is because the conventional lithography process requires many steps for final processing on a semiconductor substrate, and the maximum resolution is determined by the first pattern transfer step on the organic resist. Actually, the pattern produced on the organic resist itself is transferred with “blurring” by a plurality of subsequent processes. In general, this “bokeh” differs depending on the intended processing method and material properties, and therefore it was difficult to define in general. Therefore, the current lithographic process is competing for resolution on organic resist, which is a standardized method.
- the diameter of the ion beam irradiated to the natural oxide film is desired to be reduced to 0.3 or less, preferably 0.3 m or less, and more preferably 0.1 m or less. This makes it impossible to form a fine mask sufficient for controlling the microstructure of the nano region.
- a drawing apparatus that can irradiate an ion beam with a thin beam diameter is expensive, which causes an increase in cost.
- the present invention has been made in view of the above circumstances, and one of its purposes is to provide a method for forming a mask having a fine width suitable for nanofabrication at a low cost and with high accuracy. There is to do. Furthermore, the target resolution here refers to the minimum control area in the final processing step on the semiconductor substrate.
- a method for forming a selective mask on a surface comprising: (1) A1 Ga In As P or Al Ga
- the semiconductor surface forms a different stable reconstructed surface in vacuum depending on the temperature in the step (3).
- the phase transition point where the surface reconstruction changes by repeating the descent the surface diffusion of the atoms constituting the substrate on the surface of the semiconductor substrate is excited even in the low temperature region, and the energy beam is irradiated. It is preferable to remove the natural oxide film except for the minute central part.
- the mask forming method it is preferable to use any one of an electron beam, an ion beam, a laser beam, and an infrared beam as the energy beam in the step (1).
- the Al Ga In As P or Al Ga In N is formed by molecular beam epitaxy after selectively forming the mask.
- the mask formed by the above method serves as a trigger for nucleation of the early stage diffusion of III-V compound semiconductors, after which the III-V compound semiconductor grows while self-assembling. Therefore, by controlling the growth conditions appropriately, it is possible to achieve extremely fine tertiary regardless of the mask width.
- the original structure can be realized.
- the group III V compound semiconductor crystal is obtained by supplying a dopant after selectively growing the group III V compound semiconductor crystal by self-assembly. It is preferable to form n-channel on one facet surface and p-channel on the other facet surface.
- n-type is the same in the crystal orientation (100) plane
- a fine transistor can be formed by a small number of processes, and the surface of the three-dimensional fine structure surface
- the three-dimensional microfabrication method of the present invention forms the selective mask described above, and then performs dry etching by supplying bromide as a molecular beam, whereby the Al Ga I
- a part of the natural oxide film functions as a negative mask by selectively irradiating an energy beam while changing the dose in the step (1). It is preferable to let some function as a positive mask.
- a group III V compound semiconductor crystal is selectively grown on the surface, thereby self-assembled microfabrication. It is characterized by forming a structure.
- the III-V compound semiconductor is adsorbed to the negative mask and repels the positive mask in the initial stage of diffusion.
- various forms 3D structures can be created.
- a group V compound semiconductor crystal is self-assembled and then a group III V compound semiconductor crystal is self-assembled and grown in a gap without the positive mask to selectively form a nano-sized micro structure.
- the Al Ga In As P is formed by dry etching with bromide.
- FIG. 1 is a schematic diagram showing a state in which a natural oxide film on the surface of a GaAs substrate is irradiated with an electron beam.
- FIG. 2 is a graph showing the intensity distribution of an electron beam applied to a natural oxide film on a substrate surface.
- FIG. 3 is a schematic view showing a state in which a positive mask and a negative mask are selectively formed.
- Fig. 3 is a schematic diagram showing the state power of GaAs crystal grown by MBE method, (a) is a schematic diagram when MBE growth is small, and (b) is a diagram when MBE growth is large. It is a schematic diagram.
- FIG. 5 is a schematic diagram showing a state force of FIG. 4 (a) in which Si is supplied as a molecular beam to form an n channel and a p channel.
- FIG. 6 is a schematic diagram showing the state force of FIG. 3 being dry-etched with AsBr.
- FIG. 7 is a graph showing changes in heating temperature in the heating process.
- FIG. 8 is a view showing the substrate surface after the three-dimensional microfabrication of the present invention.
- GaAs base as GaAs layer (AlGaInAsP or AlGaInNAs layer)
- a known electron without removing a natural oxide film 2 such as As 2 O 3 or As 2 that is naturally formed on the surface of a GaAs substrate 1.
- the surface of the natural oxide film 2 was irradiated with an electron beam (energy single beam) 4a in a high vacuum using a beam drawing device (step 1).
- the line dose of the electron beam 4a was controlled by appropriately changing the amount of electron beam current and the irradiation time.
- the irradiation interval of the electron beam 4a (the distance moved in parallel to the next irradiation line after the electron beam irradiation) was set to 50 nm. That is, the electron beam 4a was irradiated several times while shifting the line by 50 nm from a ⁇ b ⁇ c.
- the native oxide film 2 having a thickness of about 3 nm, such as As O or As O, is obtained.
- the 2 3 2 oxide was replaced by chemically stable Ga 2 O.
- the natural acid film 2 is an electronic
- the region (line width) modified by one electron beam 4a irradiation is about 7 m. there were.
- the reason why the line width of the modified region is larger than the electron beam diameter (1 / zm) is due to the secondary electron scattering of the natural oxide film 2 and the internal force of the substrate 1 when the electron beam 4a is irradiated. (Proximity effect).
- the temperature was raised to about 580 ° C. to 630 ° C. (step 2).
- steps other than the portion irradiated with the electron beam 4a (non-modified region) were thermally desorbed and removed.
- the above heating temperature is gradually lowered to about 450 ° C, then raised to about 540 ° C, and about 450 ° C.
- the heating temperature was increased and decreased alternately several times to several tens times (step 3).
- the energy distribution intensity of the electron beam 4a is larger than a certain level (the dose is larger than the critical level Lh shown in FIG. 2).
- the black part 3a and the minute central part corresponding to the hatched part 3b), which has a larger dose than L1 remain, while the other natural oxide film was removed by thermal desorption, resulting in the state shown in FIG. .
- the region (line width) of the remaining natural oxide film 3a was about lOnm.
- the surface of the GaAs layer 1 forms a stable reconstructed surface in a vacuum, but tries to form a reconstructed surface having a different structure at a certain temperature (phase transition).
- the temperature at this boundary is called the “phase transition point”, but the heating temperature rises and falls intentionally and alternately so as to cross the phase transition point (or touch the phase transition point).
- This causes a phase transition on the surface of GaAs layer 1 repeatedly, which corresponds to a weak portion of the energy distribution of electron beam 4a (a region where modification was performed but the degree was insufficient).
- the natural acid film 2 can be detached.
- a portion of the natural oxide film 2 other than the minute central portion can be removed.
- the phase transition point of the GaAs layer is about 540 ° C.
- a fine mask 3a having a line width of about lOnm could be formed on the GaAs layer.
- a fine mask that can be used sufficiently for controlling the microfabrication of the nano-region can be formed.
- the critical level of the line dose (level L in the graph of Fig. 2) for leaving the natural oxide film 2 as the mask 3a can be changed, so that the width of the formed mask 3a is several nm. It can be controlled to a desired width of about 5 ⁇ m.
- the GaAs layer on the side from which the natural oxide film 2 has been removed is formed by molecular beam epitaxy (hereinafter abbreviated as "MBE method").
- MBE method molecular beam epitaxy
- the crystal growth conditions are such that the growth direction of GaAs is aligned with the plane orientation (100) of the GaAs layer, the GaAs crystal growth temperature is 500 ° C to 650 ° C, and the flux ratio of Ga atoms to As4 molecules. F / Y 5-20, GaAs crystal growth speed
- the degree was 0.1 to 2 MLZsec (molecular layer Z second: growth rate conversion for two-dimensional thin film), and the GaAs growth layer thickness was set to about the electron beam writing interval.
- the supplied Ga atoms first avoid the portion where the Ga 2 O is formed (the mask 3a).
- a GaAs growth crystal 5 was formed by self-assembly using the GaAs layer as the nucleus (starting point). That is, Ga O (the mask 3a) as a modified natural oxide film functioned as a repulsion site (positive mask).
- the mask 3a can be sublimated during GaAs crystal growth and lost, or it can be left as shown in FIG. 4 (a).
- the GaAs crystal growth rate was adjusted using a reflection high-energy electron diffraction apparatus (hereinafter referred to as “RHEED”) for in-situ observation of the surface state of the sample thin film or the substrate. If the GaAs crystal growth rate is determined at this time, the film thickness and shape of the GaAs growth crystal 5 can be controlled by adjusting the GaAs crystal growth time. By such control, it is possible to produce a substrate having a high density and a constant film thickness of each GaAs growth crystal 5.
- RHEED reflection high-energy electron diffraction apparatus
- the GaAs layer 1 is naturally formed on the surface! And the natural oxide film 2 such as As O is removed. Without irradiating the natural oxide film 2 with the electron beam 4a, chemically stable Ga 2 O 3 (mask 3a) can be formed on the surface. From the diameter of electron beam 4a
- the natural oxide film 2 is patterned with the electron beam 4a so as to have a predetermined circuit pattern, a desired circuit pattern can be processed on the surface of the GaAs layer 1.
- the natural oxide film 2 is naturally formed on the GaAs layer 1 and plays a role as a kind of inorganic resist, organic resist-free can be realized and a mask raw material becomes unnecessary.
- it is not necessary to apply a resist material to the surface of the GaAs layer 1 in advance man-hours can be reduced.
- the sensitivity of the natural oxide film 2 when the electron beam 4a is used as in this embodiment is higher than that of PMM A that is generally used as an organic resist in existing electron beam lithography. . Therefore, extremely high-speed drawing is possible, and the throughput, which is a problem when using an inorganic resist, can be greatly improved.
- the electron beam 4a is used as an energy beam! /, But as a problem of electron beam lithography (including the case where an organic resist is used), secondary electron scattering from within the substrate is considered. It is generally said that the region larger than the beam diameter of the electron beam 4a becomes a resist reaction region due to the influence of the above (proximity effect). Many proposals have been made to reduce this proximity effect. In fact, this proximity effect has become a major obstacle to miniaturization.
- the mask forming method of the present embodiment only the portion modified by secondary electron scattering (proximity effect) of the natural acid film is removed, and the forward scattered component of the incident electron beam 4a is removed. Since only the portion corresponding to (the portion corresponding to the electron beam diameter) can be left, an effect equivalent to the correction of the proximity effect can be realized. Not only that, it is also possible to leave only the central part thinner than the beam diameter of the electron beam 4a.
- the heating temperature is controlled so as to intentionally repeat the rise and fall of the temperature and dynamically pass the phase transition point on the surface of the GaAs layer 1. I'm doing it. As a result, an order much smaller than the diameter of the irradiated electron beam 4a (eg (For example, nm order) mask formation is possible.
- direct writing on the natural oxide film 2 is realized, so that the price has increased in recent years, and a projection mask (so-called reticle) can be eliminated. .
- a GaAs crystal 5 is selectively grown on the surface of the GaAs layer 1 by MBE to form a self-assembled microstructure. is doing. Therefore, the natural oxide film 3a as a mask acts as a repulsion site (functions as a positive mask) and acts as a repulsion site trigger for nucleation of Ga atom diffusion, after which the GaAs crystal self-acts. Since the growth is performed while gathering, by controlling the growth conditions appropriately, a three-dimensional structure with extremely fine spacing can be realized regardless of the width of the mask 3a. For example, when the array structure is microfabricated using the above-described method, the distance between adjacent unit structures can be controlled to a desired distance of up to several / z m of zero force (regardless of the width of the mask 3a).
- the natural acid film 2 on the GaAs substrate 1 is irradiated with the electron beam 4b and heated in the same manner as described above, and shown on the right side of FIG.
- a fine mask 3b having a width of 1 Onm was prepared.
- the irradiation condition of the electron beam 4b is exactly the same as that in the first embodiment except that the line dose is 2.5 ⁇ 10 9 electron / cm.
- GaAs was selectively grown on the GaAs layer 1 on the side from which the surface oxide film 2 was detached by the MBE method. Then, in the initial stage of diffusion, Ga atoms adhere to the portion where the Ga 2 O is formed (mask 3b) (according to the first embodiment), and self-assembled by using it as a nucleus.
- GaAs growth crystal 5 was formed as shown on the right side of FIG.
- Ga O (mask 3b) as a modified natural oxide film functioned as an adsorption site (negative mask).
- GaO as a mask is sublimated during GaAs crystal growth and disappears.
- Fig. 4 (a) As shown on the right side of Fig. 4 (a), it can be considered that it is covered with a GaAs growth crystal 5.
- FIG. 4 (b) shows an example in which the amount of selective growth of GaAs by the MBE method as described above is increased considerably compared to the case of FIG.
- GaAs amorphous crystal growth 6a is formed on the surface of the repulsion site (positive mask) 3a as a result of the MBE growth.
- GaAs single crystal growth 6b was formed on the surface of the adsorption site (negative mask) 3b.
- a GaAs single crystal growth 6c was formed on the surface of the substrate 1 where neither a positive mask nor a negative mask was present. This example suggests the possibility of a three-dimensional fine shape by controlling the amount of selective growth of GaAs by the MBE method and the presence of a positive mask as well as a positive mask.
- a GaAs crystal is grown on the GaAs substrate 1 by self-assembly using the same method as in the first or second embodiment, as shown in FIG. A high density array structure was formed. Thereafter, Si as a dopant was supplied as a molecular beam. Then, as shown in Fig. 5, n-channel is formed on the facet plane (crystal orientation (100) plane) of each GaAs growth crystal 5 and other facet planes (crystal orientation (ni l) A plane, n is 3) A p-channel was formed. [0061]
- a large number of fine transistor structures could be formed with fewer steps. In other words, the pn control of the surface of each unit structure of the high-density array structure could be performed collectively.
- electron beams 4a and 4b are applied to the natural oxide film 2 of the GaAs substrate 1 and the line doses are 2.5 X 10 10 electron / cm and 2.5 X 10 9 electronZcm. Irradiation was performed in the same manner as described above, and thereafter, the same heat treatment as described above was performed, and as shown in FIG.
- the surface of the GaAs layer 1 was dry etched in units of one atomic layer. Then, as shown in FIG. 6, the portions where the masks 3a and 3b (Ga 2 O 3), which are chemically stable oxide films, are formed,
- the positive mask 3a is a force remaining on the surface of the GaAs layer 1 throughout the entire dry etching process.
- the negative mask 3b disappears on the way, and the portion corresponding to the negative mask 3b thereafter. (d ⁇ ; f) was also etched.
- the aspect ratio is different so that the positive mask 3a portion (a to c) and the negative mask 3b portion (d to f) have a height difference.
- the natural oxide film 2 can function as a so-called analog inorganic resist. That is, the negative mask 3b has many porous materials with lower crystallinity of GaO than the positive mask 3a.
- FIG. 8 shows various examples of the three-dimensional microstructure processed by the present invention.
- FIG. 8 shows an actual image of the microstructure formed by the method of the present invention using an atomic force microscope (AFM) or an electron microscope (SEM).
- AFM atomic force microscope
- SEM electron microscope
- the present invention is particularly effective in forming a fine and high-density array structure as variously shown in FIG. It is.
- the application of the present invention is not limited to the GaAs layer.
- the group III-V compound to be selectively grown is not limited to GaAs, and for example, GaN, InAs, InP, and InSb can be used.
- the energy beam applied to the natural oxide film is not limited to the electron beam, and for example, any one of an ion beam, a laser beam, and an infrared beam can be selected and used.
- the MBE method as in the first embodiment and the dry etching as in the fourth embodiment can be used in combination.
- three-dimensional microstructures with various shapes can be created.
- it is highly desirable that crystal growth and dry etching by the MBE method are performed in a series of steps using the same apparatus.
- the etchant gas in the dry etching of the fourth embodiment is not limited to the above AsBr.
- bromides such as PBr, GaBr, and InBr can be employed.
- the mask forming method of the above embodiment is! /, And the three-dimensional microfabrication method is not only a semiconductor device but also a wavelength discrimination device, micromachining, photonic crystal, microcomponent, quantum dot, Application to quantum wires is possible.
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JP2007514399A JP4755643B2 (ja) | 2005-04-25 | 2005-04-25 | マスク形成方法、及び三次元微細加工方法 |
PCT/JP2005/007792 WO2006114886A1 (ja) | 2005-04-25 | 2005-04-25 | マスク形成方法、及び三次元微細加工方法 |
US11/912,503 US8110322B2 (en) | 2005-04-25 | 2005-04-25 | Method of mask forming and method of three-dimensional microfabrication |
EP05734479A EP1879221A4 (en) | 2005-04-25 | 2005-04-25 | METHOD FOR MASKING AND METHOD FOR THREE-DIMENSIONAL MICROFABRICATION |
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PCT/JP2005/007792 WO2006114886A1 (ja) | 2005-04-25 | 2005-04-25 | マスク形成方法、及び三次元微細加工方法 |
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EP (1) | EP1879221A4 (ja) |
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Cited By (6)
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JP2009076795A (ja) * | 2007-09-22 | 2009-04-09 | Kwansei Gakuin | 三次元微細加工方法及び三次元微細構造 |
JP2010040680A (ja) * | 2008-08-01 | 2010-02-18 | Fujitsu Ltd | 量子ドットの形成方法及び半導体装置の製造方法 |
WO2010044400A1 (ja) * | 2008-10-14 | 2010-04-22 | 旭化成株式会社 | 熱反応型レジスト材料、それを用いた熱リソグラフィ用積層体及びそれらを用いたモールドの製造方法 |
JP2010237539A (ja) * | 2009-03-31 | 2010-10-21 | Kwansei Gakuin | 三次元微細加工方法及び三次元微細構造 |
JP2012049186A (ja) * | 2010-08-24 | 2012-03-08 | Tokyo Electron Ltd | 量子ドット形成方法及びこれを実施するためのプログラムを記憶する記憶媒体並びに基板処理装置 |
JP2013033995A (ja) * | 2012-10-19 | 2013-02-14 | Kwansei Gakuin | 三次元微細加工基板 |
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US7977253B2 (en) * | 2004-08-31 | 2011-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US8337712B2 (en) * | 2007-05-15 | 2012-12-25 | Canon Kabushiki Kaisha | Method for forming etching mask, method for fabricating three-dimensional structure and method for fabricating three-dimensional photonic crystalline laser device |
US20170324219A1 (en) * | 2016-05-05 | 2017-11-09 | Macom Technology Solutions Holdings, Inc. | Semiconductor laser incorporating an electron barrier with low aluminum content |
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- 2005-04-25 US US11/912,503 patent/US8110322B2/en not_active Expired - Fee Related
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009076795A (ja) * | 2007-09-22 | 2009-04-09 | Kwansei Gakuin | 三次元微細加工方法及び三次元微細構造 |
JP2010040680A (ja) * | 2008-08-01 | 2010-02-18 | Fujitsu Ltd | 量子ドットの形成方法及び半導体装置の製造方法 |
WO2010044400A1 (ja) * | 2008-10-14 | 2010-04-22 | 旭化成株式会社 | 熱反応型レジスト材料、それを用いた熱リソグラフィ用積層体及びそれらを用いたモールドの製造方法 |
JP5194129B2 (ja) * | 2008-10-14 | 2013-05-08 | 旭化成株式会社 | 熱反応型レジスト材料、それを用いた熱リソグラフィ用積層体及びそれらを用いたモールドの製造方法 |
JP2010237539A (ja) * | 2009-03-31 | 2010-10-21 | Kwansei Gakuin | 三次元微細加工方法及び三次元微細構造 |
JP2012049186A (ja) * | 2010-08-24 | 2012-03-08 | Tokyo Electron Ltd | 量子ドット形成方法及びこれを実施するためのプログラムを記憶する記憶媒体並びに基板処理装置 |
JP2013033995A (ja) * | 2012-10-19 | 2013-02-14 | Kwansei Gakuin | 三次元微細加工基板 |
Also Published As
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JPWO2006114886A1 (ja) | 2008-12-11 |
JP4755643B2 (ja) | 2011-08-24 |
US8110322B2 (en) | 2012-02-07 |
EP1879221A4 (en) | 2011-08-03 |
EP1879221A1 (en) | 2008-01-16 |
US20100143828A1 (en) | 2010-06-10 |
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