Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R19/0023—Measuring currents or voltages from sources with high internal resistance by means of measuring circuits with high input impedance, e.g. OP-amplifiers
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
  • G01R1/20—Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
  • G01R1/203—Resistors used for electric measuring, e.g. decade resistors standards, resistors for comparators, series resistors, shunts

Definitions

• the present invention generally relates to current monitoring, and more particularly relates to a circuit for sensing current across a known resistance.
• a current sensing circuit typically measures a voltage difference across a known resistance.
• One common method used for battery current monitoring utilizes a continuous time current measurement.
• the current sensing circuit typically uses a single- ended (i.e., a single voltage input to a differential amplifier) measurement that may be susceptible to noise and transients.
• the noise and transients may be reflected in the sensed current and thereby significantly affect the accuracy of the sensed current.
• the measured voltage difference is typically in the order of about 8OmV Full Scale, and the sensed current reflects the measured voltage difference across the low known resistance as a smaller current.
• the mobile communication product may use the sensed current to perform other functions that require an instantaneous and relatively accurate current measurement, such as in the order of about a ten (10) bit resolution.
• the sensed current may be fed to an Analog-to-Digital (A/D) converter to produce a relatively high resolution value of the sensed current for use in a downstream microprocessor.
• A/D Analog-to-Digital
• conventional continuous time measurements generally provide a measurement on the order of about a seven (7) bit resolution.
• the AfD converter, or other downstream component, coupled to the current sensing circuit may require an input within a pre-determined voltage range that is significantly greater than the measured voltage difference.
• the conventional continuous time measurements generally amplify the measured voltage difference within a single stage, the amplified output is generally limited by the size of the low known resistance. These constraints generally reduce the effectiveness of conventional continuous time measurements for mobile communication products and other devices requiring higher resolution battery current measurements.
• a circuit for sensing current is desired having reduced power consumption.
• a circuit for sensing relatively low current levels is desired that minimizes circuit component size for battery current monitoring applications, such as in mobile communication products.
• FIG. 1 is a schematic diagram of an exemplary embodiment of a current sensing circuit according to the present invention.
• FIG. 2 is a circuit diagram of an exemplary embodiment of a gainstage for the current sensing circuit shown in FIG. 1;
• FIG. 3 is a circuit diagram of a current sensing circuit according to another exemplary embodiment of the present invention.
• FIG. 4 is a graph illustrating a timing sequence of the current sensing circuit shown in FIG. 3. DETAILED DESCRIPTION
• an apparatus for sensing a current across a known resistor and is well-suited for sensing current output from a battery to monitor battery current in a mobile communication handset.
• the apparatus senses the current output from the battery across the known resistor and outputs an amplified current value to an Analog-to- Digital (A/D) converter for further processing such as battery or charge level indication.
• A/D Analog-to- Digital
• FIG. 1 is a schematic diagram of an exemplary embodiment of a current sensing circuit 10 according to the present invention.
• Current sensing circuit 10 comprises a first gainstage (Gl) 12 having first and second inputs 11, 13 configured to be coupled to first and second references potentials (Vmp, V UIM ) and having first and second outputs, a second gainstage (G2) 14 having first and second inputs 19, 21 coupled, respectively, to outputs 15, 17 of first gainstage 12 and having first and second outputs 23, 25, and a sample and hold (S/H) stage 16 having first and second inputs 27, 29 coupled, respectively, to outputs 23, 25 of second gainstage 14 and having first and second outputs 24, 26.
• Gl first gainstage
• Vmp first and second references potentials
• S/H sample and hold
• the first reference potential (Vi n p) corresponds to the potential at a first terminal of the known resistor (R)
• the second reference potential (Vj nM ) corresponds to the potential at a second terminal of the known resistor (R).
• current sensing circuit 10 further comprises an A/D converter 28 coupled to outputs 24, 26 of S/H stage 16.
• each stage 12, 14, 16 of current sensing circuit 10 is amplifier based (e.g., includes an operational amplifier) to produce an amplified voltage output from an voltage input to the stage.
• First gainstage 12 senses the current (I) across the known resistor (R) from the difference between the first reference potential (V M ") and the second reference potential (Vj nM ) and produces a first amplified voltage output from the first and second reference potentials (Vj nP , Vi nM )-
• Second gainstage 14 further amplifies the first amplified voltage output from first gainstage 12 to produce a second amplified voltage output indicating an amplified value of the current (I) sensed across the known resistor (R).
• the second amplified voltage output is conveniently read by the A/D converter 28.
• S/H stage 16 samples the second amplified voltage output from second gainstage 14 and holds the second amplified voltage output for a predetermined time period (e.g., a specified settling time) sufficient for retrieval by the A/D converter 28. From the sampled values of the second amplified voltage output, a measurement of the relatively low level sensed current (I) may be derived.
• current sensing circuit 10 further comprises a first Common Mode FeedBack circuit (CMFB) 18 coupled across first and second outputs 15, 17 of first gainstage 12, a second CMFB 20 coupled across first and second outputs 23, 25 of second gainstage 14, and a third CMFB 22 coupled across first and second outputs of S/H stage 16.
• CMFBs are commonly used to stabilize the common-mode voltages of differential amplifiers by adjusting the common-mode output currents thereof, as appreciated by those of skill in the art.
• First CMFB 18 stabilizes the common-mode voltages associated with the amplifier in first gainstage 12
• second CMFB 20 stabilizes the common-mode voltages associated with the amplifier in second gainstage 14
• third CMFB 22 stabilize the common-mode voltages associated with the amplifier in S/H stage 16.
• FIG. 2 is a circuit diagram of an exemplary embodiment of a gainstage 30 for use in current sensing circuit 10 shown in FIG. 1.
• Gainstage 30 comprises a first switched capacitor network, an Operational Amplifier (OPAMP) 32 having an input coupled to the first switched capacitor network and having an output, and a second switched capacitor network coupled between the input of OPAMP 32 and the output of the OPAMP 32.
• OPAMP Operational Amplifier
• the input of OPAMP 32 comprises first and second voltage inputs 31, 39 of opposite polarity (e.g., Vi n + , Vj n " ), and the voltage output of OPAMP 32 is coupled to first and second supply voltage inputs 41, 43 of opposite polarity (e.g., supply voltages V + , V " ) of OPAMP 32.
• the first switched capacitor network substantially instantaneously samples the first and second reference potentials (Vj nP , Vj nM ) at the input to gainstage 30 and comprises a pair of two-phase switched capacitors coupled to each of first and second voltage inputs 31, 39 of OPAMP 32.
• Each two-phase switched capacitor is selectively coupled to one of the input potentials (e.g., Vinp, VJ ⁇ M) during one phase and to a common-mode voltage (V cm ) during the other phase based on a pre-determined switching sequence, as described in greater detail hereinafter.
• the common-mode voltage (V cm ) may be any reference potential and is preferably a stable reference potential, such as ground or a band gap potential.
• the first switched capacitor network comprises first and second input capacitors 40, 42 that each have a first electrode coupled to a first voltage input (e.g., Vi n + ) of OPAMP 32, third and fourth input capacitors 44, 46 that each have a first electrode coupled to a second voltage input (e.g., Vi n " ) of OPAMP 32, and first phase switches 48, 49, 52, 53 and second phase switches 47, 50, 51, 54 coupled, respectively, to a second electrode of input capacitors 40, 42, 44, 46.
• a first voltage input e.g., Vi n +
• the second switched capacitor network captures the input potentials received by OPAMP 32 (e.g., Vj nM and Vj n p) for offset cancellation.
• the second switched capacitor network comprises a first feedback capacitor 33 having a first electrode coupled to the first voltage input 31 (e.g., Vj n + ) of OPAMP 32, a second feedback capacitor 36 having a first electrode coupled to the second voltage input 39 (e.g., Vj n " ) of OPAMP 32, a first phase switch 34 coupled to a second electrode of feedback capacitor 33, a second phase switch 35 coupled to the second electrode of feedback capacitor 33, a first phase switch 37 coupled to a second electrode of feedback capacitor 36, and a second phase switch 38 coupled to the second electrode of feedback capacitor 36.
• Using a switched capacitor topology more readily achieves offset cancellation that, if unperformed, would generally degrade the accuracy of any sensed current by OPAMP 32.
• the first and second switched capacitor networks operate using timing phases to open and close switches for initializing and scaling gainstage 30.
• the first switched capacitor network initializes gainstage 30 during a first timing phase ( ⁇ i) for sensing an input potential, such as the reference potentials (Vj nP , Vj nM ), at the input of OPAMP 32 and senses the input potentials (e.g., Vj n P, Vj n M) during a second timing phase ( ⁇ 2 ).
• the second switched capacitor network captures offset voltages that may appear at the input of OPAMP 32.
• the second switched capacitor network is configured to enable scaling by OPAMP 32 of the sensed input potentials (Vj nP , Vim) to produce the first amplified voltage output at an output of gainstage 30 (V 0U tM 5 V ou tp) while canceling the offset voltages.
• first phase switches 48, 52 couple, respectively, input capacitors 40, 44 to V cm
• first phase switch 49 couples input capacitor 42 to Vj nM
• first phase switch 53 couples input capacitor 46 to Vj n p.
• Second phase switches 47, 50, 51, 54 open and close together to sense and remove the common mode at the input potentials (e.g., Vj n p, Vj nM ) so as to allow processing of full scale input voltage differential signals without saturating the amplifier stages.
• second phase switches 50, 54 couple, respectively, the second electrode of input capacitors 42, 46 to V cm> second phase switch 47 couples the second electrode of input capacitor 40 to Vi n p, and second phase switch 51 couples the second electrode of input capacitor 44 to Vj nM - Additionally, first phase switches 48, 49, 52, 53 open during the second timing phase ( ⁇ 2 ).
• an initial configuration of the input potentials (e.g., Vj nM and Vj nP ) is received at the input of OPAMP 32 during the first timing phase ( ⁇ O for initialization and offset cancellation, and an inverted configuration of the input potentials (e.g., Vj nP and VJ ⁇ M) is received at the input of OPAMP 32 during the second timing ⁇ hase( ⁇ 2 ) for common mode removal.
• first phase switches 34, 37 couple, respectively, the second electrode of feedback capacitors 33, 36 to V cm , and feedback capacitors 33, 36 capture any offset voltage appearing at first and second voltage inputs
• first phase switches 34, 37 open during the second timing phase ( ⁇ 2 ) to cancel any offset voltage at voltage inputs 31, 39 of OPAMP 32 (e.g., Vj n + and V in " ) with the captured offset voltages of feedback capacitors 33, 36.
• first phase switches 34, 37 open and close together for offset cancellation of gainstage 30, and second phase switches 35, 38 open and close together for scaling of the input potentials (e.g., Vj n + and Vj n " ) of OPAMP 32.
• gainstage 30 may be implemented in each stage 14, 16 subsequent to first gainstage 12, shown in FIG. 1, such that first and second phase switches 47, 48, 49, 50, 51, 52, 53, 54 open and close in response to later timing phases (e.g., subsequent to the first and second timing phases).
• gainstage 30 may be implemented in second gainstage 14 (FIG. 1) such that third phase switches, corresponding to first phase switches 48, 49, 52, 53 of gainstage 30, and fourth phase switches, corresponding to second phase switches 47, 50, 51, 54 of gainstage 30, of second gainstage 14 (FIG. 1) operate based on a third timing phase ( ⁇ 3 ) and a fourth timing phase ( ⁇ 4 ), respectively.
• the third timing phase ( ⁇ 3 ) and fourth timing phase ( ⁇ 4 ) are preferably initiated after a pre-determined delay following the initiation of the second timing phase ( ⁇ 2 ) for capture of the first and second output (e.g., V 0Ut M and V ou tp) of first gainstage 12 (FIG. 1) by second gainstage 14 (FIG. 1).
• This predetermined delay also provides a time period for initialization of second gainstage 14 (FIG. 1) prior to offset cancellation and scaling by second gainstage 14 (FIG. 1).
• Gainstage 30 may also be implemented in S/H stage 16 (FIG. 1) such that first and second phase switches 47, 48, 49, 50, 51, 52, 53, 54 open and close in response to later timing phases (e.g., subsequent to the third and fourth timing phases).
• sample phase switches corresponding to first phase switches 48, 49, 52, 53 of gainstage 30, of S/H stage 16 (FIG. 1) operate based on a sample timing phase ( ⁇ s), and hold phase switches, corresponding to second phase switches 47, 50, 51, 54 of gainstage 30, of S/H stage 16 (FIG.
• FIG. 3 is a circuit diagram of a current sensing circuit 72 according to another exemplary embodiment of the present invention.
• current sensing circuit 72 senses the current (I) across the known resistor (R) shown in FIG. 1 by double sampling the first and second reference potentials (Vj nP , Vj n M)-
• Current sensing circuit 72 comprises a first gainstage of the type shown in FIG. 2, having an input configured to sample the first and second reference potentials (Vj n P, Vj nM ), a second gainstage 69 having an input coupled to the output of first gainstage 30, and an S/H stage 67 having an input coupled to an output of second gainstage 69.
• Second gainstage 69 re-samples the first and second reference potentials (Vj nP , V J ⁇ M ), sensed at the input of first gainstage 30, to produce the second amplified voltage output at the output of second gainstage 69.
• second gainstage 69 comprises a third switched capacitor network comprising a first gain capacitor 74, a second gain capacitor 76, a third gain capacitor 78, a fourth gain capacitor 80, third phase switches 79, 81, 83, 85 coupled, respectively, to a first electrode of gain capacitors 74, 76, 78, 80, fourth phase switches 73, 77, 82, 84 coupled, respectively, to the first electrode of gain capacitors 74, 76, 78, 80, a fourth phase switch 86 coupled to a second electrode of both of gain capacitors 74, 76, a fourth phase switch 87 coupled to a second electrode of both of gain capacitors 78, 80, a third phase switch 88 coupled to the second electrodes of both of gain capacitors 74, 76, and a third phase switch 89 coupled to the second electrodes of both of gain capacitors 78, 80.
• the third switched capacitor network is configured to perform the second sampling of the reference potentials (Vj nP , V J ⁇ M )
• S/H stage 67 samples the second amplified voltage output from second gainstage 69 and holds the second amplified voltage output for a predetermined time period (e.g., specified settling time) sufficient for retrieval by the A/D converter 28 (FIG. 1).
• S/H stage 67 comprises a first sampling capacitor 90, a second sampling capacitor 91, first and second sampling switches 92, 93 coupled, respectively, to a first electrode of sampling capacitors 90, 91, first and second hold switches 94, 95 coupled, respectively, to the first electrodes of sampling capacitors 90, 91, a third hold switch 96 having a first terminal coupled to a second electrode of first sampling capacitor 90 and having a second terminal coupled to the first voltage input 31 (V; n + ) of OPAMP 32, a fourth hold switch 97 having a first terminal coupled to a second electrode of second sampling capacitor 91 and having a second terminal coupled to the second voltage input 39 (Vj n " ) of OPAMP 32, a fifth hold switch 71 having a first terminal coupled to the second electrode of first feedback capacitor 33 and having a second terminal coupled to the first output 41 (e.g., V 0UtM ) of first gainstage 30, a sixth hold switch 75 having a first terminal coupled to the second electrode of second
• third phase switches 79, 81, 83, 85, 88, 89 open and close together during the third timing phase ( ⁇ 3 ) to cancel offset that may appear at the output of first gainstage 30.
• third phase switches 79, 81 couple, respectively, the first electrodes of gain capacitors 74, 76 to V out p from first gainstage 30
• third phase switches 83, 85 couple, respectively, the first electrodes of gain capacitors 78, 80 to V 0UtM from first gainstage 30
• third phase switches 88, 89 couple, respectively, the second electrodes of gain capacitors 74, 76, 78, 80 to V 0n .
• the fourth phase switches 73, 77, 82, 84 open and close together during the fourth timing phase ( ⁇ 4 ) to sense and scale the input potentials (e.g., V ou tp, V 0UtM )-
• fourth phase switches 82, 84 couple, respectively, the first electrode of gain capacitors 76, 78 to V cm
• fourth phase switch 86 couples the second electrodes of gain capacitors 74, 76 to first voltage output 41 (e.g., V 0UtM ) of OPAMP 32
• fourth phase switch 87 couples the second electrodes of gain capacitors 78, 80 to second voltage output 31 (e.g., Vcutp) of OPAMP 32.
• sampling switches 92, 93 open and close together during the sampling timing phase ( ⁇ $ ).
• first sampling switch 92 couples the first electrode of first sampling capacitor 90 to V ou tp from first gainstage 30
• second sampling switch 93 couples the first electrode of second sampling capacitor 91 to V 0UtM from first gainstage 30.
• S/H stage 67 thus receives the values of V out p and V 0U t M from first gainstage 30 as further amplified by second gainstage 69.
• the second amplified voltage output (e.g., V 0U t P and V 0UtM ) is sampled from second gainstage 69, hold switches 71, 75, 94, 95, 96, 97 open and close together during the hold timing phase ( ⁇ H) to capture the sampled values for retrieval by the A/D converter 28 (FIG. 1).
• first hold switch 94 couples the first electrode of first sampling capacitor 90 to V out p from first gainstage 30
• second hold switch 95 couples the first electrode of second sampling capacitor 91 to V 0UtM from first gainstage
• third hold switch 96 couples the second electrode of first sampling capacitor 90 to first voltage input 31 (e.g., V 1n + ) of OPAMP 32
• fourth hold switch 97 couples the second electrode of second sampling capacitor 91 to second voltage input 39 (e.g., Vj n " ) of OPAMP 32
• fifth hold switch 71 couples the second electrode of first feedback capacitor 33 to first voltage output 41 (e.g., V 0UtM ) of OPAMP 32
• sixth hold switch 75 couples the second electrode of second feedback capacitor 36 to second voltage output 43 (e.g., V 0U t M ) of OPAMP 32.
• sampling switches 92, 93 open to decouple sampling capacitors 90, 91 from V out p and V 0UtM , respectively, during the hold timing phase ( ⁇ H), and S/H stage 67 thereby holds V out p and V 0UtM for capture by the A/D converter 28 (FIG. 1).
• sampling-done switches 98, 99 open and close together during a sampling-done timing phase ( ⁇ s d ) to initialize the current sensing circuit 72 for subsequent sampling.
• first sampling-done switch 98 couples first voltage input 31 (e.g., Vi n + ) of OPAMP 32 to V cm5 and second sampling- done switch 99 couples second voltage input 39 (e.g., Vj n " ) of OPAMP 32 to V cm .
• second gainstage 69 and S/H stage 67 both lack the OPAMPs used in second gainstage 14 (FIG. 1) and S/H stage 16 (FIG. 1) of current sensing circuit 10 (FIG. 1).
• Current sensing circuit 72 lacks the power consumption of OPAMPs in second gainstage 69 and S/H stage 67 while continuing to sense the current (I) across the known resistor (R) and produce an amplified voltage output indicating the current (I).
• FIG. 4 is a graph illustrating an exemplary embodiment of a timing sequence of the current sensing circuit 72 shown in FIG. 3.
• the corresponding switches open in response to a low signal (e.g., about OV) and close in response to a high signal (e.g., about 3V) over time.
• the first timing phase (O 1 ) 60 illustrates a timing sequence of first phase switches 34, 35, 48, 49, 52, 53 (FIG. 3) that initiates at a first time (T 1 ).
• the second timing phase ( ⁇ 2 ) 62 illustrates a timing sequence of second phase switches 36, 38, 47, 50, 51, 54 (FIG.
• First timing phase ( ⁇ O 60 ends at the second time (T 2 ).
• the third timing phase ( ⁇ 3 ) 64 illustrates a timing sequence for third phase switches 79, 81, 83, 85, 88, 89 (FIG. 3) that initiates at a third time (T 3 ) subsequent to the second time (T 2 ).
• the fourth timing phase ( ⁇ 4 ) 66 illustrates a timing sequence for fourth phase switches 73, 77, 82, 84, 86, 87 (FIG. 3) that initiates at a fourth time (T 4 ) subsequent to the third time (T 3 ).
• the third timing phase ( ⁇ 3 ) 64 ends at the fourth time (T 4 ).
• the sampling timing phase ( ⁇ s) 68 illustrates a timing sequence for sampling phase switches 92, 93 (FIG. 3) that initiates at sampling time (Ts).
• Hold timing phase ( ⁇ H ) 70 illustrates a timing sequence for hold phase switches 71, 75, 94, 95, 96, 97 (FIG. 3) that initiates at holding time (T H ).
• the sampling timing phase ( ⁇ s) 68 ends at the holding time (T H ). While the timing sequence is described with respect to current sensing circuit 72 shown in FIG. 3, the timing sequence may also be used with current sensing circuit 10 shown in FTG. 1.
• Each timing phase initiates a function associated with a particular stage of current sensing circuit 72.
• First timing phase ( ⁇ 0 60 initializes first gainstage 30 (FIG. 3) and cancels offset voltages that may appear at the input of OPAMP 32 (FIG. 3).
• Second timing phase ( ⁇ 2 ) 62 samples and scales the input potentials to first gainstage 30 (FIG. 3).
• Third timing phase ( ⁇ 3 ) 64 cancels offset voltages that may appear at the input of second gainstage 69 (FIG. 3) and initializes second gainstage 69 (FIG. 3).
• Fourth timing phase ( ⁇ 4 ) 67 samples and scales the input potentials to second gainstage 69 (FIG. 3).
• Sampling timing phase ( ⁇ s) 68 samples the output from second gainstage 69 (FIG. 3).
• Hold timing phase ( ⁇ H ) 70 holds the sampled output from second gainstage 69 (FIG. 3) for a predetermined time period, such as a time period sufficient for capture by the A/D converter 28 (HG. 1).
• the current sensing circuits of the present invention utilize switched capacitor networks to sense the current across the known resistor with greater accuracy than conventional current sensing circuits. Additionally, using a two-stage gain (e.g., the first and second gainstages) in the current sensing circuits of the present invention decreases capacitor sizes of the switched capacitor networks. The decrease capacitor sizes make these current sensing circuits attractive for implementation in mobile communication products where smaller component size is desirable.
• a circuit for sensing a current comprises a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network.
• the switched capacitor network is configured to sample first and second reference potentials indicating the current.
• the amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.
• a circuit for sensing a current comprises a first gainstage comprising a first switched capacitor network, a second gainstage comprising a second switched capacitor network coupled to the first gainstage, an S/H stage having an input coupled to the output of the second gainstage and having an output, and an A/D converter coupled to the output of the S/H stage.
• the first switched capacitor network is configured to sense first and second reference potentials indicating the current.
• the second gainstage is configured to produce first and second amplified reference potentials from the first and second reference potentials.
• the S/H stage is configured to obtain first and second sampled potentials from the first and second reference potentials for a predetermined time period.
• the A/D converter is configured to receive the first and second sampled potentials from the S/H stage
• a circuit for sensing a current comprises a first switched capacitor network having an output, an amplifier having an input coupled to the output of the first switched capacitor network and having an output, a second switched capacitor network having an input coupled to the output of the amplifier and having an output coupled to the input of the amplifier, and an S/H stage having an input coupled to the output of the amplifier.
• the first switched capacitor network is configured to sample first and second reference potentials indicating the current.
• the amplifier is configured to produce a first amplified potential from the first and second reference potentials.
• the second switched capacitor network is configured to produce a second amplified potential from the first amplified potential.
• the S/H stage is configured to produce a sampled amplified potential from the second amplified potential and hold the sampled amplified potential for a pre-determined time period.

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• Measurement Of Current Or Voltage (AREA)

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• 2005
  • 2005-04-01 US US11/097,593 patent/US7102365B1/en not_active Expired - Lifetime
• 2006
  • 2006-03-15 TW TW095108670A patent/TWI408378B/zh active
  • 2006-03-17 JP JP2008504131A patent/JP5030940B2/ja active Active
  • 2006-03-17 CN CN200680008837A patent/CN100580463C/zh active Active
  • 2006-03-17 WO PCT/US2006/009951 patent/WO2006107572A2/en not_active Ceased
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