WO2006095581A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2006095581A1 WO2006095581A1 PCT/JP2006/303395 JP2006303395W WO2006095581A1 WO 2006095581 A1 WO2006095581 A1 WO 2006095581A1 JP 2006303395 W JP2006303395 W JP 2006303395W WO 2006095581 A1 WO2006095581 A1 WO 2006095581A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- digital
- processing unit
- analog
- reception
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0827—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of electromagnetic or electrostatic field noise, e.g. preventing crosstalk by shielding or optical isolation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B15/00—Suppression or limitation of noise or interference
Definitions
- the present invention relates to a semiconductor device in which a transceiver is formed on one semiconductor substrate.
- Patent Document 1 Japanese Patent Laid-Open No. 2003-37172 (Page 3-5, Fig. 1-2)
- the clock line is shortened by devising the arrangement of the switching circuit to reduce noise mixed in the analog signal.
- the voltage level changes sharply, the same applies to signals (digital data) other than the clock signal input / output in the digital circuit. Therefore, the clock line is not connected to the semiconductor device disclosed in Patent Document 1.
- sufficient effect of noise reduction cannot be obtained only by shortening.
- noise is mixed in the reception processing unit of a receiver that receives and amplifies a weak broadcast wave, the noise is amplified together with the weak broadcast wave, so that the signal quality is greatly reduced.
- the circuit configuration formed on the semiconductor substrate can be arbitrarily determined according to the application and purpose, a transceiver that performs both the reception operation and the transmission operation is formed on the semiconductor substrate.
- a transceiver that performs both the reception operation and the transmission operation is formed on the semiconductor substrate.
- the circuit scale becomes large.
- the circuit scale increases, the area of the semiconductor substrate increases and the material cost increases. Therefore, it is desirable to reduce the circuit scale from the viewpoint of miniaturization and low cost.
- the present invention was created in view of the above points, and an object of the present invention is to provide a semiconductor device capable of preventing signal quality from being deteriorated due to noise and reducing the circuit scale. There is to do.
- a configuration of a transceiver that performs both a reception operation and a transmission operation is formed on a semiconductor substrate. Is partly performed by analog processing and the other part is performed by digital processing, and digital processing corresponding to each of the reception operation and the transmission operation is performed using a common digital processing unit.
- a common digital processing unit As a result, when the function as a transceiver is formed on one semiconductor substrate, both the reception operation and the transmission operation are processed using a common digital processing unit. Therefore, it is possible to reduce the scale of the circuit formed on the semiconductor substrate without having to separately provide a digital processing unit for each part.
- the semiconductor device includes a reception processing unit that performs analog processing corresponding to the above-described reception operation and a transmission processing unit that performs analog processing corresponding to the transmission operation, and is a corner of a semiconductor substrate having a rectangular shape. It is desirable to arrange a reception processing unit in the vicinity of and a digital processing unit in the vicinity of another corner not adjacent to one corner. Alternatively, it includes a reception processing unit that performs analog processing corresponding to the reception operation and a transmission processing unit that performs analog processing corresponding to the transmission operation, and is located near one end of one diagonal line of the semiconductor substrate having a rectangular shape. It is desirable to arrange the reception processing unit and the digital processing unit near the other end.
- the reception processing unit as the front end of a transmitter / receiver performs processing such as extracting weak signals received and amplifying them or converting them into intermediate frequency signals.
- the quality is greatly reduced.
- the digital processing unit, which is the source of noise, and the reception processing unit are arranged on the semiconductor substrate so as to be farthest from each other, thereby reducing noise mixed in the reception processing unit in the reception processing unit.
- Signal quality that is input and output can be greatly improved.
- the reception processing unit described above performs frequency mixing of the reception signal and the first oscillation signal. It is desirable that the number conversion operation is performed and the transmission processing unit performs a modulation operation for modulating the second oscillation signal, and generates the first and second oscillation signals using a common oscillator. As a result, the circuit scale can be reduced by sharing the oscillator.
- a first analog-digital conversion operation that converts an analog signal into digital data corresponding to the reception operation described above and inputs the digital data
- an analog signal converted into digital data corresponding to the transmission operation It is desirable to perform the second analog-digital conversion operation that is converted and input to the digital processing unit, and to perform the first and second analog-digital conversion operations using a common analog-digital converter.
- Two types of analog-to-digital conversion operations required for each reception and transmission operation are performed using a single analog-to-digital converter ⁇ . The scale can be reduced.
- a first digital-analog conversion operation that converts digital data output from the digital processing unit into an analog signal corresponding to the reception operation described above, and an output from the digital processing unit corresponding to the transmission operation It is desirable to perform a second digital-analog conversion operation for converting digital data into an analog signal, and to perform the first and second digital-analog conversion operations using a common digital-analog converter.
- the circuit scale is greater than when a separate digital-to-analog converter is provided. Can be reduced.
- the digital processing unit described above performs a stereo modulation operation for generating stereo composite data from two input data as digital processing corresponding to the transmission operation. This makes it possible to perform a stereo modulation operation without providing a dedicated analog circuit.
- FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment formed on a semiconductor substrate.
- FIG. 2 is a diagram showing a layout of the semiconductor device of the present embodiment.
- FIG. 3 is a diagram showing another layout of the semiconductor device.
- DSP Digital signal processor
- VCO Voltage controlled oscillator
- FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment formed on a semiconductor substrate.
- the semiconductor device of this embodiment includes a reception processing unit 10, analog-to-digital converters (ADCs) 12, 40, a digital signal processing device (DSP) 20, and a digital analog converter (DAC). 30 and 50, a transmission processing unit 52, a voltage controlled oscillator (VCO) 60, a frequency synthesizer 62, an antenna 200, and a crystal resonator 300.
- the semiconductor device constitutes a transceiver.
- each component other than the antenna 200 and the crystal resonator 300 is formed as a one-chip component on the semiconductor substrate 100 using a CMOS process or a MOS process. By using these processes, it is possible to reduce the size and power consumption of a one-chip component formed on the semiconductor substrate 100.
- the configuration of a transceiver that performs both a reception operation and a transmission operation is formed on a semiconductor substrate 100.
- Each of the reception operation and the transmission operation is partly performed by analog processing and the other part is performed by digital processing.
- This digital processing is a digital signal processing device as a common digital processing unit. This is done using 20.
- the reception processing unit 10 performs analog processing corresponding to the reception operation, and transmits a broadcast wave signal received via the antenna 200 (if the modulation signal is similar to the broadcast wave signal, it is transmitted)
- the intermediate frequency signal is output by performing frequency conversion on the transmitter (which may be a broadcasting station or a home transmitter).
- a local oscillator is configured by the voltage controlled oscillator 60, the frequency synthesizer 62, and the crystal oscillator 300, and a local oscillation signal output from the voltage controlled oscillator 60 is input to the reception processing unit 10.
- the reception processing unit 10 is an analog circuit that performs frequency conversion by analog processing, and mixes the frequency of the broadcast wave signal received via the antenna 200 and the local oscillation signal output from the voltage-controlled oscillator 60.
- the reception processing unit 10 includes components as a receiver front end such as a tuning circuit and an RF amplifier.
- the intermediate frequency signal as an analog signal output from the reception processing unit 10 is converted into digital data having a predetermined number of bits by the analog-digital converter 12.
- the digital signal processing device 20 is a digital processing unit that performs digital processing on digital data, and performs a predetermined demodulation operation on the digital data output from the analog-digital converter 12. For example, FM demodulation processing and FM stereo demodulation processing are performed, and the demodulated digital data is converted into an analog signal by the digital / analog converter 30. For example, when an audio signal is considered as an analog signal, the audio signal is amplified and output from a speaker or the like.
- the digital data generated by the demodulation process performed by the digital signal processing device 20 is not limited to audio data. For example, image data may be generated by demodulation processing.
- the digital signal processing device 20 corresponds to the audio signal.
- Predetermined digital processing necessary to transmit the modulated signal is performed. For example, when L data and R data are input as audio data, stereo modulation processing is performed to synthesize these two data. In addition, processing to generate I component and Q component is performed.
- Digital data output from the digital signal processing device 20 is converted into an analog signal by a digital-analog conversion 50.
- the transmission processing unit 52 performs analog modulation processing as analog processing corresponding to the transmission operation.
- the voltage-controlled oscillator 60 is connected to both the reception processing unit 10 and the transmission processing unit 52, and a signal (first oscillation signal) required for the reception operation by the reception processing unit 10 and the transmission processing unit 52 Generates a signal (second oscillation signal) necessary for transmission operation.
- FIG. 2 is a diagram showing a layout of the semiconductor device of the present embodiment.
- the reception processing unit 10 is disposed near one corner of the semiconductor substrate 100 having a rectangular shape, and the other corner not adjacent to the one corner.
- a digital signal processor 20 is arranged in the vicinity.
- the reception processing unit 10 is disposed near one end of one diagonal line of the semiconductor substrate 100 having a rectangular shape, and the digital signal processing device 20 is disposed near the other end.
- the reception processing unit 10 is arranged near the upper left corner of the rectangular shape, and the digital signal processing device 20 is arranged near the lower right corner.
- a transmission processing unit 52 is arranged near the upper right corner, and a frequency synthesizer 62 is arranged near the lower left corner.
- a voltage-controlled oscillator 60 is arranged at approximately the center of the reception processing unit 10 and the transmission processing unit 52 arranged along the upper side of the rectangular shape, and voltage control is performed with each of the reception processing unit 10 and the transmission processing unit 52. This prevents the length of the wiring connecting to the type oscillator 60 from becoming unnecessarily long.
- analog-digital converters 2 and 40 and digital-analog converters 30 and 50 are arranged in a horizontal row in the center of the rectangular shape, and these can be used for reception processing unit 10, transmission processing unit 52, and voltage-controlled oscillator 60. And a circuit group including the digital signal processing device 20 and the frequency synthesizer 62 are separated from each other.
- FIG. 3 is a diagram showing another layout of the semiconductor device.
- the reception processing unit 10 is arranged near the upper left corner of the rectangular shape, and the digital signal processing device 20 is arranged near the lower right corner.
- analog-digital converters 12, 40 and digital-analog converters 30, 50 Force A frequency synthesizer 62 is placed near the lower left corner.
- a voltage controlled oscillator 60 and a transmission processing unit 52 are arranged between the reception processing unit 10 and the frequency synthesizer 62.
- the digital signal processing device 20 that is a noise generation source and the reception processing unit 10 are separated from each other on the semiconductor substrate 100 so as to be mixed into the reception processing unit 10. Noise can be reduced and the signal quality input / output in the reception processing unit 10 can be greatly improved.
- the digital signal processing device for the reception operation and the digital signal processing device for the transmission processing unit are separately provided.
- the scale of the circuit formed on the semiconductor substrate 100 that does not need to be provided can be reduced.
- it is possible to reduce the circuit scale by sharing the voltage-controlled oscillator 60 by using the common voltage-controlled oscillator 60 to generate the oscillation signals necessary for reception and transmission operations.
- the stereo modulation operation can be performed without providing a dedicated analog circuit, and the circuit scale can be further reduced.
- the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention.
- the force described for the case where the two analog-to-digital converters 12 and 40 are separately provided is one common analog-to-digital converter (“common analog-to-digital converter”). May be used to cause these two analog-to-digital converters 12 and 40 to operate.
- the common analog-to-digital converter is used as the analog-to-digital converter 12 when the receiving operation is performed, and the common analog-to-digital converter is converted to an analog-digital converter when the transmitting operation is performed.
- the circuit scale can be reduced by using the common analog-digital converter and the common digital-analog converter. Also, as described above, when the digital signal processing device 20, the voltage controlled oscillator 60, the common analog-digital converter, and the common digital analog conversion ⁇ are shared by the reception operation and the transmission operation, they are provided separately. There is also an effect of reducing power consumption.
- both the reception operation and the transmission operation are processed using a common digital processing unit. There is no need to separately provide a digital processing unit and a digital processing unit for the transmission processing unit, and the scale of the circuit formed on the semiconductor substrate can be reduced.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Theoretical Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Transceivers (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/816,165 US20090028224A1 (en) | 2005-03-10 | 2006-02-24 | Semiconductor device |
EP06714534A EP1858166A1 (en) | 2005-03-10 | 2006-02-24 | Semiconductor device |
JP2007507042A JPWO2006095581A1 (ja) | 2005-03-10 | 2006-02-24 | 半導体装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005-066522 | 2005-03-10 | ||
JP2005066522 | 2005-03-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006095581A1 true WO2006095581A1 (ja) | 2006-09-14 |
Family
ID=36953182
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/303395 WO2006095581A1 (ja) | 2005-03-10 | 2006-02-24 | 半導体装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20090028224A1 (ja) |
EP (1) | EP1858166A1 (ja) |
JP (1) | JPWO2006095581A1 (ja) |
CN (1) | CN101142744A (ja) |
TW (1) | TW200711042A (ja) |
WO (1) | WO2006095581A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019121673A (ja) * | 2018-01-04 | 2019-07-22 | ラピスセミコンダクタ株式会社 | 半導体装置および半導体モジュール |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001516525A (ja) * | 1997-02-05 | 2001-09-25 | テレフオンアクチーボラゲツト エル エム エリクソン | 無線アーキテクチャ |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4943942A (en) * | 1986-09-19 | 1990-07-24 | Advanced Micro Devices | Full-duplex modem using a single processor |
US5857156A (en) * | 1996-04-24 | 1999-01-05 | Anderson; John R. | Personal intercommunication purchase and fulfillment system |
US6373954B1 (en) * | 1997-10-14 | 2002-04-16 | Cirrus Logic, Inc. | Single-chip audio circuitry, method, and systems using the same |
US6058291A (en) * | 1997-12-03 | 2000-05-02 | 3Com Corporation | Methods and apparatus for carrier suppression in a radio modulator |
US7106388B2 (en) * | 1999-12-15 | 2006-09-12 | Broadcom Corporation | Digital IF demodulator for video applications |
US20020090931A1 (en) * | 2001-01-11 | 2002-07-11 | Scott Papineau | Fly - safe operating mode for smart phone |
JP2003037172A (ja) * | 2001-07-23 | 2003-02-07 | Niigata Seimitsu Kk | アナログ・デジタル混載集積回路 |
JP2005175819A (ja) * | 2003-12-10 | 2005-06-30 | Sony Corp | 増幅器並びに通信装置 |
US8112618B2 (en) * | 2004-04-08 | 2012-02-07 | Texas Instruments Incorporated | Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making |
-
2006
- 2006-02-24 CN CNA2006800077469A patent/CN101142744A/zh active Pending
- 2006-02-24 JP JP2007507042A patent/JPWO2006095581A1/ja active Pending
- 2006-02-24 US US11/816,165 patent/US20090028224A1/en not_active Abandoned
- 2006-02-24 WO PCT/JP2006/303395 patent/WO2006095581A1/ja active Application Filing
- 2006-02-24 EP EP06714534A patent/EP1858166A1/en not_active Withdrawn
- 2006-02-27 TW TW095106610A patent/TW200711042A/zh unknown
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001516525A (ja) * | 1997-02-05 | 2001-09-25 | テレフオンアクチーボラゲツト エル エム エリクソン | 無線アーキテクチャ |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019121673A (ja) * | 2018-01-04 | 2019-07-22 | ラピスセミコンダクタ株式会社 | 半導体装置および半導体モジュール |
US11264838B2 (en) | 2018-01-04 | 2022-03-01 | Lapis Semiconductor Co., Ltd. | Semiconductor device and semiconductor module |
JP7115723B2 (ja) | 2018-01-04 | 2022-08-09 | ラピスセミコンダクタ株式会社 | 半導体装置および半導体モジュール |
Also Published As
Publication number | Publication date |
---|---|
EP1858166A1 (en) | 2007-11-21 |
US20090028224A1 (en) | 2009-01-29 |
JPWO2006095581A1 (ja) | 2008-08-14 |
CN101142744A (zh) | 2008-03-12 |
TW200711042A (en) | 2007-03-16 |
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