Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32082—Radio frequency generated discharge
  • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01332—Making the insulator
  • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01332—Making the insulator
  • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
  • H10D64/01338—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the conductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6302—Non-deposition formation processes
  • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6302—Non-deposition formation processes
  • H10P14/6319—Formation by plasma treatments, e.g. plasma oxidation of the substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials

Definitions

• a method of fabricating a gate of a transistor device on a semiconductor substrate includes the steps of forming discrete electrode/insulator layered structures spanning respective source-drain channels regions of the substrate, the layered structures having side walls, and then etching the layered structures to remove oxidation from side walls of the conductive layers of the layered structures .
• a selective re- oxidation step is performed to restore oxide material removed from side walls of the insulator layers of the layered structures during the etching step .
• the re-oxidation step consists of :
• FIG. 3 is a graph qualitatively illustrating the general behavior of contaminant particle count in a gate oxide layer as a function of chamber pressure .
• FIG . 5 is a graph comparing the ion bombardment damage count or density in the gate oxide layer as a function of chamber pressure for the case in which plasma source power is a applied as continuous RF power (the curve labeled ⁇ CW" ) and as pulsed RF power (the curve labeled "pulsed RF" ) .
• FIG . 6. illustrates the time domain waveform of the pulsed RF plasma source power employed in carrying out the invention .
• FIG . 7 is a graph qualitatively illustrating the general behavior of ion bombardment damage count or density in the gate oxide layer as a function of duty cycle of the pulsed RF plasma source power.
• FIG. 10 is a graph of plasma electron energy as a function of chamber pressure for the case of continuous RF source power (the curve labeled "continuous RF") and for the case of pulsed RF plasma source power (the curve labeled "pulsed RF”) .
• FIG. 11 is a graph illustrating plasma ion energy population distributions (population being the vertical axis and ion energy being the horizontal axis ) for three different duty cycles , "10%", “50%” and "100%” .
• FIG . 12 is a graph illustrating plasma ion energy population distributions (population being the vertical axis and ion energy being the horizontal axis ) for three relatively short duty cycles , "5%”, “10%” and “20%”, showing a much more favorable energy distribution .
• FIG . 13 is a graph illustrating plasma ion energy population distributions (population being the vertical axis and ion energy being the horizontal axis ) for three different chamber pressures , "10 mT” ( solid line) , “20 mT” (dashed line) and “40 mT” (dotted line) .
• the reactor further includes a wafer support pedestal 26, which may be an electrostatic chuck, for holding a semiconductor wafer 27 , a gas inj ection system 28 and a vacuum pump 30 coupled to the interior of the chamber .
• the gas inj ection system 28 is supplied by a process gas source, such as an oxygen container 32.
• the wafer support pedestal 26 includes heating apparatus such as a dual radial zone heater 34 having radially inner and outer heating elements 34a, 34b beneath the top surface of the wafer support pedestal .
• the chamber pressure is controlled by a throttle valve 38 of the vacuum pump 30.
• the duty cycle of the pulsed RF power output at the gate 22 is controlled by controlling the duty cycle of a pulse generator 36 whose output is coupled to the gate 22. Plasma is generated in an ion generation region 39 corresponding to a volume under the ceiling 14 surrounded by the coil antenna 16.
• the silicon dioxide structure in the gate oxide layer 40 has defects 50 giving rise to incomplete or dangling bonds , then the electric fields associated with those dangling bonds can perturb the flow of charge carriers , thereby impeding device performance .
• This deleterious effect is noticeable at a defect density (Dit) in the gate oxide layer greater than 5xl0 10 cm ⁇ 2 . eV ⁇ 1 , where a single defect corresponds to a dangling bond or interface trap quantum states .
• the defect density Dit is defined relative to an energy level (eV) because individual trap levels (defects ) cannot be distinguished experimentally and the summation over all interface trap levels can be replaced by an integral .
• the density function Dit (s) is defined as the probability per unit area that an interface trap level is present with energy (in eV) between an energy s and an energy s+delta s . This definition is discussed by E . H . Nicollian and J. R. Brews , MOS (Metal Oxide Semiconductor) Physics and Technology, John Wiley and Sons , 1982 , at pp . 191-193.
• the gate electrode 48 may consist entirely of polysilicon .
• the gate electrode may be a stacked structure as shown in FIG . 2A including a polysilicon base layer 48a, a tungsten nitride diffusion barrier layer 48b and a tungsten layer 48c .
• a further problem with plasma processes for growing the silicon dioxide gate insulator layer 40 is that plasma processing typically produces a non-uniform thickness distribution of the gate insulator layer 40, typically having a variance of about 1.04% across the wafer surface .
• contamination-induced defects are eliminated by reducing the chamber pressure to very low levels (on the order of 10 ⁇ iT) .
• ion bombardment-induced defects that would be expected at such a low chamber pressure levels are prevented by using a quasi- remote plasma source and pulsing the RF plasma source power (using a pulsed RF power source) .
• reducing the pulsed RF plasma source duty cycle reduces the density of defects believed to be formed by ion bombardment damage in the silicon dioxide layer .
• pulsing the plasma source power provides a surprisingly uniform distribution of thickness of the gate insulator layer 40 , which solves the problem of non-uniform oxide formation in the plasma process .
• the "off" time T F is defined by a pulse frequency between about 2 and 20 kHz and an "on" duty cycle between about 5% and 20% .
• the ion generation region-to-wafer distance L D is on the order of about 2cm or 3cr ⁇ .
• the ion generation region-to-wafer distance L D can be about the same as (or greater than) the distance V D x T F traveled by the plasma ions during a single ⁇ off" time of the pulsed RF power waveform.
• an operating window for the process of the invention illustrated in FIG. 14 shows possible pairs of chamber pressure and duty cycle values that produce the highest quality gate insulator layer in an oxidation process .
• the width of the process window depends upon the permissible defect density in the gate oxide layer that is formed during the process of the invention .
• the tungsten oxide film 60 must be removed.
• An oxide etch process is therefore performed to remove the tungsten oxide layer 60.
• this oxide etch process also attacks the silicon dioxide gate insulator layer 40 , removing material from the gate insulator layer 40 near the bottom of the gate 48 , giving it a slightly concave shape defining a recess 40a, as shown in FIG . 2C .
• a conductive gate electrode is deposited over the insulating layer (block 122 of FIG. 15) .

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Plasma & Fusion (AREA)
• Chemical & Material Sciences (AREA)
• Analytical Chemistry (AREA)
• Formation Of Insulating Films (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)

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Publications (2)

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• 2005
  • 2005-02-02 US US11/050,471 patent/US7141514B2/en not_active Expired - Lifetime
• 2006
  • 2006-01-30 JP JP2007554154A patent/JP5172352B2/ja not_active Expired - Fee Related
  • 2006-01-30 KR KR1020077017554A patent/KR20070097558A/ko not_active Abandoned
  • 2006-01-30 WO PCT/US2006/003250 patent/WO2006083778A2/en not_active Ceased
  • 2006-01-30 EP EP06719894A patent/EP1851795A4/en not_active Withdrawn

Non-Patent Citations (1)

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