WO2006080082A1 - 積層型半導体装置用キャリア及び積層型半導体装置の製造方法 - Google Patents
積層型半導体装置用キャリア及び積層型半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2006080082A1 WO2006080082A1 PCT/JP2005/001247 JP2005001247W WO2006080082A1 WO 2006080082 A1 WO2006080082 A1 WO 2006080082A1 JP 2005001247 W JP2005001247 W JP 2005001247W WO 2006080082 A1 WO2006080082 A1 WO 2006080082A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- carrier
- groove
- stacked
- stacked semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
Definitions
- the present invention relates to a carrier for a stacked semiconductor device and a method for manufacturing the stacked semiconductor device.
- CSP chip scale package
- MCP packages
- PoP stacked packages
- FIG. 1 is a view showing a conventional carrier for a stacked semiconductor device (hereinafter referred to as a carrier), where (a) shows a side view of the carrier and (b) shows a top view of the carrier.
- This carrier 1 is used in the manufacture of laminated semiconductor devices.
- the carrier 1 includes a storage portion 2 that stores a plurality of stacked semiconductor devices 4 and a guide portion 3 that guides the semiconductor devices 4.
- a laminated semiconductor device is manufactured through a reflow process in which hot air is applied to stacked semiconductor devices to heat them and the semiconductor devices are connected to each other and a cleaning process in which liquid is used for cleaning.
- the present invention has been made in view of the above problems, and provides a carrier for a stacked semiconductor device and a method for manufacturing the stacked semiconductor device that can improve manufacturing yield or cleaning effect. Objective.
- the present invention provides a storage unit that stores a plurality of stacked semiconductor devices, a guide unit that guides the semiconductor device, and the storage unit from the side of the semiconductor device. And a groove for guiding a gas or liquid to the stacked semiconductor device carrier.
- a first groove that guides gas or liquid from the side surface side of the semiconductor device to the housing portion it is possible to make it easier to pass hot air in the reflow process and cleaning liquid in the cleaning process. Improvements in yield and cleaning effect can be expected.
- the present invention is a carrier for a stacked semiconductor device, further including a hole provided in a corner of the storage portion. According to the present invention, by introducing the gas from the lower side of the storage portion, heat is transmitted to the semiconductor device, and there is an effect of reducing the bonding failure of the stacked connection portion of the semiconductor device.
- the present invention is the carrier for a stacked semiconductor device, further including a second groove that connects between the holes provided in the adjacent storage portions among the holes.
- the present invention is the carrier for the stacked semiconductor device, further including a third groove that connects the hole to the outside on the peripheral side of the carrier for the stacked semiconductor device.
- the present invention is the carrier for the stacked semiconductor device, further including a hole provided in the groove and connecting the groove to the outside on the lower surface side of the carrier for the stacked semiconductor device.
- the groove is formed corresponding to each side of the semiconductor device.
- gas or liquid can be guided to each side of the semiconductor device.
- the first and third grooves are formed deeper than the upper surface of the lowest semiconductor device to be stacked. With this configuration, heat can be transmitted over a wide range to the joint portion of the semiconductor device when the hot air reflow is passed, and the cleaning liquid becomes easier to pass in the cleaning process. Improvement of the purification effect can be expected.
- the upper surface of the lowermost semiconductor device to be stacked is a surface connected to the semiconductor device stacked on the semiconductor device.
- the first groove is formed such that at least a part of the connection terminal located at the end of the semiconductor device is exposed to the outside of the carrier for the stacked semiconductor device.
- the first groove is formed to be wider toward the outside from the storage portion. This
- the guide portion is formed at a height higher than that of the uppermost semiconductor device to be stacked.
- the guide portion is formed at a position corresponding to at least two of the plurality of corner portions of the semiconductor device.
- the storage portion, the guide portion, and the first groove are preferably formed of a single member.
- the present invention provides a first semiconductor device and a first semiconductor device in the housing portion of the carrier for a stacked semiconductor device, including a housing portion that houses a plurality of stacked semiconductor devices and a guide portion that guides the semiconductor device.
- a step of bonding the second semiconductor device to the stacked semiconductor device According to the present invention, an improvement in manufacturing yield can be expected.
- the present invention is a method for manufacturing a stacked semiconductor device, further comprising a step of cleaning a junction between the first semiconductor device and the second semiconductor device via the groove. According to the present invention, an improvement in cleaning effect can be expected.
- the invention's effect it is possible to provide a carrier for a stacked semiconductor device and a method for manufacturing a stacked semiconductor device that can improve the manufacturing yield or the cleaning effect.
- FIG. 1 is a view showing a conventional carrier for a stacked semiconductor device.
- FIG. 2 is a view showing a carrier for a stacked semiconductor device according to the present invention.
- FIG. 3 is a cross-sectional view of a carrier for a stacked semiconductor device of the present invention.
- FIG. 4 (a) is a top view of the carrier for a stacked semiconductor device of the present invention, (b) is a front view, and (c) is an enlarged view of a main part.
- FIG. 5 is a view showing another configuration of the carrier for a stacked semiconductor device of the present invention.
- FIG. 6 is a top view showing another configuration of the carrier for a stacked semiconductor device of the present invention.
- FIG. 7 is a view showing another configuration of the carrier for a stacked semiconductor device of the present invention.
- FIG. 8 is a view showing another configuration of the carrier for a stacked semiconductor device of the present invention.
- FIG. 9 is a view showing another configuration of the laminated semiconductor carrier of the present invention.
- FIG. 2A and 2B are diagrams showing a stacked semiconductor device carrier according to the present invention.
- FIG. 2A is a side view of the carrier
- FIG. 2B is a top view of the carrier.
- the carrier 10 includes a storage portion 11 that stores a plurality of stacked semiconductor devices 4, a guide portion 12-12 that guides the periphery of the semiconductor device 4,
- a groove (first groove) 13 to 13 for guiding a gas or liquid as a fluid from the side surface side of the semiconductor device 4 to the storage portion 11 is included. From the direction of the arrow
- the groove 13 is preferably formed corresponding to each side of the semiconductor device 4.
- Fig. 2 four storage units are shown, but an actual carrier has a larger number of storage units.
- the grooves 13-13 are provided on the side surface of the storage portion 11 so that gas or liquid can easily pass therethrough.
- the carrier 10 is formed as a single piece by a manufacturing method such as cutting out from a metal plate, forging or forging. It is preferably formed as a structure.
- a manufacturing method such as cutting out from a metal plate, forging or forging.
- PCT / JP20 04/012476 and PCT / JP2004 / 006265 by the same applicant as this application, it consisted of parts with several strengths. By forming it as an integral structure, it is possible to suppress variations in assembly accuracy when manufacturing the carrier. In addition, the rigidity is higher than that of the divided structure, and the possibility of carrier breakage can be reduced in the assembly process of the laminated semiconductor device.
- FIG. 3A is a cross-sectional view taken along the line AA ′ of FIG. 2, and FIG. 3B is an enlarged view of a main part.
- the uppermost semiconductor device 41 is stacked on the lowermost semiconductor device 42.
- Connection terminals (solder balls) 43 are provided on the lower surfaces of the semiconductor devices 41 and 42.
- An electrode pad (not shown) to which the connection terminal 43 of the semiconductor device 41 is connected is provided on the upper surface of the substrate of the semiconductor device 42. Hot air is sent from the opening under the groove 13 and the lowermost semiconductor device 42 by reflow heating, and the connection terminal 43 is melted to manufacture the stacked semiconductor device.
- the semiconductor device 41 is a logic device and the semiconductor device 42 is a memory device such as a flash memory
- a stacked semiconductor device in which a logic device and a memory device are stacked is manufactured.
- the groove 13 is formed deeper than the upper surface B of the lowermost semiconductor device 42 to be stacked (reference number C). For this reason, heat can be transferred to a wide range of the junctions of the semiconductor devices 41 and 42 when the hot air reflow is passed, and the cleaning liquid can be more easily passed in the cleaning process, so that the manufacturing yield and the cleaning effect are improved. I can expect.
- FIG. 4A is a top view of the carrier 10 for a stacked semiconductor device according to the present invention
- FIG. 4B is a front view
- FIG. 4C is an enlarged view of a main part.
- the semiconductor device 4 is stored in the storage portion 11 of the carrier 10.
- FIGS. 4B and 4C when viewed from the side surface P of the carrier 10, at least a part of the connection terminal (solder ball) 43 at the end of the semiconductor device 4 is exposed in the groove 13. It is formed to do.
- FIG. 5 is a diagram showing a part of another configuration of the carrier for a stacked semiconductor device of the present invention.
- FIG. 4A is a view corresponding to the BB ′ cross-sectional view of FIG. 2, and FIG.
- the stacked semiconductor device including the semiconductor devices 41 and 42 is stored in the storage unit 11 of the carrier 20.
- the stacked semiconductor device is simply joined by stacking the semiconductor devices 41 and 42. Therefore, the semiconductor devices 41 and 42 are displaced or detached between the stacking process and the end of the reflow process. For this reason, as shown in FIG. 5, by forming the guide portion 12 at a height higher than the uppermost semiconductor device 41 to be stacked (reference symbols D and E), the stacking during transport between processes is performed. Stacking misalignment of the type semiconductor device can be prevented.
- FIG. 6 is a top view showing another configuration of the carrier for the stacked semiconductor device of the present invention.
- the carrier 30 includes a storage portion 11 that stores a plurality of stacked semiconductor devices 4, a guide portion 12-12 that guides the periphery of the semiconductor device, and a side surface of the semiconductor device 4.
- the hole 14 penetrates to the back side of the carrier 20. Hole 14 is circular
- the corners of the semiconductor device Since the temperature is transmitted to the corners of the semiconductor device by connecting to the outside of the peripheral side of the carrier 30 for the semiconductor device, the corners of the semiconductor device that occurred when the semiconductor device was passed through hot air reflow Connection failure can be reduced.
- FIG. 7 is a diagram showing another configuration of the carrier for a stacked semiconductor device of the present invention.
- the carrier 40 includes a storage unit 11 that stores a plurality of stacked semiconductor devices 4, a guide unit 32 32 that guides two of the four corners of the semiconductor device 4, and a semiconductor.
- the guide part is formed at a position corresponding to at least two corners of the corner of the semiconductor device 4. It needs to be made.
- FIG. 8 is a view showing another configuration of the carrier for a stacked semiconductor device of the present invention.
- FIG. 4A shows an example in which the groove 13 is formed at an angle of 90 ° with respect to the side surface of the semiconductor device.
- FIG. 2B shows an example in which the groove is formed at an angle of 45 ° with respect to the side surface of the semiconductor device.
- Reference numeral 50 denotes a carrier
- 502 denotes a guide portion
- 503 denotes a groove.
- FIG. 5B by forming the groove 503 so as to have an outward force as viewed from the storage portion 11, it is possible to improve the flow of hot air during the reflow process and the cleaning liquid during the cleaning process.
- by reducing the deposition of the carrier itself it is possible to suppress the heat capacity of the carrier in the reflow process and to melt the solder at the junction of the semiconductor device at a low temperature in the reflow furnace.
- FIG. 9 is a view showing another configuration of the stacked semiconductor carrier of the present invention.
- the carrier 60 is provided on the side surface of the storage unit 11, a storage unit 11 that stores a plurality of stacked semiconductor devices 4, a guide unit 12-12 that guides the periphery of the semiconductor device 4. Groove provided 1
- groove 13-13 provided in groove 13-13 connect groove 13-13 to the outside on the underside of carrier 60
- Hole ⁇ 61—61 is the groove 13—13 force to the bottom surface of carrier 60
- the carrier 60 is actually formed with a plurality of storage portions in the same manner as described with reference to FIG. To facilitate passage of gas or liquid into the grooves 13-13 on the side of the storage 11
- a first semiconductor device 41 and a second semiconductor device 42 are provided in the storage portion 11 of the carrier 10 for a stacked semiconductor device, which includes a storage portion 11 that stores a plurality of stacked semiconductor devices and a guide portion 12 that guides the semiconductor device. And the step of bonding the first semiconductor device 41 and the second semiconductor device 42 by reflowing through the groove 13 for guiding the side force gas of the storage portion 11 and the groove 13. And a step of cleaning the junction between the first semiconductor device 41 and the second semiconductor device. This can be expected to improve manufacturing yields and cleaning effects.
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Description
Claims
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007500394A JP4675955B2 (ja) | 2005-01-28 | 2005-01-28 | 積層型半導体装置用キャリア及び積層型半導体装置の製造方法 |
| PCT/JP2005/001247 WO2006080082A1 (ja) | 2005-01-28 | 2005-01-28 | 積層型半導体装置用キャリア及び積層型半導体装置の製造方法 |
| US11/341,984 US7414305B2 (en) | 2005-01-28 | 2006-01-27 | Carrier for stacked type semiconductor device and method of fabricating stacked type semiconductor devices |
| TW095103430A TWI392079B (zh) | 2005-01-28 | 2006-01-27 | 堆疊型半導體裝置用載體及製造堆疊型半導體裝置的方法 |
| US12/166,293 US7846771B2 (en) | 2005-01-28 | 2008-07-01 | Carrier for stacked type semiconductor device and method of fabricating stacked type semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2005/001247 WO2006080082A1 (ja) | 2005-01-28 | 2005-01-28 | 積層型半導体装置用キャリア及び積層型半導体装置の製造方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/341,984 Continuation US7414305B2 (en) | 2005-01-28 | 2006-01-27 | Carrier for stacked type semiconductor device and method of fabricating stacked type semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2006080082A1 true WO2006080082A1 (ja) | 2006-08-03 |
Family
ID=36740117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2005/001247 Ceased WO2006080082A1 (ja) | 2005-01-28 | 2005-01-28 | 積層型半導体装置用キャリア及び積層型半導体装置の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US7414305B2 (ja) |
| JP (1) | JP4675955B2 (ja) |
| TW (1) | TWI392079B (ja) |
| WO (1) | WO2006080082A1 (ja) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9093563B2 (en) | 2013-07-11 | 2015-07-28 | International Business Machines Corporation | Electronic module assembly with patterned adhesive array |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000216333A (ja) * | 1999-01-20 | 2000-08-04 | Hyundai Electronics Ind Co Ltd | 積層半導体パッケ―ジ及びその製造方法、並びに積層半導体パッケ―ジ製造用アライニングジグ |
| JP2001223297A (ja) * | 1999-11-30 | 2001-08-17 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法及び半導体装置の積層方法 |
| JP2001274319A (ja) * | 2000-03-28 | 2001-10-05 | Rohm Co Ltd | 半導体装置およびその製造方法 |
| JP2001352035A (ja) * | 2000-06-07 | 2001-12-21 | Sony Corp | 多層半導体装置の組立治具及び多層半導体装置の製造方法 |
| JP2005005529A (ja) * | 2003-06-12 | 2005-01-06 | Toshiba Corp | 三次元実装半導体モジュール及び三次元実装半導体システム |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09159369A (ja) * | 1995-12-05 | 1997-06-20 | Kokusai Denki Erutetsuku:Kk | 熱処理炉 |
| JP2987101B2 (ja) * | 1996-04-15 | 1999-12-06 | 株式会社ニッシン | 半導体装置の接続方法並びに半導体装置の接続器 |
| DE112004002858T5 (de) * | 2004-05-11 | 2007-04-19 | Spansion Llc, Sunnyvale | Träger für eine Stapel-Halbleitervorrichtung und Verfahren zum Herstellen derselben |
| JP4613367B2 (ja) * | 2004-08-30 | 2011-01-19 | スパンション エルエルシー | 積層型半導体装置用キャリア構成、この製造方法及び積層型半導体装置の製造方法 |
| WO2006080351A1 (ja) * | 2005-01-25 | 2006-08-03 | Matsushita Electric Industrial Co., Ltd. | 半導体装置およびその製造方法 |
-
2005
- 2005-01-28 WO PCT/JP2005/001247 patent/WO2006080082A1/ja not_active Ceased
- 2005-01-28 JP JP2007500394A patent/JP4675955B2/ja not_active Expired - Fee Related
-
2006
- 2006-01-27 US US11/341,984 patent/US7414305B2/en not_active Expired - Fee Related
- 2006-01-27 TW TW095103430A patent/TWI392079B/zh not_active IP Right Cessation
-
2008
- 2008-07-01 US US12/166,293 patent/US7846771B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000216333A (ja) * | 1999-01-20 | 2000-08-04 | Hyundai Electronics Ind Co Ltd | 積層半導体パッケ―ジ及びその製造方法、並びに積層半導体パッケ―ジ製造用アライニングジグ |
| JP2001223297A (ja) * | 1999-11-30 | 2001-08-17 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法及び半導体装置の積層方法 |
| JP2001274319A (ja) * | 2000-03-28 | 2001-10-05 | Rohm Co Ltd | 半導体装置およびその製造方法 |
| JP2001352035A (ja) * | 2000-06-07 | 2001-12-21 | Sony Corp | 多層半導体装置の組立治具及び多層半導体装置の製造方法 |
| JP2005005529A (ja) * | 2003-06-12 | 2005-01-06 | Toshiba Corp | 三次元実装半導体モジュール及び三次元実装半導体システム |
Also Published As
| Publication number | Publication date |
|---|---|
| US7414305B2 (en) | 2008-08-19 |
| JPWO2006080082A1 (ja) | 2008-06-19 |
| TWI392079B (zh) | 2013-04-01 |
| TW200644215A (en) | 2006-12-16 |
| US20060245908A1 (en) | 2006-11-02 |
| US7846771B2 (en) | 2010-12-07 |
| US20080274591A1 (en) | 2008-11-06 |
| JP4675955B2 (ja) | 2011-04-27 |
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