WO2006072979A1 - Transistor semi-conducteur - Google Patents

Transistor semi-conducteur Download PDF

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Publication number
WO2006072979A1
WO2006072979A1 PCT/JP2005/000036 JP2005000036W WO2006072979A1 WO 2006072979 A1 WO2006072979 A1 WO 2006072979A1 JP 2005000036 W JP2005000036 W JP 2005000036W WO 2006072979 A1 WO2006072979 A1 WO 2006072979A1
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WO
WIPO (PCT)
Prior art keywords
transistor
pad
semiconductor transistor
source
cells
Prior art date
Application number
PCT/JP2005/000036
Other languages
English (en)
Japanese (ja)
Inventor
Kazuhiro Iyomasa
Koji Yamanaka
Masatoshi Nakayama
Tadashi Takagi
Hiroshi Ohtsuka
Tetsuo Kunii
Makoto Matsunaga
Yukinobu Tarui
Original Assignee
Mitsubishi Denki Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Denki Kabushiki Kaisha filed Critical Mitsubishi Denki Kabushiki Kaisha
Priority to PCT/JP2005/000036 priority Critical patent/WO2006072979A1/fr
Publication of WO2006072979A1 publication Critical patent/WO2006072979A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Definitions

  • the present invention relates to a microwave high-power semiconductor transistor used as a high-power amplifier for a terrestrial microwave, a millimeter-wave communication device, a mobile communication device, a satellite communication device, a radar device, etc.
  • the present invention relates to a semiconductor transistor that suppresses stable operation.
  • High-frequency high-power transistors include a structure in which a plurality of transistor cells (hereinafter referred to as “cells” as appropriate) are connected in parallel.
  • the high-power transistor chip includes a drain electrode and a source electrode. Comb transistors that are alternately arranged in a comb shape are used.
  • the source electrode is connected to the source pad via an air wiring called an air bridge, and further connected to the back electrode of the semi-insulating GaAs substrate by a via hole.
  • an air wiring called an air bridge
  • 12 gate fingers constitute one transistor cell, and one gate pad is provided for the 12 gate fingers.
  • Each gate finger is supplied with power through a gate bus.
  • all cells were connected by a gate bus! /, And! /.
  • the high-frequency, high-power transistors connected in parallel may oscillate when a DC voltage is applied or when a high-frequency signal is input.
  • the signals from the transistors connected in parallel are not synthesized with the same amplitude and phase because of the uneven electrical characteristics between the transistors connected in parallel. It is said that oscillation occurs when there is gain in the potential difference loop of the signal (see Non-Patent Document 1, for example).
  • Patent Document 1 Japanese Patent Application Laid-Open No. 11 103072
  • Non-Patent Document 1 Ito, Takagi, "Basics and Applications of MMIC Technology", Realize, 1996, pp. 1
  • Non-Patent Document 2 T.TAKAGI, at el., "Analysis of High Power Amplifier Instability due to fo / 2 Loop Oscillation, IEICE Trans on Electron. E78- C [8], pp. 936-943 (March 1995)
  • the present invention has been made to solve the above-described problems, and the signal of each cell force is not synthesized with the same amplitude and in-phase due to the non-uniformity of the characteristics and impedance between the cells. It is an object of the present invention to obtain a semiconductor transistor capable of suppressing the oscillation phenomenon caused by applying DC voltage or inputting a high frequency signal.
  • a plurality of drain electrodes and a plurality of source electrodes are alternately arranged in a comb shape via transistor cell force gate fingers arranged in parallel, and adjacent transistor cells.
  • a source pad is provided between the drain pads, and this source pad is connected to the source pad on the gate pad side to electrically isolate the transistor cells from each other.
  • FIG. 1 is a configuration diagram illustrating a semiconductor transistor according to a first embodiment of the present invention.
  • FIG. 2 is a configuration diagram showing a semiconductor transistor according to a second embodiment of the present invention.
  • FIG. 3 is a configuration diagram showing a semiconductor transistor according to a third embodiment of the present invention.
  • FIG. 4 is a configuration diagram showing a semiconductor transistor according to a fourth embodiment of the present invention.
  • FIG. 5 is a configuration diagram showing a semiconductor transistor according to a fifth embodiment of the present invention.
  • FIG. 6 is a configuration diagram showing a semiconductor transistor according to a sixth embodiment of the present invention.
  • FIG. 7 is a configuration diagram showing a semiconductor transistor according to a seventh embodiment of the present invention.
  • FIG. 8 is a configuration diagram showing a semiconductor transistor according to an eighth embodiment of the present invention.
  • FIG. 9 is a configuration diagram showing a semiconductor transistor according to a ninth embodiment of the present invention.
  • FIG. 10 is a configuration diagram showing a semiconductor transistor according to Embodiment 10 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a configuration diagram of a semiconductor transistor according to Embodiment 1 of the present invention.
  • the semiconductor transistor according to the first embodiment is an example in which four transistor cells constitute one transistor chip, and the transistor cells are connected in parallel to obtain high output. And
  • the semiconductor transistor of the first embodiment is a comb transistor in which the drain electrode 1 and the source electrode 2 are alternately arranged in a comb shape. Further, the source electrode 2 is connected to the source pad 4 through an air wiring called an air bridge 3.
  • gate fingers (gate electrodes) 5 constitute one transistor cell.
  • One gate pad 6 is provided for the 12 gate fingers 5.
  • Seven drain electrodes 1 are drawn from one drain pad 8 per cell, and three source electrodes 2 are drawn from one source pad 4 per cell. And The drain electrode 1 and the source electrode 2 are alternately arranged facing each other across the gate finger 5.
  • the gate finger 5 is configured to be supplied with power through the gate bus 7. Further, the source electrode 2 is connected to the source pad 4 via the air wiring called the air bridge 3 as described above so as not to contact the gate bus 7.
  • a source pad 4 is provided between a drain pad 8 provided in a cell and a drain pad 8 of an adjacent cell, and the source pad is arranged on the gate pad 6 side.
  • the wiring from 4 is configured to be connected to the source pad 4 provided between the drain pads 8 described above.
  • the drain electrode 1 and the drain pad 8 are formed on a semi-insulating substrate (semiconductor substrate) 9 made of GaAs or the like.
  • each cell is separated by a wiring between source pads on the gate side and the drain side in units of one cell (hereinafter referred to as one block) It is characterized by constituting a transistor chip. That is, with such a configuration, the cells are electrically separated from each other.
  • the transistor cells are connected to a gate bus.
  • a plurality of striped drain electrodes connected to the drain pad via a plurality of striped gate electrodes and a plurality of striped source electrodes connected to the source pad provided on the gate bus side are comb-shaped. So that the transistor cells are electrically separated from each other by providing source pads between the drain pads of adjacent transistor cells and connecting the source pads to the source pads on the gate bus side.
  • the conventional state of the transistor is such that the electrical state of each cell does not affect other cells.
  • the loop circuit is eliminated arising among the cells in the transistor chip, there is an effect that can lower the possibility of oscillation occurring between transistor cells.
  • each cell is electrically separated, there is an effect that oscillation can be prevented by providing an isolation resistor in an external circuit. In this way, it is possible to suppress the instability caused by the unbalance operation between cells as described in the problem, and to further improve the operation stability of the transistor. Also, an isolation resistor is added to the external circuit. By providing, the above-described transistor chip reliability problem can be avoided.
  • on-wafer evaluation can be performed for each cell, and transistors with uniform characteristics can be found between the cells. For this reason, it is possible to find a transistor that can provide a desired output with a small unbalance between cells.
  • FIG. 2 is a configuration diagram of a semiconductor transistor according to the second embodiment of the present invention.
  • the semiconductor transistor of the second embodiment is composed of the drain electrode 1 and the semi-insulating substrate 9, and the definition of the function of each component in the figure is the same as that of the first embodiment.
  • the arrangement of the gate electrode and the drain electrode in each cell, such as the comb-shaped portion, is the same as in the first embodiment.
  • the semiconductor transistor according to the second embodiment has two cells as a unit (the case where the number of cells per block is two is shown as an embodiment), and the source pad 4 on the gate side and the drain side 4
  • the semiconductor transistor is characterized in that a transistor chip is formed by electrically separating cells from each other by wiring therebetween.
  • the same configuration as in the first embodiment has an effect of reducing the possibility of oscillation occurring between the transistor cells, and If you increase the number of cells per block in advance, it will not oscillate! If you know that it is! /, You can use multiple cells per block as in this Embodiment 2.
  • the number of wiring between the source pads between the cells and the source pads arranged on the drain side is reduced. This has the effect of reducing the size of the transistor chip.
  • FIG. 3 is a configuration diagram of a semiconductor transistor according to the third embodiment of the present invention.
  • the semiconductor transistor of the third embodiment is composed of the drain electrode 1 and the semi-insulating substrate 9, and the definition of the function of each component in the figure is the same as that of the first embodiment.
  • the arrangement of the comb-shaped portion of the gate electrode and the drain electrode in each cell is the same as in the first embodiment. Take as an example.
  • the gate bus 7 and the drain pad 8 are cut in units of two cells. In the enlarged portion (circular portion) in the figure, the gate bus 7 being cut is shown, and therefore the air bridge 3 of the source electrode 2 is omitted, and only the gate bus 7 and the gate finger 5 are shown.
  • 10 gate fingers 5 fed via the gate bus 7 constitute one transistor cell, and one gate pad is provided for the 10 gate fingers 5. 6 is provided. Further, five drain electrodes 1 are drawn from one drain pad 8 per cell, and three source electrodes 2 are drawn from one source pad 4 per cell. The drain electrode 1 and the source electrode 2 are alternately arranged opposite to each other across the gate finger 5.
  • the cells are electrically isolated by cutting the gate bus 7 and the drain pad 8 in units of two cells.
  • the transistor cells are connected to a gate bus.
  • a plurality of striped drain electrodes connected to the drain pad via a plurality of striped gate electrodes and a plurality of striped source electrodes connected to the source pad provided on the gate bus side are comb-shaped.
  • one or more transistor cells are used as a unit, and at least one of the gate bus or drain pad between adjacent transistor cells is cut to electrically isolate the transistor cells from each other. As a result, the electrical state of each cell does not affect other cells. There is an effect that can lower the gel the possibility of oscillation occurring between Ranjisutaseru.
  • the gate bus is disconnected in accordance with conditions such as the impedance of the matching circuit connected to the transistor and the high-frequency signal input to the gate electrode.
  • FIG. 4 is a configuration diagram of a semiconductor transistor according to the fourth embodiment of the present invention.
  • the drain pad 8 is all connected.
  • the cell is electrically isolated by cutting the gate bus 7 in units of one cell, and the transistor chip is separated. It is a semiconductor transistor characterized by comprising. Note that the enlarged portion (circular portion) in the figure represents the gate bus 7 that has been cut, so the air bridge 3 of the source electrode 2 is omitted, and only the gate bus 7 and the gate finger 5 are shown! .
  • the gate bus between adjacent transistor cells is cut in units of one or more transistor cells to electrically isolate the transistor cells from each other.
  • the possibility of oscillation occurring between transistor cells in which the electrical state of each cell does not affect other cells can be reduced.
  • the drain pad 8 since the drain pad 8 is not cut and is continuous, the degree of freedom for wire bonding is increased, and there is an advantage in mounting.
  • FIG. 5 is a configuration diagram of a semiconductor transistor according to the fifth embodiment of the present invention.
  • the gate buses 7 are connected, but the cell is electrically isolated by cutting the drain pad 8 in units of one cell, thereby forming a transistor chip.
  • This is a semiconductor transistor.
  • the number of force cells is not necessarily one, as an example where one cell is used as a unit.
  • the drain pad 8 between adjacent transistor cells is cut in units of one or more transistor cells to electrically isolate the transistor cells. As a result, it is possible to reduce the possibility of oscillation occurring between transistor cells in which the electrical state of each cell does not affect other cells.
  • FIG. 6 is a configuration diagram of a semiconductor transistor according to the sixth embodiment of the present invention.
  • the semiconductor transistor of the sixth embodiment is composed of a drain electrode 1 and a single metal wire 10, and the definitions relating to the functions of the components in the figure are the same as those of the first embodiment except for the metal wire 10. Further, the arrangement of the comb-shaped portion including the gate finger 5 and the drain electrode 1 in each cell is the same as that in the first embodiment.
  • the semiconductor transistor according to the sixth embodiment is provided with the metal wire 10 connected to the ground from the source pad 4 on the gate pad 6 side and the drain pad 8 side in the semiconductor transistor of the first embodiment.
  • the force is shown in which the source pad 4 on both the gate pad 6 side and the drain pad 8 side is connected to the ground. Even if the metal wire is connected to only one side of the source pad 4 good.
  • At least one of the part on the gate bus side or the part on the drain pad side in the source pad is connected to the ground. Since it has a metal wire, it has the effect of operating stably as a source-grounded semiconductor transistor.
  • FIG. 7 is a configuration diagram of a semiconductor transistor according to the seventh embodiment of the present invention.
  • the semiconductor transistor of the seventh embodiment is composed of a drain electrode 1 and one metal wire 10, and the definition of the functions of each component in the figure is the same as in the first embodiment except for the metal wire 10.
  • the arrangement of the comb-shaped portion including the gate finger 5 and the drain electrode 1 in each cell is the same as that of the third embodiment.
  • the semiconductor transistor according to the seventh embodiment is characterized in that the semiconductor wire of the third embodiment is provided with a metal wire 10 connected to the ground on the source pad 4 on the gate pad 6 side. It is a semiconductor transistor.
  • the semiconductor transistor of the seventh embodiment since the metal wire for connecting to the source pad force ground is provided, it is possible to stably operate as a source grounded type semiconductor transistor. There is.
  • FIG. 8 is a configuration diagram of a semiconductor transistor according to the eighth embodiment of the present invention.
  • the semiconductor transistor of the eighth embodiment is composed of one drain electrode 1 and a via hole 11. Except for the via hole 11, the definition of the function of each component in the figure is the same as that of the first embodiment. In addition, the arrangement of the gate fingers 5 and the comb-shaped portions of the drain electrode 1 in each cell is the same as that in the first embodiment.
  • the semiconductor transistor in the eighth embodiment is the same as the semiconductor transistor in the first embodiment.
  • the semiconductor transistor is characterized in that the source pad 4 on the gate pad 6 side has a via hole 11 connected to the ground.
  • the source transistor is stably operated as a grounded source type semiconductor transistor.
  • the inductance component between the source and the ground can be reduced as compared with the case where the metal wire is wired from the source node to the ground. Since the amount of feedback is reduced, there is an effect of higher frequency, higher gain, and higher output.
  • FIG. 9 is a configuration diagram of a semiconductor transistor according to the ninth embodiment of the present invention.
  • the semiconductor transistor of the ninth embodiment is composed of one drain electrode 1 and a via hole 11. Except for the via hole 11, the definition of the function of each component in the figure is the same as that of the first embodiment. In addition, the arrangement of the comb-shaped portions of the gate electrode and the drain electrode in each cell is the same as that of the second embodiment.
  • the semiconductor transistor in the ninth embodiment includes the via hole 11 connected to the ground in the source pad 4 on the gate pad 6 side and the drain pad 8 side in the semiconductor transistor in the second embodiment.
  • the semiconductor transistor of the ninth embodiment since the via hole for connecting to the ground is provided in the source pad, there is an effect that the semiconductor transistor operates stably as a source-grounded semiconductor transistor, Compared to the case of the eighth embodiment, since the number of via holes is large, there is an effect that the inductance component between the source and the ground can be further reduced.
  • FIG. 10 is a configuration diagram of a semiconductor transistor according to the tenth embodiment of the present invention.
  • the semiconductor transistor of the tenth embodiment includes a drain electrode 1 and a via hole 11. Except for the via hole 11, the definition of the function of each component in the figure is the same as that of the first embodiment.
  • the arrangement of the gate fingers 5 and the comb-shaped portion of the drain electrode 1 in each cell is The same thing as Embodiment 3 is mentioned as an example.
  • the semiconductor transistor according to the tenth embodiment has the via hole 11 connected to the ground in the source pad 4 on the gate pad 6 side in the semiconductor transistor according to the third embodiment. It is.
  • the semiconductor transistor of the tenth embodiment since the via hole for connecting to the ground is provided in the source pad, there is an effect that the semiconductor transistor operates stably as a grounded source type semiconductor transistor.
  • the semiconductor transistor of Embodiment 10 when the semiconductor transistor of Embodiment 10 is applied to a semiconductor amplifier, the inductance component between the source and ground can be reduced and the amount of feedback can be reduced as compared with the case where the metal wire is wired from the source pad to the ground. Therefore, there are effects of high frequency, high gain, and high output.
  • the force applied to the third embodiment is used, and the semiconductor transistor shown in the fourth and fifth embodiments is used to similarly connect the source pad and the ground with a via hole. Thus, the same effect can be obtained.
  • the semiconductor transistor according to the present invention suppresses oscillation in a semiconductor transistor in which a plurality of transistor cells are arranged in parallel on a semiconductor substrate, and is suitable for use in a high-power amplifier or the like. .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Selon l’invention des cellules de transistor disposées en parallèle sont formées en configurant une pluralité d’électrodes de drain (1) et une pluralité d’électrodes de source (2), qui sont connectées à un patin de source (4) disposé sur un côté d’un patin de grille (6), pour qu’elles se trouvent face à face de manière alternée en forme alvéolaire, à travers une pluralité de doigts de grille (5). Les patins de source (4) sont disposés entre des patins de drain (8) des cellules de transistor adjacentes, le patin de source (4) est connecté au patin de source (4) sur le côté du patin de grille (6), et les cellules de transistor sont isolées électriquement l’une de l’autre.
PCT/JP2005/000036 2005-01-05 2005-01-05 Transistor semi-conducteur WO2006072979A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/000036 WO2006072979A1 (fr) 2005-01-05 2005-01-05 Transistor semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/000036 WO2006072979A1 (fr) 2005-01-05 2005-01-05 Transistor semi-conducteur

Publications (1)

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WO2006072979A1 true WO2006072979A1 (fr) 2006-07-13

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6481501A (en) * 1987-09-24 1989-03-27 Mitsubishi Electric Corp Microwave semiconductor switch
JPH10233404A (ja) * 1997-02-21 1998-09-02 Mitsubishi Electric Corp 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6481501A (en) * 1987-09-24 1989-03-27 Mitsubishi Electric Corp Microwave semiconductor switch
JPH10233404A (ja) * 1997-02-21 1998-09-02 Mitsubishi Electric Corp 半導体装置

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