WO2006072979A1

WO2006072979A1 - Semiconductor transistor

Info

Publication number: WO2006072979A1
Application number: PCT/JP2005/000036
Authority: WO
Inventors: Kazuhiro Iyomasa; Koji Yamanaka; Masatoshi Nakayama; Tadashi Takagi; Hiroshi Ohtsuka; Tetsuo Kunii; Makoto Matsunaga; Yukinobu Tarui
Original assignee: Mitsubishi Denki Kabushiki Kaisha
Priority date: 2005-01-05
Filing date: 2005-01-05
Publication date: 2006-07-13

Abstract

Transistor cells arranged in parallel are formed by arranging a plurality of drain electrodes (1) and a plurality of source electrodes (2), which are connected to a source pad (4) provided on a side of a gate pad (6), to alternately face in comb-shape, through a plurality of gate fingers (5). The source pads (4) are provided between drain pads (8) of the adjacent transistor cells, the source pad (4) is connected to the source pad (4) on the side of the gate pad (6), and the transistor cells are electrically isolated from each other.

Description

Specification

Semiconductor transistor technology

TECHNICAL FIELD [0001] The present invention relates to a microwave high-power semiconductor transistor used as a high-power amplifier for a terrestrial microwave, a millimeter-wave communication device, a mobile communication device, a satellite communication device, a radar device, etc. The present invention relates to a semiconductor transistor that suppresses stable operation.

Background art

[0002] Conventional high-frequency high-power transistors include a structure in which a plurality of transistor cells (hereinafter referred to as “cells” as appropriate) are connected in parallel. The high-power transistor chip includes a drain electrode and a source electrode. Comb transistors that are alternately arranged in a comb shape are used.

[0003] In addition, the source electrode is connected to the source pad via an air wiring called an air bridge, and further connected to the back electrode of the semi-insulating GaAs substrate by a via hole. Conventionally, for example, 12 gate fingers constitute one transistor cell, and one gate pad is provided for the 12 gate fingers. Each gate finger is supplied with power through a gate bus. In addition, all cells were connected by a gate bus! /, And! /.

[0004] By the way, the high-frequency, high-power transistors connected in parallel may oscillate when a DC voltage is applied or when a high-frequency signal is input. As for the oscillation mechanism, the signals from the transistors connected in parallel are not synthesized with the same amplitude and phase because of the uneven electrical characteristics between the transistors connected in parallel. It is said that oscillation occurs when there is gain in the potential difference loop of the signal (see Non-Patent Document 1, for example).

[0005] When the transistor oscillates, there is a problem that the operation of the transistor becomes unstable because the signal is not output or an unnecessary signal is amplified, and the synthesis efficiency is remarkably reduced. Therefore, the signals of the transistors connected in parallel are of equal amplitude, As a countermeasure against oscillation that occurs when they are not synthesized well in the same phase, an isolation resistor is mounted so that the gate terminals are connected in close proximity to the gate terminals of the transistors connected in parallel, and the potential difference that occurs during non-uniform operation is isolated. There is a method of reducing the resistance with the resistance (for example, see Non-Patent Document 2).

[0006] In addition, there is a semiconductor device in which an isolation resistor is provided between a gate bus or a drain pad between cells in order to suppress an oscillation phenomenon that occurs in a transistor chip by using the above-described method for suppressing the oscillation phenomenon of a transistor. (For example, see Patent Document 1).

Patent Document 1: Japanese Patent Application Laid-Open No. 11 103072

Non-Patent Document 1: Ito, Takagi, "Basics and Applications of MMIC Technology", Realize, 1996, pp. 1

60-164

Non-Patent Document 2: T.TAKAGI, at el., "Analysis of High Power Amplifier Instability due to fo / 2 Loop Oscillation, IEICE Trans on Electron. E78- C [8], pp. 936-943 (August 1995)

However, in such a conventional semiconductor device, there are problems such as a complicated process for providing an isolation resistor. In addition, since the isolation resistance is provided inside the transistor chip, the physical resistance of the isolation resistor itself is small, so there is a limit to the withstand power, and it is difficult to realize a large withstand power. There was a problem.

[0009] The present invention has been made to solve the above-described problems, and the signal of each cell force is not synthesized with the same amplitude and in-phase due to the non-uniformity of the characteristics and impedance between the cells. It is an object of the present invention to obtain a semiconductor transistor capable of suppressing the oscillation phenomenon caused by applying DC voltage or inputting a high frequency signal.

Disclosure of the invention

[0010] In the semiconductor transistor according to the present invention, a plurality of drain electrodes and a plurality of source electrodes are alternately arranged in a comb shape via transistor cell force gate fingers arranged in parallel, and adjacent transistor cells. A source pad is provided between the drain pads, and this source pad is connected to the source pad on the gate pad side to electrically isolate the transistor cells from each other. [0011] This has the effect of reducing the possibility of oscillation occurring between transistor cells, where the electrical state of each cell does not affect other cells. Brief Description of Drawings

FIG. 1 is a configuration diagram illustrating a semiconductor transistor according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a semiconductor transistor according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a semiconductor transistor according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram showing a semiconductor transistor according to a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram showing a semiconductor transistor according to a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram showing a semiconductor transistor according to a sixth embodiment of the present invention.

FIG. 7 is a configuration diagram showing a semiconductor transistor according to a seventh embodiment of the present invention.

FIG. 8 is a configuration diagram showing a semiconductor transistor according to an eighth embodiment of the present invention.

FIG. 9 is a configuration diagram showing a semiconductor transistor according to a ninth embodiment of the present invention.

FIG. 10 is a configuration diagram showing a semiconductor transistor according to Embodiment 10 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, in order to describe the present invention in more detail, the best mode for carrying out the present invention will be described with reference to the accompanying drawings.

Embodiment 1.

FIG. 1 is a configuration diagram of a semiconductor transistor according to Embodiment 1 of the present invention.

[0014] The semiconductor transistor according to the first embodiment is an example in which four transistor cells constitute one transistor chip, and the transistor cells are connected in parallel to obtain high output. And

[0015] The semiconductor transistor of the first embodiment is a comb transistor in which the drain electrode 1 and the source electrode 2 are alternately arranged in a comb shape. Further, the source electrode 2 is connected to the source pad 4 through an air wiring called an air bridge 3.

[0016] Also, 12 gate fingers (gate electrodes) 5 constitute one transistor cell.

One gate pad 6 is provided for the 12 gate fingers 5.

[0017] Seven drain electrodes 1 are drawn from one drain pad 8 per cell, and three source electrodes 2 are drawn from one source pad 4 per cell. And The drain electrode 1 and the source electrode 2 are alternately arranged facing each other across the gate finger 5. The gate finger 5 is configured to be supplied with power through the gate bus 7. Further, the source electrode 2 is connected to the source pad 4 via the air wiring called the air bridge 3 as described above so as not to contact the gate bus 7.

[0018] In addition, with one cell as a unit, a source pad 4 is provided between a drain pad 8 provided in a cell and a drain pad 8 of an adjacent cell, and the source pad is arranged on the gate pad 6 side. The wiring from 4 is configured to be connected to the source pad 4 provided between the drain pads 8 described above. The drain electrode 1 and the drain pad 8 are formed on a semi-insulating substrate (semiconductor substrate) 9 made of GaAs or the like.

In the semiconductor transistor according to the first embodiment, each cell is separated by a wiring between source pads on the gate side and the drain side in units of one cell (hereinafter referred to as one block) It is characterized by constituting a transistor chip. That is, with such a configuration, the cells are electrically separated from each other.

As described above, according to the semiconductor transistor of the first embodiment, in a semiconductor transistor in which a plurality of transistor cells are arranged in parallel on a semiconductor substrate, the transistor cells are connected to a gate bus. A plurality of striped drain electrodes connected to the drain pad via a plurality of striped gate electrodes and a plurality of striped source electrodes connected to the source pad provided on the gate bus side are comb-shaped. So that the transistor cells are electrically separated from each other by providing source pads between the drain pads of adjacent transistor cells and connecting the source pads to the source pads on the gate bus side. As a result, the conventional state of the transistor is such that the electrical state of each cell does not affect other cells. Compared to, since the loop circuit is eliminated arising among the cells in the transistor chip, there is an effect that can lower the possibility of oscillation occurring between transistor cells.

[0021] Further, since each cell is electrically separated, there is an effect that oscillation can be prevented by providing an isolation resistor in an external circuit. In this way, it is possible to suppress the instability caused by the unbalance operation between cells as described in the problem, and to further improve the operation stability of the transistor. Also, an isolation resistor is added to the external circuit. By providing, the above-described transistor chip reliability problem can be avoided.

In the first embodiment, on-wafer evaluation can be performed for each cell, and transistors with uniform characteristics can be found between the cells. For this reason, it is possible to find a transistor that can provide a desired output with a small unbalance between cells.

[0023] Embodiment 2.

FIG. 2 is a configuration diagram of a semiconductor transistor according to the second embodiment of the present invention. The semiconductor transistor of the second embodiment is composed of the drain electrode 1 and the semi-insulating substrate 9, and the definition of the function of each component in the figure is the same as that of the first embodiment. In addition, the arrangement of the gate electrode and the drain electrode in each cell, such as the comb-shaped portion, is the same as in the first embodiment.

[0024] The semiconductor transistor according to the second embodiment has two cells as a unit (the case where the number of cells per block is two is shown as an embodiment), and the source pad 4 on the gate side and the drain side 4 The semiconductor transistor is characterized in that a transistor chip is formed by electrically separating cells from each other by wiring therebetween.

As apparent from the above, according to the second embodiment, the same configuration as in the first embodiment has an effect of reducing the possibility of oscillation occurring between the transistor cells, and If you increase the number of cells per block in advance, it will not oscillate! If you know that it is! /, You can use multiple cells per block as in this Embodiment 2. By configuring, compared to the first embodiment, the number of wiring between the source pads between the cells and the source pads arranged on the drain side is reduced. This has the effect of reducing the size of the transistor chip.

Embodiment 3.

FIG. 3 is a configuration diagram of a semiconductor transistor according to the third embodiment of the present invention. The semiconductor transistor of the third embodiment is composed of the drain electrode 1 and the semi-insulating substrate 9, and the definition of the function of each component in the figure is the same as that of the first embodiment. In addition, the arrangement of the comb-shaped portion of the gate electrode and the drain electrode in each cell is the same as in the first embodiment. Take as an example.

In the semiconductor transistor according to the third embodiment, four transistor cells constitute one transistor chip, and these transistor cells are connected in parallel to obtain a high output. In the third embodiment, the gate bus 7 and the drain pad 8 are cut in units of two cells. In the enlarged portion (circular portion) in the figure, the gate bus 7 being cut is shown, and therefore the air bridge 3 of the source electrode 2 is omitted, and only the gate bus 7 and the gate finger 5 are shown.

In the third embodiment, 10 gate fingers 5 fed via the gate bus 7 constitute one transistor cell, and one gate pad is provided for the 10 gate fingers 5. 6 is provided. Further, five drain electrodes 1 are drawn from one drain pad 8 per cell, and three source electrodes 2 are drawn from one source pad 4 per cell. The drain electrode 1 and the source electrode 2 are alternately arranged opposite to each other across the gate finger 5.

In the semiconductor transistor according to the third embodiment, the cells are electrically isolated by cutting the gate bus 7 and the drain pad 8 in units of two cells.

Also, here, the power given by taking the case of two cells as an example. If the number of cells in each block is the same, the number of cells need not be two.

As described above, according to the semiconductor transistor of the third embodiment, in a semiconductor transistor in which a plurality of transistor cells are arranged in parallel on a semiconductor substrate, the transistor cells are connected to a gate bus. A plurality of striped drain electrodes connected to the drain pad via a plurality of striped gate electrodes and a plurality of striped source electrodes connected to the source pad provided on the gate bus side are comb-shaped. In addition, one or more transistor cells are used as a unit, and at least one of the gate bus or drain pad between adjacent transistor cells is cut to electrically isolate the transistor cells from each other. As a result, the electrical state of each cell does not affect other cells. There is an effect that can lower the gel the possibility of oscillation occurring between Ranjisutaseru. In addition, the gate bus is disconnected in accordance with conditions such as the impedance of the matching circuit connected to the transistor and the high-frequency signal input to the gate electrode. By selecting whether the drain pad to be cut is to be cut, there is an effect that the isolation state of the transistor can be surely ensured.

[0031] Embodiment 4.

FIG. 4 is a configuration diagram of a semiconductor transistor according to the fourth embodiment of the present invention.

In FIG. 4, the definitions of symbols in the figure are the same as those in the first embodiment. Further, the arrangement of the comb-shaped portion composed of the gate finger 5 and the drain electrode 1 in each cell is taken as an example similar to the third embodiment.

[0032] In the semiconductor transistor according to the fourth embodiment, the drain pad 8 is all connected. The cell is electrically isolated by cutting the gate bus 7 in units of one cell, and the transistor chip is separated. It is a semiconductor transistor characterized by comprising. Note that the enlarged portion (circular portion) in the figure represents the gate bus 7 that has been cut, so the air bridge 3 of the source electrode 2 is omitted, and only the gate bus 7 and the gate finger 5 are shown! .

Also, here is an example of the case where one cell is used as a unit. If the number of cells in each block is the same, the number of cells need not be one.

As described above, according to the semiconductor transistor of the fourth embodiment, the gate bus between adjacent transistor cells is cut in units of one or more transistor cells to electrically isolate the transistor cells from each other. As a result, there is an effect that the possibility of oscillation occurring between transistor cells in which the electrical state of each cell does not affect other cells can be reduced. In the fourth embodiment, since the drain pad 8 is not cut and is continuous, the degree of freedom for wire bonding is increased, and there is an advantage in mounting.

[0034] Embodiment 5.

FIG. 5 is a configuration diagram of a semiconductor transistor according to the fifth embodiment of the present invention.

In FIG. 5, the definitions of symbols in the figure are the same as those in the first embodiment. Further, the arrangement of the comb-shaped portion composed of the gate finger 5 and the drain electrode 1 in each cell is taken as an example similar to the third embodiment.

In the semiconductor transistor according to the fifth embodiment, all the gate buses 7 are connected, but the cell is electrically isolated by cutting the drain pad 8 in units of one cell, thereby forming a transistor chip. This is a semiconductor transistor. Also, here, the number of force cells is not necessarily one, as an example where one cell is used as a unit.

As described above, according to the semiconductor transistor of the fifth embodiment, the drain pad 8 between adjacent transistor cells is cut in units of one or more transistor cells to electrically isolate the transistor cells. As a result, it is possible to reduce the possibility of oscillation occurring between transistor cells in which the electrical state of each cell does not affect other cells.

[0036] Embodiment 6.

FIG. 6 is a configuration diagram of a semiconductor transistor according to the sixth embodiment of the present invention.

The semiconductor transistor of the sixth embodiment is composed of a drain electrode 1 and a single metal wire 10, and the definitions relating to the functions of the components in the figure are the same as those of the first embodiment except for the metal wire 10. Further, the arrangement of the comb-shaped portion including the gate finger 5 and the drain electrode 1 in each cell is the same as that in the first embodiment.

[0037] The semiconductor transistor according to the sixth embodiment is provided with the metal wire 10 connected to the ground from the source pad 4 on the gate pad 6 side and the drain pad 8 side in the semiconductor transistor of the first embodiment. The semiconductor transistor characterized by the above.

[0038] In this example, the force is shown in which the source pad 4 on both the gate pad 6 side and the drain pad 8 side is connected to the ground. Even if the metal wire is connected to only one side of the source pad 4 good.

As described above, according to the semiconductor transistor of the sixth embodiment, at least one of the part on the gate bus side or the part on the drain pad side in the source pad is connected to the ground. Since it has a metal wire, it has the effect of operating stably as a source-grounded semiconductor transistor.

[0040] In addition, in the semiconductor transistors described in the first and second embodiments, even when the via hole process cannot be applied, there is an effect that the semiconductor transistor can be applied as a common source semiconductor transistor.

[0041] Further, when the semiconductor transistor of the sixth embodiment is applied to a semiconductor amplifier, the metal from both the source pads 4 arranged on the gate pad 6 side and the drain pad 8 side to the ground. By wiring wire 10, compared to the case where only the source pad 4 on one side is also wired

Since the inductance component between the source and ground can be reduced and the amount of feedback is reduced, there is an effect that high frequency, high gain, and high output can be achieved.

[0042] Embodiment 7.

FIG. 7 is a configuration diagram of a semiconductor transistor according to the seventh embodiment of the present invention.

The semiconductor transistor of the seventh embodiment is composed of a drain electrode 1 and one metal wire 10, and the definition of the functions of each component in the figure is the same as in the first embodiment except for the metal wire 10.

. In addition, the arrangement of the comb-shaped portion including the gate finger 5 and the drain electrode 1 in each cell is the same as that of the third embodiment.

The semiconductor transistor according to the seventh embodiment is characterized in that the semiconductor wire of the third embodiment is provided with a metal wire 10 connected to the ground on the source pad 4 on the gate pad 6 side. It is a semiconductor transistor.

As described above, according to the semiconductor transistor of the seventh embodiment, since the metal wire for connecting to the source pad force ground is provided, it is possible to stably operate as a source grounded type semiconductor transistor. There is.

[0045] In addition, in the semiconductor transistor described in Embodiment 3, when the via hole process is not applicable, there is an effect that the semiconductor transistor can be applied as a common source type semiconductor transistor.

[0046] Here, the force described in the case of applying to the third embodiment is used. Similarly, using the semiconductor transistor shown in the fourth embodiment and the fifth embodiment, a metal wire is connected between the source pad and the ground. By doing so, the same effect can be obtained.

[0047] Embodiment 8.

FIG. 8 is a configuration diagram of a semiconductor transistor according to the eighth embodiment of the present invention.

The semiconductor transistor of the eighth embodiment is composed of one drain electrode 1 and a via hole 11. Except for the via hole 11, the definition of the function of each component in the figure is the same as that of the first embodiment. In addition, the arrangement of the gate fingers 5 and the comb-shaped portions of the drain electrode 1 in each cell is the same as that in the first embodiment.

That is, the semiconductor transistor in the eighth embodiment is the same as the semiconductor transistor in the first embodiment. The semiconductor transistor is characterized in that the source pad 4 on the gate pad 6 side has a via hole 11 connected to the ground.

As described above, according to the eighth embodiment, since the via hole for connecting to the ground is provided on the source pad, there is an effect that the source transistor is stably operated as a grounded source type semiconductor transistor.

[0050] When the semiconductor transistor of Embodiment 8 is applied to a semiconductor amplifier, the inductance component between the source and the ground can be reduced as compared with the case where the metal wire is wired from the source node to the ground. Since the amount of feedback is reduced, there is an effect of higher frequency, higher gain, and higher output.

[0051] Embodiment 9.

FIG. 9 is a configuration diagram of a semiconductor transistor according to the ninth embodiment of the present invention.

The semiconductor transistor of the ninth embodiment is composed of one drain electrode 1 and a via hole 11. Except for the via hole 11, the definition of the function of each component in the figure is the same as that of the first embodiment. In addition, the arrangement of the comb-shaped portions of the gate electrode and the drain electrode in each cell is the same as that of the second embodiment.

That is, the semiconductor transistor in the ninth embodiment includes the via hole 11 connected to the ground in the source pad 4 on the gate pad 6 side and the drain pad 8 side in the semiconductor transistor in the second embodiment. This is a semiconductor transistor.

As described above, according to the semiconductor transistor of the ninth embodiment, since the via hole for connecting to the ground is provided in the source pad, there is an effect that the semiconductor transistor operates stably as a source-grounded semiconductor transistor, Compared to the case of the eighth embodiment, since the number of via holes is large, there is an effect that the inductance component between the source and the ground can be further reduced.

[0054] Embodiment 10.

FIG. 10 is a configuration diagram of a semiconductor transistor according to the tenth embodiment of the present invention. The semiconductor transistor of the tenth embodiment includes a drain electrode 1 and a via hole 11. Except for the via hole 11, the definition of the function of each component in the figure is the same as that of the first embodiment. The arrangement of the gate fingers 5 and the comb-shaped portion of the drain electrode 1 in each cell is The same thing as Embodiment 3 is mentioned as an example.

That is, the semiconductor transistor according to the tenth embodiment has the via hole 11 connected to the ground in the source pad 4 on the gate pad 6 side in the semiconductor transistor according to the third embodiment. It is.

As described above, according to the semiconductor transistor of the tenth embodiment, since the via hole for connecting to the ground is provided in the source pad, there is an effect that the semiconductor transistor operates stably as a grounded source type semiconductor transistor. In addition, when the semiconductor transistor of Embodiment 10 is applied to a semiconductor amplifier, the inductance component between the source and ground can be reduced and the amount of feedback can be reduced as compared with the case where the metal wire is wired from the source pad to the ground. Therefore, there are effects of high frequency, high gain, and high output.

Note that here, the force applied to the third embodiment is used, and the semiconductor transistor shown in the fourth and fifth embodiments is used to similarly connect the source pad and the ground with a via hole. Thus, the same effect can be obtained.

Industrial applicability

[0058] As described above, the semiconductor transistor according to the present invention suppresses oscillation in a semiconductor transistor in which a plurality of transistor cells are arranged in parallel on a semiconductor substrate, and is suitable for use in a high-power amplifier or the like. .

Claims

The scope of the claims

[1] In a semiconductor transistor in which a plurality of transistor cells are arranged in parallel on a semiconductor substrate,

The transistor cell is connected to a plurality of striped drain electrodes connected to a drain pad and a source pad provided on the gate bus side via a plurality of striped gate electrodes connected to a gate bus. A plurality of striped source electrodes are alternately arranged opposite to each other in a comb shape.

A semiconductor transistor in which a source pad is provided between the drain pads of adjacent transistor cells, and the source pad is connected to the source pad on the gate bus side to electrically isolate the transistor cells.

[2] In a semiconductor transistor in which a plurality of transistor cells are arranged in parallel on a semiconductor substrate,

The transistor cell is connected to a plurality of striped drain electrodes connected to a drain pad and a source pad provided on the gate bus side via a plurality of striped gate electrodes connected to a gate bus. A plurality of striped source electrodes are alternately arranged opposite to each other in a comb shape, and

A semiconductor transistor in which at least one of a gate bus and a drain pad between adjacent transistor cells is cut in units of one or more of the transistor cells to electrically isolate the transistor cells.

[3] The metal wire for connecting to at least one partial force ground of the gate pad side portion or the drain pad side portion of the source pad is provided. Semiconductor transistor.

[4] The semiconductor transistor according to claim 2, further comprising a metal wire for connecting the source pad to the ground.

[5] The semiconductor transistor according to claim 1, wherein a via hole for connecting to the ground is provided in the source pad.

[6] The semiconductor transistor according to claim 2, wherein a via hole for connecting to the ground is provided in the source pad.