WO2006072871A3 - Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees - Google Patents

Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees Download PDF

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Publication number
WO2006072871A3
WO2006072871A3 PCT/IB2005/054432 IB2005054432W WO2006072871A3 WO 2006072871 A3 WO2006072871 A3 WO 2006072871A3 IB 2005054432 W IB2005054432 W IB 2005054432W WO 2006072871 A3 WO2006072871 A3 WO 2006072871A3
Authority
WO
WIPO (PCT)
Prior art keywords
areas
localised
electrical conducting
stacked structures
vertical electrical
Prior art date
Application number
PCT/IB2005/054432
Other languages
English (en)
Other versions
WO2006072871A2 (fr
Inventor
Hubert Moriceau
Franck Fournel
Christophe Morales
Original Assignee
Commissariat Energie Atomique
Hubert Moriceau
Franck Fournel
Christophe Morales
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique, Hubert Moriceau, Franck Fournel, Christophe Morales filed Critical Commissariat Energie Atomique
Priority to EP05850920A priority Critical patent/EP1797588A2/fr
Priority to US11/576,743 priority patent/US7781300B2/en
Priority to JP2007535322A priority patent/JP5329808B2/ja
Publication of WO2006072871A2 publication Critical patent/WO2006072871A2/fr
Publication of WO2006072871A3 publication Critical patent/WO2006072871A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de réalisation d'une structure semi-conductrice, comportant : - la formation contrôlée, à travers un masque (31), dans un premier substrat (30) en un matériau semi-conducteur, d' au moins une première zone en un matériau isolant (36), jusqu'au niveau de la surface inférieure (35) du masque, avant ou pendant le retrait du masque.
PCT/IB2005/054432 2004-10-06 2005-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees WO2006072871A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP05850920A EP1797588A2 (fr) 2004-10-06 2005-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees
US11/576,743 US7781300B2 (en) 2004-10-06 2005-10-06 Method for producing mixed stacked structures, different insulating areas and/or localised vertical electrical conducting areas
JP2007535322A JP5329808B2 (ja) 2004-10-06 2005-10-06 様々な絶縁領域及び／又は局所的な垂直導電領域を有する混合積層構造物を製造する方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR04/52284 2004-10-06
FR0452284A FR2876220B1 (fr) 2004-10-06 2004-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.

Publications (2)

Publication Number Publication Date
WO2006072871A2 WO2006072871A2 (fr) 2006-07-13
WO2006072871A3 true WO2006072871A3 (fr) 2006-11-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/054432 WO2006072871A2 (fr) 2004-10-06 2005-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees

Country Status (5)

Country Link
US (1) US7781300B2 (fr)
EP (1) EP1797588A2 (fr)
JP (1) JP5329808B2 (fr)
FR (1) FR2876220B1 (fr)
WO (1) WO2006072871A2 (fr)

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FR2850487B1 (fr) * 2002-12-24 2005-12-09 Commissariat Energie Atomique Procede de realisation de substrats mixtes et structure ainsi obtenue
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2875947B1 (fr) * 2004-09-30 2007-09-07 Tracit Technologies Nouvelle structure pour microelectronique et microsysteme et procede de realisation
FR2876220B1 (fr) 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2897982B1 (fr) 2006-02-27 2008-07-11 Tracit Technologies Sa Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat
US8264466B2 (en) * 2006-03-31 2012-09-11 3M Innovative Properties Company Touch screen having reduced visibility transparent conductor pattern
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FR2906078B1 (fr) * 2006-09-19 2009-02-13 Commissariat Energie Atomique Procede de fabrication d'une structure micro-technologique mixte et une structure ainsi obtenue
FR2909221B1 (fr) * 2006-11-29 2009-04-17 Commissariat Energie Atomique Procede de realisation d'un substrat mixte.
FR2910177B1 (fr) * 2006-12-18 2009-04-03 Soitec Silicon On Insulator Couche tres fine enterree
FR2910702B1 (fr) * 2006-12-26 2009-04-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat mixte
FR2914493B1 (fr) * 2007-03-28 2009-08-07 Soitec Silicon On Insulator Substrat demontable.
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FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
FR2932788A1 (fr) 2008-06-23 2009-12-25 Commissariat Energie Atomique Procede de fabrication d'un composant electromecanique mems / nems.
FR2932923B1 (fr) 2008-06-23 2011-03-25 Commissariat Energie Atomique Substrat heterogene comportant une couche sacrificielle et son procede de realisation.
EP2161742A1 (fr) 2008-09-03 2010-03-10 S.O.I.TEC. Silicon on Insulator Technologies S.A. Procédé pour la fabrication d'un substrat germanium sur un isolateur localement passivé
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
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JP5505367B2 (ja) 2011-05-11 2014-05-28 信越半導体株式会社 基板の一部に絶縁層を有する貼り合わせ基板の製造方法
US9329336B2 (en) * 2012-07-06 2016-05-03 Micron Technology, Inc. Method of forming a hermetically sealed fiber to chip connection
KR102007258B1 (ko) * 2012-11-21 2019-08-05 삼성전자주식회사 광전 집적회로 기판의 제조방법
FR3008190B1 (fr) 2013-07-08 2015-08-07 Commissariat Energie Atomique Procede et dispositif de mesure d'un champ magnetique au moyen d'excitations synchronisees
CN104752311B (zh) * 2013-12-27 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种绝缘体上硅衬底及其制造方法
FR3039699B1 (fr) * 2015-07-31 2017-07-28 Commissariat Energie Atomique Procede de realisation d'un dispositif electronique
FR3040108B1 (fr) 2015-08-12 2017-08-11 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse

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US5238865A (en) * 1990-09-21 1993-08-24 Nippon Steel Corporation Process for producing laminated semiconductor substrate
EP0736897A2 (fr) * 1995-04-04 1996-10-09 Motorola, Inc. Procédé pour former une structure de rainure pour isolation pour circuit intégré
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Also Published As

Publication number Publication date
WO2006072871A2 (fr) 2006-07-13
FR2876220A1 (fr) 2006-04-07
EP1797588A2 (fr) 2007-06-20
JP5329808B2 (ja) 2013-10-30
US20070202660A1 (en) 2007-08-30
JP2008516443A (ja) 2008-05-15
US7781300B2 (en) 2010-08-24
FR2876220B1 (fr) 2007-09-28

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