WO2006052379A1 - Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor - Google Patents

Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor Download PDF

Info

Publication number
WO2006052379A1
WO2006052379A1 PCT/US2005/036894 US2005036894W WO2006052379A1 WO 2006052379 A1 WO2006052379 A1 WO 2006052379A1 US 2005036894 W US2005036894 W US 2005036894W WO 2006052379 A1 WO2006052379 A1 WO 2006052379A1
Authority
WO
WIPO (PCT)
Prior art keywords
drain
spacer
outside
source
semiconductor layer
Prior art date
Application number
PCT/US2005/036894
Other languages
French (fr)
Inventor
Qi Xiang
Niraj Subba
Witold P. Maszara
Zoran Krivokapic
Ming-Ren Lin
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to JP2007541196A priority Critical patent/JP2008520097A/en
Priority to EP05812228A priority patent/EP1815531A1/en
Priority to KR1020077010284A priority patent/KR101122753B1/en
Priority to CN200580035899XA priority patent/CN101061587B/en
Publication of WO2006052379A1 publication Critical patent/WO2006052379A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Definitions

  • the present invention relates generally to silicon-on-insulator semiconductor _devices_ and more particularly to fully depleted silicon-on-insulator transistors.
  • Integrated circuits are used in everything from airplanes and televisions to wristwatches. Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each wafer worth hundreds or thousands of dollars.
  • CMOS complementary metal oxide semiconductor
  • CMOS transistor generally consist of a silicon substrate having shallow trench oxide isolation regions cordoning off transistor areas.
  • the transistor areas contain polysilicon gates on silicon oxide gates, or gate oxides, over the silicon substrate.
  • the silicon substrate on both sides of the polysilicon gate is slightly doped to become conductive. These lightly doped regions of the silicon substrate are referred to as “shallow source/drain”, which are separated by a channel region beneath the polysilicon gate.
  • a curved silicon oxide or silicon nitride spacer, referred to as a "sidewall spacer” on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain ("S/D”), which are called "deep S/D".
  • S/D shallow source/drain
  • a silicon oxide dielectric layer is deposited to cover the polysilicon gate, the curved spacer, and the silicon substrate.
  • openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the S/D. The openings are filled with metal to form electrical contacts.
  • the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
  • CMOS transistor uses an insulating substrate and is called silicon on insulator ("SOI").
  • SOI silicon on insulator
  • FETs field effect transistors
  • the SOI FETs are manufactured with an insulator, such as silicon dioxide, on a semiconductor substrate, such as silicon.
  • the entire FETs, including their source junction, channel, drain junction, gate, ohmic contacts and wiring channels, are formed on silicon islands in the insulator and are insulated from any fixed potential. This results in what is called the "floating body” problem because the potential of the body or channel regions floats and can acquire a potential which can interfere with the proper functioning of the FETs.
  • the floating body problem causes high leakage current and parasitic bipolar action since the semiconductor substrate is floating with respect to the channel. This problem has adverse affects on threshold voltage control and circuit operation.
  • FDSOI CMOS Another key issue for fabrication of FDSOI CMOS is mechanisms to improve performance.
  • One way to improve performance is to introduce tensile strain or compressive strain to the channel. Tensile strain along the direction of current flow increases both electron and hole mobility. On the other hand, compressive strain increases hole mobility but degrades electron mobility. Strain is introduced to the channel through trench isolation fill. However, mesa isolation, where there is no trench etch and fill, is conventionally used for FDSOI CMOS.
  • the present invention provides a semiconductor substrate having an insulator thereon with a semiconductor layer on the insulator.
  • a deep trench isolation is formed, introducing strain to the semiconductor layer.
  • a gate dielectric and a gate are formed on the semiconductor layer.
  • a spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
  • FIG. 1 is a cross-section of a fully depleted silicon on insulator semiconductor wafer
  • FIG. 2 shows the structure of FIG. 1 with a gate formed thereon;
  • FIG. 3 shows the structure of FIG. 2 with a liner and spacer deposited thereon;
  • FIG. 4 shows the structure of FIG. 3 with recessed source/drain in accordance with an embodiment of the present invention
  • FIG. 5 shows the structure of FIG. 4 after silicidation in accordance with an embodiment of the present invention
  • FIG. 6 shows the structure of FIG. 5 with a contact etch stop layer in accordance with an alternate embodiment of the present invention.
  • FIG. 7 is a flow chart of a method for manufacturing a strained fully depleted silicon on insulator semiconductor device in accordance with the present invention.
  • horizontal as used herein is defined as a plane parallel to a substrate or wafer.
  • vertical refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), "higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane.
  • processing includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
  • FDSOI fully depleted silicon on insulator
  • Si p-doped silicon
  • BOX buried oxide layer
  • SiO 2 silicon dioxide
  • a deep trench isolation (“DTI") 108 spaced outside recessed source/drain 402 (FIG. 4), has been added to the FDSOI wafer 100.
  • the DTI 108 is formed with a deep trench etch that etches through the channel layer 106, the BOX 104, and into the substrate 102. To maintain device isolation, the depth of the DTI must be greater than the recessed source/drain 402 (FIG. 4).
  • the resulting deep trench is filled with a dielectric of a material such as SiO 2 .
  • FIG. 2 therein is shown the structure of FIG. 1 after conventional deposition, patterning, photolithography, and etching to form a gate dielectric 202 of a material such as SiO 2 , silicon oxynitride ("SiON"), or silicon nitride ("Si 3 N 4 "), and a gate 204 of a material such as polysilicon or amorphous silicon which can be either doped or undoped.
  • a gate dielectric 202 of a material such as SiO 2 , silicon oxynitride ("SiON"), or silicon nitride ("Si 3 N 4 ")
  • Si 3 N 4 silicon nitride
  • a liner 302 of a material such as SiO 2 is deposited on the gate 204, the channel layer 106, and the DTI 108.
  • a spacer 304 of a material such as Si 3 N 4 is formed around the gate portion of the liner 302 and in the DTI 108.
  • FIG. 4 therein is shown the structure of FIG 3 after processing in accordance with an embodiment of the present invention.
  • Recessed source/drain 402 have been added to the FDSOI wafer 100.
  • the channel layer 106 has been etched to form a channel 404.
  • a suitable process such as etching, is used to penetrate through the channel layer 106 and the BOX 104 between the gate 204 and the DTI 108. It has been discovered that a thin BOX 104 from IOOA - 6O ⁇ A provides an optimal thickness. Selective epitaxial growth (“SEG”) then takes place on the surface of the substrate 102 and the sidewall of the channel 404. This ensures a continuous, high quality Si surface for the SEG of the recessed source/drain 402 even when silicon of the channel layer 106 may be partially or even entirely consumed by previous processes.
  • SEG selective epitaxial growth
  • the resulting structure retains the advantages of elevated source and drain, such as low parasitic series resistance, while overcoming the problem of SEG on thin silicon. At this stage, performance can be improved through modification of the SEG of the recessed source/drain 402.
  • FIG. 5 therein is shown the structure of FIG. 4 after further processing in accordance with an embodiment of the present invention.
  • Silicidation takes place on the gate 204 and the source/drain 402 to form a NiSi layer 504.
  • the recessed source/drain 402 can be formed in situ during selective epitaxial growth of the recessed source/drain 402 or by ion implantation and rapid thermal anneal.
  • the DTI 108 introduces strain to the channel 404 and is preferred for isolation among transistors. Introducing tensile strain or compressive strain to the channels of FDSOI CMOS devices improves performance. Tensile strain along the direction of current flow increases both electron and hole mobility in an
  • strain can be further improved in FDSOI PMOS transistors by selective epitaxial growth of silicon germanium (SiGe).
  • SiGe of the recessed source/drain 402 effectively induce strain in the channel 404 of a FDSOI PMOS transistor.
  • the strain is also more effective because the recessed source/drain 402 are immediately adjacent the channel 404 and allow more strain to be introduced than can be introduced in raised source/drain.
  • strain can be further improved in FDSOI NMOS transistors by selective epitaxial growth of silicon carbide (SiC).
  • SiC of the recessed source/drain effectively induce strain in the channel 404 of a FDSOI NMOS transistor.
  • the strain is also more effective because the recessed source/drain 402 are immediately adjacent the channel 404 and more strain can be introduced than can be introduced in raised source/drain.
  • the above strain control can be implemented as an adjunct to the strain control from the DTI 108 or as the primary control where the DTI 108 is formed before the recessed source/drain 402.
  • FIG. 6 therein is shown the structure of FIG. 5 after further processing in accordance with an alternate embodiment of the present invention.
  • An etch has removed the spacer 304 (FIG. 5) and the dielectric fill of the DTI 108 (FIG. 5), leaving a trench 602.
  • a contact etch stop layer 604 is deposited in the trench 602 and over the source/drain 402, the liner 302, and the gate 204.
  • the contact etch stop layer 604 in the trench 602 introduces additional strain to the channel 404.
  • the method 700 includes providing a semiconductor substrate having an insulator thereon with a semiconductor layer on the insulator in a block 702; forming a gate dielectric and a gate on the semiconductor layer in a block 704; forming a deep trench isolation spaced outside the spacer and introducing strain to the semiconductor layer in a block 706; forming a. spacer around the gate in a block 708; removing the semiconductor layer and the insulator outside the spacer in a block 710; and forming recessed source/drain outside the spacer in a block 712.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor substrate (102) is provided having an insulator (104) thereon with a semiconductor layer (106) on the insulator (104). A deep trench isolation (108) is formed, introducing strain to the semiconductor layer (106). A gate dielectric (202) and a gate (204) are formed on the semiconductor layer (106). A spacer (304) is formed around the gate (204), and the semiconductor layer (106) and the insulator (104) are removed outside the spacer (304). Recessed source/drain (402) are formed outside the spacer (304).

Description

STRAINED FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
TECHNICAL FIELD
The present invention relates generally to silicon-on-insulator semiconductor _devices_ and more particularly to fully depleted silicon-on-insulator transistors.
BACKGROUND ART
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in everything from airplanes and televisions to wristwatches. Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each wafer worth hundreds or thousands of dollars.
Integrated circuits are made up of hundreds to millions of individual components. One common component is the semiconductor transistor. The most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor device is a complementary metal oxide semiconductor ("CMOS") transistor.
The principal elements of a CMOS transistor generally consist of a silicon substrate having shallow trench oxide isolation regions cordoning off transistor areas. The transistor areas contain polysilicon gates on silicon oxide gates, or gate oxides, over the silicon substrate. The silicon substrate on both sides of the polysilicon gate is slightly doped to become conductive. These lightly doped regions of the silicon substrate are referred to as "shallow source/drain", which are separated by a channel region beneath the polysilicon gate. A curved silicon oxide or silicon nitride spacer, referred to as a "sidewall spacer", on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain ("S/D"), which are called "deep S/D".
To complete the transistor, a silicon oxide dielectric layer is deposited to cover the polysilicon gate, the curved spacer, and the silicon substrate. To provide electrical connections for the transistor, openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the S/D. The openings are filled with metal to form electrical contacts. To complete the integrated circuits, the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
One improvement to the CMOS transistor uses an insulating substrate and is called silicon on insulator ("SOI"). The advantages of using an insulating substrate in CMOS and high speed field effect transistors ("FETs") include latchup immunity, radiation hardness, reduced parasitic junction capacitance, reduced junction leakage currents, and reduced short channel effects. Many of these advantages translate to increased speed performance of the FETs.
The SOI FETs are manufactured with an insulator, such as silicon dioxide, on a semiconductor substrate, such as silicon. The entire FETs, including their source junction, channel, drain junction, gate, ohmic contacts and wiring channels, are formed on silicon islands in the insulator and are insulated from any fixed potential. This results in what is called the "floating body" problem because the potential of the body or channel regions floats and can acquire a potential which can interfere with the proper functioning of the FETs. The floating body problem causes high leakage current and parasitic bipolar action since the semiconductor substrate is floating with respect to the channel. This problem has adverse affects on threshold voltage control and circuit operation.
In order to eliminate the floating body problem, it is necessary to fully deplete the silicon island. This means making the silicon island so thin that the entire thickness of the body region is depleted of majority carriers when the FET is in the off state and both junctions are at ground. To fully deplete the silicon island and create a fully depleted silicon on insulator ("FDSOI"), it has been found that the silicon island must be extremely thin.
However, having a thin silicon island causes problems in the fabrication of FDSOI CMOS in the formation of source and drain with low parasitic series resistance. One solution is to elevate the source and drain over the thin silicon island. Elevated source and drain are formed by selective epitaxial growth ("SEG"). Unfortunately, it is difficult to uniformly grow high quality, single crystalline source and drain on the extremely thin silicon island. Furthermore, processes performed prior to SEG, such as oxidation, pre-clean, and H2 baking, can remove all or parts of the thin silicon needed for SEG.
Another key issue for fabrication of FDSOI CMOS is mechanisms to improve performance. One way to improve performance is to introduce tensile strain or compressive strain to the channel. Tensile strain along the direction of current flow increases both electron and hole mobility. On the other hand, compressive strain increases hole mobility but degrades electron mobility. Strain is introduced to the channel through trench isolation fill. However, mesa isolation, where there is no trench etch and fill, is conventionally used for FDSOI CMOS.
What is needed, therefore, is a way to uniformly grow high quality, single crystalline source and drain while introducing strain to the channel. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a semiconductor substrate having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer. Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-section of a fully depleted silicon on insulator semiconductor wafer;
FIG. 2 shows the structure of FIG. 1 with a gate formed thereon; FIG. 3 shows the structure of FIG. 2 with a liner and spacer deposited thereon;
FIG. 4 shows the structure of FIG. 3 with recessed source/drain in accordance with an embodiment of the present invention; FIG. 5 shows the structure of FIG. 4 after silicidation in accordance with an embodiment of the present invention;
FIG. 6 shows the structure of FIG. 5 with a contact etch stop layer in accordance with an alternate embodiment of the present invention; and
FIG. 7 is a flow chart of a method for manufacturing a strained fully depleted silicon on insulator semiconductor device in accordance with the present invention.
MODE(S) FOR CARRYING OUT THE INVENTION
In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known device configurations and process steps are not disclosed in detail.
Likewise, the drawings showing embodiments of the device are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be shown greatly exaggerated in the FIGs.
The term "horizontal" as used herein is defined as a plane parallel to a substrate or wafer. The term "vertical" refers to a direction perpendicular to the horizontal as just defined. Terms, such as "on", "above", "below", "bottom", "top", "side" (as in "sidewall"), "higher", "lower", "over", and "under", are defined with respect to the horizontal plane.
The term "processing" as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
Referring now to FIG. 1, therein is shown a cross-section of a fully depleted silicon on insulator ("FDSOI") wafer 100, which includes a semiconductor substrate 102 of a material such as a p-doped silicon ("Si"). On top of the semiconductor substrate 102 is a buried oxide layer ("BOX") 104, which is an insulator layer of a material such as silicon dioxide ("SiO2"), and a channel layer 106 of a thin layer of Si. In order to control short channel effects of 45nm and below node with a 25nm or smaller gate length, it has been discovered that the channel layer 106 must be thinner than 100 A in thickness. A deep trench isolation ("DTI") 108, spaced outside recessed source/drain 402 (FIG. 4), has been added to the FDSOI wafer 100. The DTI 108 is formed with a deep trench etch that etches through the channel layer 106, the BOX 104, and into the substrate 102. To maintain device isolation, the depth of the DTI must be greater than the recessed source/drain 402 (FIG. 4). In order to complete the DTI 108, the resulting deep trench is filled with a dielectric of a material such as SiO2.
Referring now to FIG. 2, therein is shown the structure of FIG. 1 after conventional deposition, patterning, photolithography, and etching to form a gate dielectric 202 of a material such as SiO2, silicon oxynitride ("SiON"), or silicon nitride ("Si3N4"), and a gate 204 of a material such as polysilicon or amorphous silicon which can be either doped or undoped. Referring now to FIG. 3, therein is shown the structure of FIG. 2 after further processing. A recess etch of the DTI 108 prepares the wafer 100 for spacer formation in the DTI 108. A liner 302 of a material such as SiO2 is deposited on the gate 204, the channel layer 106, and the DTI 108. A spacer 304 of a material such as Si3N4 is formed around the gate portion of the liner 302 and in the DTI 108.
Among the key issues for fabrication of FDSOI CMOS is the formation of source and drain with low parasitic series resistance. One solution has been to elevate the source and drain. Elevated source and drain can be formed by selective epitaxial growth ("SEG"). Unfortunately, it is difficult to uniformly grow high quality, single crystalline source and drain on an extremely thin silicon island such as the channel layer 106. Furthermore, processes performed prior to SEG, such as oxidation, pre-clean, and H2 baking, can remove all or parts of the thin silicon needed for SEG. Referring now to FIG. 4, therein is shown the structure of FIG 3 after processing in accordance with an embodiment of the present invention. Recessed source/drain 402 have been added to the FDSOI wafer 100. The channel layer 106 has been etched to form a channel 404.
To form the recessed source/drain 402, a suitable process, such as etching, is used to penetrate through the channel layer 106 and the BOX 104 between the gate 204 and the DTI 108. It has been discovered that a thin BOX 104 from IOOA - 6OθA provides an optimal thickness. Selective epitaxial growth ("SEG") then takes place on the surface of the substrate 102 and the sidewall of the channel 404. This ensures a continuous, high quality Si surface for the SEG of the recessed source/drain 402 even when silicon of the channel layer 106 may be partially or even entirely consumed by previous processes.
The resulting structure retains the advantages of elevated source and drain, such as low parasitic series resistance, while overcoming the problem of SEG on thin silicon. At this stage, performance can be improved through modification of the SEG of the recessed source/drain 402.
Referring now to FIG. 5, therein is shown the structure of FIG. 4 after further processing in accordance with an embodiment of the present invention. Silicidation takes place on the gate 204 and the source/drain 402 to form a NiSi layer 504. It will be understood that the order of forming the recessed source/drain 402 and the DTI 108 is optional and the sequence described above has been done so as a matter of convenience. The recessed source/drain 402 can be formed in situ during selective epitaxial growth of the recessed source/drain 402 or by ion implantation and rapid thermal anneal. Through strain engineered trench fill dielectrics, the DTI 108 introduces strain to the channel 404 and is preferred for isolation among transistors. Introducing tensile strain or compressive strain to the channels of FDSOI CMOS devices improves performance. Tensile strain along the direction of current flow increases both electron and hole mobility in an
NMOS. On the other hand compressive strain improves performance of a PMOS by increasing hole mobility.
Thus, applied strain as appropriate to the channel 404 significantly increases channel mobility, consequently increasing drive current by a significant fraction of the mobility gain.
It has been discovered that strain can be further improved in FDSOI PMOS transistors by selective epitaxial growth of silicon germanium (SiGe). Thus, the SiGe of the recessed source/drain 402 effectively induce strain in the channel 404 of a FDSOI PMOS transistor. The strain is also more effective because the recessed source/drain 402 are immediately adjacent the channel 404 and allow more strain to be introduced than can be introduced in raised source/drain.
Furthermore, it has been discovered that strain can be further improved in FDSOI NMOS transistors by selective epitaxial growth of silicon carbide (SiC). Thus, SiC of the recessed source/drain effectively induce strain in the channel 404 of a FDSOI NMOS transistor. The strain is also more effective because the recessed source/drain 402 are immediately adjacent the channel 404 and more strain can be introduced than can be introduced in raised source/drain.
The above strain control can be implemented as an adjunct to the strain control from the DTI 108 or as the primary control where the DTI 108 is formed before the recessed source/drain 402.
Referring now to FIG. 6, therein is shown the structure of FIG. 5 after further processing in accordance with an alternate embodiment of the present invention. An etch has removed the spacer 304 (FIG. 5) and the dielectric fill of the DTI 108 (FIG. 5), leaving a trench 602. After the etch, a contact etch stop layer 604 is deposited in the trench 602 and over the source/drain 402, the liner 302, and the gate 204. The contact etch stop layer 604 in the trench 602 introduces additional strain to the channel 404.
Referring now to FIG. 7, therein is shown a flow chart of a method 700 for manufacturing a strained fully depleted silicon on insulator semiconductor device in accordance with the present invention. The method 700 includes providing a semiconductor substrate having an insulator thereon with a semiconductor layer on the insulator in a block 702; forming a gate dielectric and a gate on the semiconductor layer in a block 704; forming a deep trench isolation spaced outside the spacer and introducing strain to the semiconductor layer in a block 706; forming a. spacer around the gate in a block 708; removing the semiconductor layer and the insulator outside the spacer in a block 710; and forming recessed source/drain outside the spacer in a block 712. Thus, it has been discovered that the semiconductor device method and apparatus of the present invention furnish important and heretofore unknown and unavailable solutions, capabilities, and functional advantages for FDSOI CMOS. The resulting process and configurations are straightforward, economical, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready manufacturing, application, and utilization. While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims

THE INVENTION CLAIMED IS:
1. A method (700) for manufacturing a semiconductor device comprising: providing a semiconductor substrate (102) having an insulator (104) thereon with a semiconductor layer (106) on the insulator (104); forming a deep trench isolation (108), introducing strain to the semiconductor layer (106); forming a gate dielectric (202) and a gate (204) on the semiconductor layer (106); forming a spacer (304) around the gate (204); removing the semiconductor layer (106) and the insulator (104) outside the spacer (304); and forming recessed source/drain (402) outside the spacer (304)..
2. The method (700) of claim 1 wherein forming recessed source/drain (402) outside the spacer
(304) further comprises forming recessed source/drain (402) by selective epitaxial growth outside the spacer (304).
3. The method (700) of claim 1 wherein forming recessed source/drain (402) outside the spacer (304) further comprises forming recessed carbon doped silicon source/drain (402) outside the spacer (304), introducing strain to the semiconductor layer (106).
4. The method (700) of claim 1 wherein forming recessed source/drain (402) outside the spacer (304) further comprises forming recessed silicon germanium source/drain (402) outside the spacer (304), introducing strain to the semiconductor layer (106).
5. The method (700) of claim 1 additionally comprising: removing the spacer (304); removing the deep trench isolation (108), leaving a trench (602); depositing a layer (604) in the trench (602), over the recessed source/drain (402), and over the gate (204), introducing strain to the semiconductor layer (106).
6. A semiconductor device comprising: a semiconductor substrate (102) having an insulator (104) thereon with a semiconductor layer (106) on the insulator (104); a gate dielectric (202) and a gate (204) on the semiconductor layer (106); optionally a spacer (304) around the gate (204); recessed source/drain (402) outside the spacer (304); and a trench (602) spaced outside the spacer (304), optionally introducing strain to the silicon layer as a deep trench isolation (108).
7. The semiconductor device of claim 6 wherein the recessed source/drain (402) outside the spacer (304) further comprises recessed source/drain (402) formed by selective epitaxial growth outside the spacer (304).
8. The semiconductor device of claim 6 wherein the recessed source/drain (402) outside the spacer (304) further comprises recessed carbon doped silicon source/drain (402) outside the spacer (304) introducing strain to the semiconductor layer (106).
9. The semiconductor device of claim 6 wherein the recessed source/drain (402) outside the spacer (304) further comprises recessed silicon germanium source/drain (402) outside the spacer (304), introducing strain to the semiconductor layer (106).
10. The semiconductor device of claim 6 additionally comprising a layer in the trench (602), over the recessed source/drain (402), and over the gate (204), introducing strain to the semiconductor layer (106).
PCT/US2005/036894 2004-11-10 2005-10-12 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor WO2006052379A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007541196A JP2008520097A (en) 2004-11-10 2005-10-12 Strain fully depleted silicon-on-insulator semiconductor device and manufacturing method thereof
EP05812228A EP1815531A1 (en) 2004-11-10 2005-10-12 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
KR1020077010284A KR101122753B1 (en) 2004-11-10 2005-10-12 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
CN200580035899XA CN101061587B (en) 2004-11-10 2005-10-12 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/986,399 US7306997B2 (en) 2004-11-10 2004-11-10 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
US10/986,399 2004-11-10

Publications (1)

Publication Number Publication Date
WO2006052379A1 true WO2006052379A1 (en) 2006-05-18

Family

ID=35658988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/036894 WO2006052379A1 (en) 2004-11-10 2005-10-12 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor

Country Status (7)

Country Link
US (2) US7306997B2 (en)
EP (1) EP1815531A1 (en)
JP (1) JP2008520097A (en)
KR (1) KR101122753B1 (en)
CN (1) CN101061587B (en)
TW (1) TWI380373B (en)
WO (1) WO2006052379A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007053382A1 (en) * 2005-10-31 2007-05-10 Advanced Micro Devices, Inc. An embedded strain layer in thin soi transistors and a method of forming the same
JP2008071851A (en) * 2006-09-13 2008-03-27 Sony Corp Semiconductor device and manufacturing method thereof
US7399663B2 (en) 2005-10-31 2008-07-15 Advanced Micro Devices, Inc. Embedded strain layer in thin SOI transistors and a method of forming the same
JP2009519610A (en) * 2005-12-14 2009-05-14 インテル コーポレイション Strained silicon MOS device with box layer between source and drain regions
JP5182703B2 (en) * 2006-06-08 2013-04-17 日本電気株式会社 Semiconductor device

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2872626B1 (en) * 2004-07-05 2008-05-02 Commissariat Energie Atomique METHOD FOR CONTRAINDING A THIN PATTERN
JP2006165335A (en) * 2004-12-08 2006-06-22 Toshiba Corp Semiconductor device
US7091071B2 (en) * 2005-01-03 2006-08-15 Freescale Semiconductor, Inc. Semiconductor fabrication process including recessed source/drain regions in an SOI wafer
US7446350B2 (en) * 2005-05-10 2008-11-04 International Business Machine Corporation Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer
JP2006332243A (en) * 2005-05-25 2006-12-07 Toshiba Corp Semiconductor device and its manufacturing method
US7384851B2 (en) * 2005-07-15 2008-06-10 International Business Machines Corporation Buried stress isolation for high-performance CMOS technology
US7473593B2 (en) * 2006-01-11 2009-01-06 International Business Machines Corporation Semiconductor transistors with expanded top portions of gates
US7569434B2 (en) * 2006-01-19 2009-08-04 International Business Machines Corporation PFETs and methods of manufacturing the same
DE602006019940D1 (en) * 2006-03-06 2011-03-17 St Microelectronics Crolles 2 Production of a shallow conducting channel made of SiGe
US7613369B2 (en) * 2006-04-13 2009-11-03 Luxtera, Inc. Design of CMOS integrated germanium photodiodes
US8154051B2 (en) * 2006-08-29 2012-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. MOS transistor with in-channel and laterally positioned stressors
JP2008153515A (en) * 2006-12-19 2008-07-03 Fujitsu Ltd Mos transistor, method for manufacturing the same mos transistor, cmos type semiconductor device using the same mos transistor, and semiconductor device using the same cmos type semiconductor device
US20080157118A1 (en) * 2006-12-29 2008-07-03 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing strained technology
US9640666B2 (en) * 2007-07-23 2017-05-02 GlobalFoundries, Inc. Integrated circuit employing variable thickness film
JP2009212413A (en) * 2008-03-06 2009-09-17 Renesas Technology Corp Semiconductor device and method of manufacturing semiconductor device
US8421050B2 (en) * 2008-10-30 2013-04-16 Sandisk 3D Llc Electronic devices including carbon nano-tube films having carbon-based liners, and methods of forming the same
KR101592505B1 (en) 2009-02-16 2016-02-05 삼성전자주식회사 Semiconductor memory device and method of manufacturing the same
US8106456B2 (en) * 2009-07-29 2012-01-31 International Business Machines Corporation SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics
US7994062B2 (en) * 2009-10-30 2011-08-09 Sachem, Inc. Selective silicon etch process
CN102299092B (en) * 2010-06-22 2013-10-30 中国科学院微电子研究所 Semiconductor device and forming method thereof
CN102376769B (en) * 2010-08-18 2013-06-26 中国科学院微电子研究所 Ultra-thin body transistor and manufacturing method thereof
CN102487018B (en) * 2010-12-03 2014-03-12 中芯国际集成电路制造(北京)有限公司 MOS transistor and formation method thereof
CN102122669A (en) * 2011-01-27 2011-07-13 上海宏力半导体制造有限公司 Transistor and manufacturing method thereof
US8455308B2 (en) 2011-03-16 2013-06-04 International Business Machines Corporation Fully-depleted SON
US9184214B2 (en) * 2011-04-11 2015-11-10 Globalfoundries Inc. Semiconductor device exhibiting reduced parasitics and method for making same
US20120326230A1 (en) * 2011-06-22 2012-12-27 International Business Machines Corporation Silicon on insulator complementary metal oxide semiconductor with an isolation formed at low temperature
WO2013020576A1 (en) * 2011-08-05 2013-02-14 X-Fab Semiconductor Foundries Ag Semiconductor device
US9136158B2 (en) * 2012-03-09 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral MOSFET with dielectric isolation trench
US8664050B2 (en) 2012-03-20 2014-03-04 International Business Machines Corporation Structure and method to improve ETSOI MOSFETS with back gate
CN102931092A (en) * 2012-10-26 2013-02-13 哈尔滨工程大学 Autocollimation SOI (Silicon On Insulator) FD (focal distanc) MOSFEI (metal-oxide -semiconductor field effect transistor) formation method
CN103779279B (en) * 2012-10-26 2017-09-01 中芯国际集成电路制造(上海)有限公司 A kind of manufacture method of semiconductor devices
US9525027B2 (en) * 2014-03-13 2016-12-20 Globalfoundries Inc. Lateral bipolar junction transistor having graded SiGe base
FR3025941A1 (en) * 2014-09-17 2016-03-18 Commissariat Energie Atomique MOS TRANSISTOR WITH RESISTANCE AND REDUCED PARASITE CAPACITY
CN105632909B (en) * 2014-11-07 2019-02-01 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacturing method, electronic device
US9281305B1 (en) 2014-12-05 2016-03-08 National Applied Research Laboratories Transistor device structure
CN105742248A (en) * 2014-12-09 2016-07-06 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure
US20230269061A1 (en) * 2022-02-18 2023-08-24 Psemi Corporation Lna with tx harmonic filter

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986287A (en) * 1995-09-08 1999-11-16 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E. V. Semiconductor structure for a transistor
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US20040005740A1 (en) * 2002-06-07 2004-01-08 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20040018668A1 (en) * 2002-06-25 2004-01-29 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US20040087114A1 (en) * 2002-10-24 2004-05-06 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
US20040108559A1 (en) * 2002-10-02 2004-06-10 Renesas Technology Corp. Insulated-gate field-effect transistor, method of fabricating same, and semiconductor device employing same
WO2004049406A1 (en) * 2002-11-25 2004-06-10 International Business Machines Corporation Strained finfet cmos device structures
US20040188760A1 (en) * 2002-04-03 2004-09-30 Thomas Skotnicki Strained-channel isolated-gate field effect transistor, process for making same and resulting integrated circuit
US20040217430A1 (en) * 2003-05-01 2004-11-04 Chu Jack Oon High performance FET devices and methods therefor

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2636786B2 (en) * 1995-03-20 1997-07-30 日本電気株式会社 Method for manufacturing semiconductor device
JP3373772B2 (en) * 1997-11-19 2003-02-04 株式会社東芝 Semiconductor device
US6303448B1 (en) * 1998-11-05 2001-10-16 Taiwan Semiconductor Manufacturing Company Method for fabricating raised source/drain structures
US6339244B1 (en) * 2000-02-22 2002-01-15 Advanced Micro Devices, Inc. Fully depleted silicon on insulator semiconductor device and manufacturing method therefor
US6323104B1 (en) * 2000-03-01 2001-11-27 Micron Technology, Inc. Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry
JP2002083972A (en) * 2000-09-11 2002-03-22 Hitachi Ltd Semiconductor integrated circuit device
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
JP2002237590A (en) * 2001-02-09 2002-08-23 Univ Tohoku Mos field effect transistor
US6558994B2 (en) * 2001-03-01 2003-05-06 Chartered Semiconductors Maufacturing Ltd. Dual silicon-on-insulator device wafer die
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6660598B2 (en) * 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP4173672B2 (en) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
KR100416627B1 (en) * 2002-06-18 2004-01-31 삼성전자주식회사 Semiconductor device and Method for manufacturing the same
US20040033677A1 (en) * 2002-08-14 2004-02-19 Reza Arghavani Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
US8097924B2 (en) * 2003-10-31 2012-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same
US7037795B1 (en) * 2004-10-15 2006-05-02 Freescale Semiconductor, Inc. Low RC product transistors in SOI semiconductor process

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986287A (en) * 1995-09-08 1999-11-16 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E. V. Semiconductor structure for a transistor
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US20040188760A1 (en) * 2002-04-03 2004-09-30 Thomas Skotnicki Strained-channel isolated-gate field effect transistor, process for making same and resulting integrated circuit
US20040005740A1 (en) * 2002-06-07 2004-01-08 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20040018668A1 (en) * 2002-06-25 2004-01-29 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US20040108559A1 (en) * 2002-10-02 2004-06-10 Renesas Technology Corp. Insulated-gate field-effect transistor, method of fabricating same, and semiconductor device employing same
US20040087114A1 (en) * 2002-10-24 2004-05-06 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
WO2004049406A1 (en) * 2002-11-25 2004-06-10 International Business Machines Corporation Strained finfet cmos device structures
US20040217430A1 (en) * 2003-05-01 2004-11-04 Chu Jack Oon High performance FET devices and methods therefor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JURCZAK M ET AL: "SILICON-ON-NOTHING (SON)-AN INNOVATIVE PROCESS FOR ADVANCED CMOS", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, vol. 47, no. 11, November 2000 (2000-11-01), pages 2179 - 2185, XP000970486, ISSN: 0018-9383 *
MONFRAY S ET AL: "COULOMB-BLOCKADE IN NANOMETRIC SI-FILM SILICON-ON-NOTHING (SON) MOSFETS", IEEE TRANSACTIONS ON NANOTECHNOLOGY, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 2, no. 4, December 2003 (2003-12-01), pages 295 - 300, XP001046490, ISSN: 1536-125X *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007053382A1 (en) * 2005-10-31 2007-05-10 Advanced Micro Devices, Inc. An embedded strain layer in thin soi transistors and a method of forming the same
GB2445511A (en) * 2005-10-31 2008-07-09 Advanced Micro Devices Inc An embedded strain layer in thin soi transistors and a method of forming the same
US7399663B2 (en) 2005-10-31 2008-07-15 Advanced Micro Devices, Inc. Embedded strain layer in thin SOI transistors and a method of forming the same
GB2445511B (en) * 2005-10-31 2009-04-08 Advanced Micro Devices Inc An embedded strain layer in thin soi transistors and a method of forming the same
JP2009519610A (en) * 2005-12-14 2009-05-14 インテル コーポレイション Strained silicon MOS device with box layer between source and drain regions
DE112006003402B4 (en) * 2005-12-14 2010-01-28 Intel Corp., Santa Clara A strained silicon MOS device having a buried oxide layer (BOX) layer between the source and drain regions and manufacturing methods therefor
JP5182703B2 (en) * 2006-06-08 2013-04-17 日本電気株式会社 Semiconductor device
US9577095B2 (en) 2006-06-08 2017-02-21 Renesas Electronics Corporation Semiconductor device
JP2008071851A (en) * 2006-09-13 2008-03-27 Sony Corp Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
US20060099752A1 (en) 2006-05-11
CN101061587A (en) 2007-10-24
KR20070084008A (en) 2007-08-24
TW200620489A (en) 2006-06-16
JP2008520097A (en) 2008-06-12
US7306997B2 (en) 2007-12-11
KR101122753B1 (en) 2012-03-23
EP1815531A1 (en) 2007-08-08
US20080054316A1 (en) 2008-03-06
CN101061587B (en) 2011-01-12
US8502283B2 (en) 2013-08-06
TWI380373B (en) 2012-12-21

Similar Documents

Publication Publication Date Title
US7306997B2 (en) Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
US8211761B2 (en) Semiconductor system using germanium condensation
JP4110085B2 (en) Manufacturing method of double gate type field effect transistor
US7435639B2 (en) Dual surface SOI by lateral epitaxial overgrowth
US6605514B1 (en) Planar finFET patterning using amorphous carbon
US7994010B2 (en) Process for fabricating a semiconductor device having embedded epitaxial regions
US8298895B1 (en) Selective threshold voltage implants for long channel devices
US7670914B2 (en) Methods for fabricating multiple finger transistors
US9634103B2 (en) CMOS in situ doped flow with independently tunable spacer thickness
US7781278B2 (en) CMOS devices having channel regions with a V-shaped trench and hybrid channel orientations, and method for forming the same
KR100612420B1 (en) Semiconductor device and method for forming the same
KR20000029367A (en) Deep divot mask for enhanced buried-channel pfet performance and reliability
US7442612B2 (en) Nitride-encapsulated FET (NNCFET)
US20040253773A1 (en) SOI shaped structure
US6657261B2 (en) Ground-plane device with back oxide topography
KR101336219B1 (en) Fully depleted SOI device with buried doped layer
KR100886708B1 (en) Soi device and method for fabricating the same
US20060068542A1 (en) Isolation trench perimeter implant for threshold voltage control
KR20080081550A (en) Mosfet device and method of mamufacturing the same
KR100486643B1 (en) Method for manufacturing mosfet
KR19990075417A (en) Manufacturing Method of Semiconductor Device
KR100295687B1 (en) Manufacturing method for mostransistor
JP2007299977A (en) Process for fabricating semiconductor device
KR19990038113A (en) Manufacturing method of MOS device
KR20050050909A (en) Method for forming semiconductor device by silicon on insulator

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 200580035899.X

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 1020077010284

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2007541196

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2005812228

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2005812228

Country of ref document: EP