CN101061587A - Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor - Google Patents

Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor Download PDF

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Publication number
CN101061587A
CN101061587A CNA200580035899XA CN200580035899A CN101061587A CN 101061587 A CN101061587 A CN 101061587A CN A200580035899X A CNA200580035899X A CN A200580035899XA CN 200580035899 A CN200580035899 A CN 200580035899A CN 101061587 A CN101061587 A CN 101061587A
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drain
interval body
concave type
outside
semiconductor layer
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CN101061587B (en
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相奇
N·苏巴
W·P·麦斯扎拉
Z·克里沃卡皮克
M-R·林
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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Abstract

A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Description

Strained fully depleted silicon on insulator semiconductor device and manufacture method thereof
Technical field
The present invention roughly is about silicon-on-insulator (silicon-on-insulator) semiconductor device, refers in particular to exhaust the silicon-on-insulator transistor entirely.
Background technology
Each aspect during electronic product almost is applied to live at present, and the heart of those electronic products promptly is an integrated circuit.Integrated circuit is applied to aircraft, TV to the various products of wrist-watch.
With utmost point complication system, need the coordination of the program of hundreds of or even thousands of accurate controls, make integrated circuit in Silicon Wafer or on the Silicon Wafer, and get a semiconductor crystal wafer of finishing.Each semiconductor crystal wafer of finishing has hundreds to tens thousand of integrated circuits, and the hundreds of or thousands of dollars of each wafer worth.
Integrated circuit is made of hundreds of extremely millions of stand-alone assemblies.A kind of assembly commonly used is semiconductor transistor.The most normal use at present and important semiconductor technology are based on silicon, and the best based on the semiconductor device of silicon be complementary metal oxide semiconductors (CMOS) (complementary metal oxide semiconductor, CMOS).
The primary clustering of CMOS (Complementary Metal Oxide Semiconductor) transistor by having the oxide shallow trench isolation region, is formed in order to the silicon substrate in isolated transistor district usually.On the silicon substrate, transistor area contains compound crystal silicon (polysilicon) grid on silica grid or gate oxide.The silicon substrate of compound crystal silicon grid both sides of mixing a little makes tool conductivity.Those silicon substrates doped regions a little are called " shallow source/drain ", and the channel region below this compound crystal silicon grid separates.The crooked silica of compound crystal silicon grid side or silicon nitride spacer body (spacer), be called " sidewall spacers (sidewallspacer) ", other doping is deposited and the more severe doped region of formation shallow source/drain, be called " deep source/drain (deep S/D) ".
The silicon oxide dielectric layer is deposited to cover compound crystal silicon grid, curved spacer and silicon substrate, to finish transistorized making.For transistorized electric connection is provided, in the silicon oxide dielectric layer etching perforate of compound crystal silicon grid and source/drain.Those perforates are with metal filled and form electrically contact.For finishing the making of integrated circuit, those contacts are connected to other line layer in the other dielectric materials layer, make to reach to this dielectric material outside.
A kind of method of improving CMOS (Complementary Metal Oxide Semiconductor) transistor is used dielectric substrate, be called silicon-on-insulator (silicon on insulator, SOI).Complementary metal oxide semiconductors (CMOS) and high speed field-effect transistor (field effect transistors, FETs) advantage of use dielectric substrate comprises elimination latch-up phenomenon (latch-up immunity), improves radioresistance power (radiationhardness), reduces parasitic junction capacitance, reduction connects the face leakage current and reduce short-channel effect.The many speed abilities that increase field-effect transistor that change into of those advantages.
The silicon-on-insulator field-effect transistor is on the Semiconductor substrate for example on the silicon substrate, makes to have for example insulator of silicon dioxide.Whole field-effect transistor comprises its source junction, raceway groove, drain junction, grid, ohmic contact and wiring raceway groove, is formed on the silicon island of insulator, and isolated with any fixed potential.This can cause so-called " buoyancy aid (floating body) " problem, because the current potential of this buoyancy aid or channel region is floating, and can obtain to disturb the cause of the current potential of field-effect transistor normal function.Because it is floating that Semiconductor substrate presents raceway groove, so the buoyancy aid problem causes high leakage current and parasitic bipolar action.This problem is unfavorable for the control and the circuit operation of threshold voltage (thresholdvoltage).
In order to solve the buoyancy aid problem, the silicon island need be exhausted fully (deplete).This meaning connects face all during ground connection when field-effect transistor is in not on-state (off state) and two, the silicon island is as thin as allows whole floating body region thickness lack the degree of most of carriers.Exhaust silicon-on-insulator entirely (fully depleted silicon on insulator FDSOI), has found to make the silicon island to become extremely thin in order to exhaust this silicon island fully and to produce.
Yet thin silicon island exhausts in the silicon-on-insulator complementary metal oxide semiconductors (CMOS) (FDSOI CMOS) entirely in making, and forms the source electrode during with drain electrode with low parasitic series resistance, can have problems.A solution is that source electrode and drain electrode are promoted on this thin silicon island.(selective epitaxial growth, mode SEG) form the source electrode and the drain electrode that promote with selective epitaxial growth.But unfortunately, on silicon island as thin as a wafer, be difficult to grow equably source electrode and drain electrode high-quality, monocrystalline.In addition, before selective epitaxial growth, when carrying out baking processing procedure, can remove all or the required thin silicon of selective epitaxial growth partly such as oxidation, pre-cleaning (pre-clean) and hydrogen.
Another important topic of making FDSOI CMOS is for improving the mechanism of performance.A kind of method of improving performance is to introduce tensile strain or compressive strain to raceway groove.Along the elongation strain of direction of current flow, increased the mobility in electronics and electric hole.On the other hand, compression strain has increased the mobility in electric hole but has made the movement of electrons reduction.The filling of mat channel separating zone and strain is guided into to raceway groove.Yet the manufacturing of FDSOI CMOS is to use the platform-type isolation that does not have ditch trench etch and filling traditionally.
Therefore, when when raceway groove produces strain, need the method for the even growing high quality of a kind of energy, single crystalline source and drain electrode.
How to overcome above-mentioned those problems and inquire into for a long time for people, but previous exploitation teaching or advise any solution not, so, be familiar with the method that this area person looks forward to having those problems of solution for a long time.
Summary of the invention
The invention provides a kind of Semiconductor substrate that has insulator thereon, and on this insulator semiconductor layer is arranged.Form deep trench isolation, produce strain at this semiconductor layer.On this semiconductor layer, form gate-dielectric and grid.Form interval body around this grid, and this semiconductor layer and this insulator of this interval body outside removed.At outside concave type (recessed) source/drain that forms of this interval body.
Certain embodiments of the invention have except that the above, or substitute above-described other advantage.To being familiar with this area person, read following detailed explanation and with reference to the accompanying drawings after, these advantages will become clearly.
Description of drawings
Fig. 1 is the profile of fully depleted silicon on insulator semiconductor wafer;
Be formed with grid on the structure of Fig. 2 displayed map 1;
Deposit linear zone and interval body on the structure of Fig. 3 displayed map 2;
Fig. 4 shows Fig. 3 structure with concave type source/drain according to embodiments of the invention;
Fig. 5 shows Fig. 4 structure after the silication of carrying out according to embodiments of the invention;
Fig. 6 shows Fig. 5 structure with contact etch stop layer according to another embodiment of the present invention; And
Fig. 7 is the flow chart according to the method for manufacturing strained fully depleted silicon on insulator semiconductor device of the present invention.
Embodiment
Below explanation will provide many clear and definite details, enable fully to understand the present invention.Yet the present invention must not implement in having under those clear and definite details obviously.For fear of fuzzy the present invention, some well-known device configurations and fabrication steps will no longer be described in detail
Similarly, the figure of display unit embodiment is half signal formula but not draw in proportion, and the size among some figure particularly is for making clear excessive amplification of explanation.
Used in this specification " horizontal plane (horizontal) " speech is defined as the plane parallel with substrate or wafer." vertically " speech, refer to as the vertical direction of the defined horizontal plane of preceding paragraph.Other term such as " go up ", " above (above) ", " following (below) ", " bottom ", " top ", " side (as " sidewall "), " higher ", " lower ", " on (over) ", " under (under) " all refer to respect to the horizontal plane.
Used in this specification " processing (processing) " speech, when forming described structure, required step comprises: the deposition of material or photoresistance, patterning, exposure, development, etching, cleaning (cleaning) and/or remove this material or photoresistance.
Fig. 1 shows the profile that exhausts silicon-on-insulator (FDSOI) wafer 100 entirely, comprises such as be the Semiconductor substrate 102 of the material of p doped silicon (Si).Imbed on Semiconductor substrate 102 tops oxide layer (buried oxide layer, BOX) 104, this imbeds oxide layer 104 is silicon dioxide (SiO for example 2) the insulating barrier of material; And the channel layer 106 of silicon thin layer.
In order to control 45 nanometers with 25 nanometers (nm) or littler grid length and 45 nanometers, found that channel layer 106 thickness must be thinner than 100 dusts () with the short-channel effect of lower node.
With the isolated deep trench isolation that is positioned at concave type source/drain 402 outside (see figure 4)s (deep trench isolation, DTI) 108, add to and exhaust silicon-on-insulator wafer 100 entirely.Formation has the deep trench isolation 108 of zanjon etching (etching is passed channel layer 106, imbeds oxide layer 104 and entered substrate 102).Be the isolation of holding device, the degree of depth of deep trench isolation must be greater than concave type source/drain 402 (see figure 4)s.Insert for example SiO at the zanjon that produces 2The dielectric medium of material, to finish the making of deep trench isolation 108.
The structure of Fig. 2 displayed map 1 and forms by such as SiO after commonly using deposition, patterning, photoetching and etch process 2, silicon oxynitride (silicon oxynitride, SiON) or silicon nitride (Si 3N 4) the gate-dielectric that material constituted 202, and by such as may be through mixing or the grid that material constituted 204 of unadulterated compound crystal silicon or amorphous silicon (amorphous silicon).
Fig. 3 shows Fig. 2 structure after further processing.(recess etch) preparation that concavelys etch of deep trench isolation 108 is used to the deep trench isolation 108 interior wafers 100 that form interval body.Material is SiO for example 2 Linear zone 302 be to be deposited on grid 204, channel layer 106 and the deep trench isolation 108.Material is Si for example 3N 4Interval body 304 be around the grid part of linear zone 302 and formation deep trench isolation 108 in.
Make one of important topic of FDSOI CMOS, promptly form source electrode and drain electrode with low parasitic series resistance.A solution is that source electrode and drain electrode are promoted.Can form source electrode and the drain electrode that promotes by selective epitaxial growth.Unfortunately, on silicon island as thin as a wafer, on channel layer 106, be difficult to grow equably source electrode and drain electrode high-quality, monocrystalline.In addition, before selective epitaxial growth, carry out baking processing procedure, can remove all or the required thin silicon of selective epitaxial growth partly such as oxidation, precleaning and hydrogen.
Fig. 4 shows according to the Fig. 3 after the processing of the present invention's embodiment and constructs.Concave type source/drain 402 has added to and has exhausted silicon-on-insulator wafer 100 entirely.Channel layer 106 is etched and form raceway groove 404.
Be to form concave type source/drain 402, and use suitable processing procedure such as etching, to pass the channel layer 106 that is positioned at grid 204 and 108 of deep trench isolation and to imbed oxide layer 104.The thin oxide layer 104 of imbedding of having found 100  to 600  provides best thickness.On the sidewall of the surface of substrate 102 and raceway groove 404, carry out selective epitaxial growth (SEG) then.Even this guarantee when the silicon of channel layer 106 can part or even when all be previous process consumption, the selective epitaxial growth of concave type source/drain 402 has continuous, high-quality silicon face.
During the problem of selective epitaxial growth, the structure of generation is possessed the advantage that promotes source/drain on overcoming thin silicon, for example low parasitic series resistance.In this stage, the modification of the selective epitaxial growth of mat concave type source/drain 402 can make performance improvement.
Fig. 5 shows according to Fig. 4 structure after the further processing of the present invention's embodiment.On grid 204 and source/drain 402, carry out silicification reaction to generate NiSi layer 504.
Should understand that the order system that forms concave type source/drain 402 and deep trench isolation 108 can change, and the above is cause for convenience in proper order.Concave type source/drain 402 can be implanted (in situ) formation on the spot with Rapid Thermal tempering (thermal anneal) during concave type source/drain 402 selective epitaxial growths or by ion.Through the groove filling dielectric medium of strained handling, deep trench isolation 108 leads strain in raceway groove 404, and is fit to as the isolation between transistor.
Elongation strain or compression strain are directed in the raceway groove of FDSOI CMOS device to improve performance.Along the elongation strain of direction of current flow, electronics and electric hole mobility among the NMOS are all increased.On the other hand, the compression strain mat increases electric hole mobility and improves the performance of PMOS.Thus, applying suitable strain significantly increases the raceway groove mobility to raceway groove 404, and the result increases by the mobility of signal portion, and drive current is improved.
Be found in the FDSOI PMOS transistor, (silicon germanium, selective epitaxial growth SiGe) can further improve strain by SiGe.Thus, the SiGe of concave type source/drain 402 produces strain effectively in the transistorized raceway groove 404 of FDSOI PMOS.Because therefore concave type source/drain 402 next-door neighbour's raceway grooves 404, and the more strain of strain in the source/drain of importing specific energy importing lifting also make this should change effectively.
In addition, found in the FDSOI nmos pass transistor that (siliconcarbide, selective epitaxial growth SiC) can further improve strain by carborundum.Thus, the SicC of concave type source/drain produces strain effectively in the raceway groove 404 of FDSOI nmos pass transistor.Because concave type source/drain 402 next-door neighbour raceway grooves 404, and can import specific energy and import the more strain of strain in the source/drain that promotes, therefore this should be changed effectively.
Above strain control can be implemented auxiliary (adjunct) that controls as from the strain of deep trench isolation 108, or as before 402 formation of concave type source/drain, the basic controlling that deep trench isolation 108 forms.
Fig. 6 shows according to Fig. 5 structure after the further processing of another embodiment of the present invention.The dielectric medium charges of interval body 304 (see figure 5)s and deep trench isolation 108 (see figure 5)s are removed through etching step, stay groove 602.After the etching, contact etch stop layer 604 is deposited in the groove 602 and on source/drain 402, linear zone 302 and grid 204.Contact etch stop layer 604 in the groove 602 imports raceway groove 404 with other strain.
Fig. 7 shows the flow chart according to the method 700 of the present invention's manufacturing strained fully depleted silicon on insulator semiconductor device.Method 700 is included in the step 702, and the Semiconductor substrate that has insulator on it is provided, and wherein has semiconductor layer on this insulator; In step 704, on this semiconductor layer, form gate-dielectric and grid; In step 706, form isolated deep trench isolation in the interval body outside, and strain is guided into to this semiconductor layer; In step 708, form interval body around this grid; In step 710, remove this semiconductor layer and this insulator of this interval body outside; And in step 712, at the outside concave type source/drain that forms of this interval body.
So, found semiconductor device of the present invention and manufacture method, to FDSOI CMOS provide important and not known as yet up to now or solution, ability and the function used on advantage.The processing procedure of this gained and configuration system is direct, economical, uncomplicated, high flexibility, accurately, sensitive and effectively, and can be applicable to known assembly and go easily to make and application.
With reference to specific most preferred embodiment, this specification discloses the present invention.Should understand that many changes, modification and variation are for being familiar with this area person, above explanation will make it become clearly.Therefore, all those changes, modification and variation all are covered by in the following claim.The interior accompanying drawing that perhaps shows that is disclosed in this specification is to be used to explain the present invention, but not is used to limit category of the present invention.

Claims (10)

1. a method (700) of making semiconductor device comprises the following steps:
The Semiconductor substrate that has insulator (104) thereon (102) is provided, semiconductor layer (106) is arranged on this insulator (104);
Form deep trench isolation (108), strain is introduced into this semiconductor layer (106);
Go up formation gate-dielectric (202) and grid (204) at this semiconductor layer (106);
Form interval body (304) around this grid (204);
Remove at this interval body (304) outside this semiconductor layer (106) and this insulator (104); And
At the outside concave type source/drain (402) that forms of this interval body (304).
2. the method for claim 1 (700), wherein, further comprise by selective epitaxial growth at the outside concave type source/drain (402) that forms of this interval body (304) in the outside step that forms concave type source/drain (402) of this interval body (304).
3. the method for claim 1 (700), wherein, further be included in the outside silicon source/drain electrode (402) that forms the doping of concave type carbon of this interval body (304) in the outside step that forms concave type source/drain (402) of this interval body (304), strain is introduced into this semiconductor layer (106).
4. the method for claim 1 (700), wherein, further be included in the outside formation of this interval body (304) concave type silicon Germanium source/drain electrode (402) in the outside step that forms concave type source/drain (402) of this interval body (304), strain is introduced into this semiconductor layer (106).
5. the method for claim 1 (700) comprises in addition:
Remove this interval body (304);
Remove this deep trench isolation (108), stay groove (602); And
In this groove (602), this concave type source/drain (402) is gone up and this grid (204) is gone up sedimentary deposit (604), and strain is introduced into this semiconductor layer (106).
6. semiconductor device comprises:
Have the Semiconductor substrate (102) of insulator (104) thereon, semiconductor layer (106) is arranged on this insulator (104);
Gate-dielectric (202) on this semiconductor layer (106) and grid (204);
Optionally center on the interval body (304) of this grid (204);
At the outside concave type source/drain (402) of this interval body (304); And
At the outside isolated groove (602) of this interval body (304), as deep trench isolation (108) strain is introduced into this silicon layer alternatively.
7. semiconductor device as claimed in claim 6 wherein, further comprises the concave type source/drain (402) that is formed on this interval body (304) outside by selective epitaxial growth at this outside concave type source/drain (402) of this interval body (304).
8. semiconductor device as claimed in claim 6, wherein, further comprise the silicon source/drain electrode (402) that strain is introduced into this semiconductor layer (106) at this outside concave type source/drain (402) of this interval body (304) in the outside concave type carbon doping of this interval body (304).
9. semiconductor device as claimed in claim 6, wherein, further comprise the concave type silicon Germanium source/drain electrode (402) that strain is introduced into this semiconductor layer (106) at this outside concave type source/drain (402) of this interval body (304) in this interval body (304) outside.
10. semiconductor device as claimed in claim 6, comprise in addition with strain be introduced into this semiconductor layer (106) in this groove (602), this concave type source/drain (402) is gone up and this grid (204) on layer.
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