CN102487018B - MOS transistor and formation method thereof - Google Patents
MOS transistor and formation method thereof Download PDFInfo
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- CN102487018B CN102487018B CN201010573301.5A CN201010573301A CN102487018B CN 102487018 B CN102487018 B CN 102487018B CN 201010573301 A CN201010573301 A CN 201010573301A CN 102487018 B CN102487018 B CN 102487018B
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Abstract
The invention provides an MOS transistor and a formation method thereof. The method comprises the following steps: providing a semiconductor substrate; patterning the semiconductor substrate to form a groove; forming a spacer on a sidewall of the groove; oxidizing a bottom of the groove, and forming an oxide layer at the bottom of the groove; removing the spacer, forming semiconductor material in the groove, and covering the oxide layer, wherein, a surface of the semiconductor material is level with a surface of the semiconductor substrate; forming a gate structure at the surface of the semiconductor material, wherein, the gate structure comprises a gate which is on a gate dielectric layer between the gate and the surface of the semiconductor material. According to the MOS transistor and the formation method of the invention, generation of leakage current can be prevented, or at least the leakage current can be reduced. And, technology of forming the oxide layer is simple, and control is easy.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to and form MOS transistor and method thereof.
Background technology
MOS transistor comprises: grid, and the gate dielectric layer between grid and substrate, source region and ，Qie source region, drain region and drain region easily produce leakage current.The existence of this leakage current can affect the performance of the semiconductor device of final formation.
The United States Patent (USP) that publication number is " US7572712B2 " discloses a kind of method that forms nmos pass transistor.Fig. 1 a～Fig. 1 e is the cross-sectional view that prior art forms MOS transistor method.
With reference to figure 1a, Semiconductor substrate 10 is provided, in described conductive substrate 10, form silicon oxide layer 11 and silicon nitride layer 12, described silicon oxide layer 11 is positioned in described Semiconductor substrate 10, and described silicon nitride layer 12 is positioned on described silicon oxide layer 11.Utilize the graphical silicon oxide layer 11 of photoetching process and silicon nitride layer 12, define the figure of groove; Take patterned silicon oxide layer 11 and silicon nitride layer 12 is mask, and etching conductive substrate 10 forms groove 13.
With reference to figure 1b, fill stress material, cover the surface of described silicon nitride layer 12, and fill up groove 13; Afterwards, utilize chemical-mechanical planarization (CMP) to remove the surperficial stress material of silicon nitride layer 12, and exceed the stress material in the surperficial groove 13 of silicon nitride layer 12, at the interior surface stress material 14 equal with the surface of silicon nitride layer 12 that form of groove 13.
With reference to figure 1c, the silicon nitride layer 12 of take is carved stress material 14 as mask returns, and makes the surface of stress material 14 lower than the surface of Semiconductor substrate 10.
With reference to figure 1d, utilize epitaxial growth method, along stress material 14 surface level epitaxial growth epitaxial loayers 15, the surface of epitaxial loayer 15 is equal with the surface of Semiconductor substrate 10.The material of epitaxial loayer 15 is other semi-conducting materials such as silicon, carbon doped silicon or germanium silicon, and epitaxial loayer 15 is in mos transistor structure, as the raceway groove between source region and drain region.
Afterwards, with reference to figure 1e and in conjunction with reference to figure 1d, remove silicon nitride layer 12 and silicon oxide layer 11.Can form the grid structure that comprises grid 16, gate dielectric layer 17 and side wall 18 on the surface of epitaxial loayer 15.
The method of the formation MOS transistor of above-described prior art, stress material 14 avoids producing leakage current as isolation structure, or at least can reduce the leakage current of generation.
Yet along with the development of semiconductor technology, (CD) is more and more less for the characteristic size of device, therefore, when the interior filling stress material of groove 13, easily form gap, the existence in gap can affect the growth of epitaxial loayer 15; And, form the method complexity of the stress material of predetermined thickness, need first in groove, to fill up stress material, then utilize CMP technique to remove the stress material that exceeds silicon nitride layer 12 surfaces, then, return quarter, remove the stress material of groove 13 interior certain altitudes, the final stress material 14 that forms predetermined altitude, complex process.
Summary of the invention
The problem that the present invention solves is the method for the formation MOS transistor of prior art, easily produces space during isolation structure under forming raceway groove; And the complex process of formation raceway groove below isolation structure.
For addressing the above problem, the invention provides a kind of method that forms MOS transistor, comprising:
Semiconductor substrate is provided;
Graphical described Semiconductor substrate, forms groove;
Sidewall at described groove forms side wall;
Be oxidized described bottom portion of groove, in the bottom of described groove, form oxide layer;
Remove described side wall, in described groove, form semi-conducting material, cover described oxide layer, the surface of described semi-conducting material is equal with the surface of described Semiconductor substrate;
On described semiconductor material surface, form grid structure, described grid structure comprises: grid, the gate dielectric layer between described grid and described semiconductor material surface.
Optionally, utilize epitaxial growth method to form semi-conducting material in described groove.
Optionally, described epitaxial growth method be selected from rapid heat chemical vapour deposition, high vacuum chemical vapour deposition, molecular beam epitaxy one of them.
Optionally, in oxygen atmosphere, utilize thermal oxidation to form oxide layer at described bottom portion of groove.
Optionally, in oxygen atmosphere, utilize plasma oxidation to form oxide layer at described bottom portion of groove.
Optionally, the material of described side wall is silicon nitride.
Optionally, the degree of depth of described groove is 200 dust-2000 dusts.
Optionally, the sidewall of described groove depart from bottom angle be greater than 85 °.
Optionally, the thickness of described oxide layer is 20 dust-1000 dusts.
Optionally, described graphical described Semiconductor substrate, forms groove and comprises:
In described Semiconductor substrate, form hard mask layer;
Graphical described hard mask layer, forms patterned hard mask layer, defines the figure of groove;
The described patterned hard mask layer of take is mask, and Semiconductor substrate described in etching forms groove.
Optionally, described hard mask layer comprises: silicon oxide layer and silicon nitride layer, and described silicon oxide layer is positioned in described Semiconductor substrate, and described silicon nitride layer is positioned on described silicon oxide layer.
Optionally, the described sidewall at described groove forms side wall and comprises:
Form insulating barrier, cover the surface of described patterned hard mask layer, the bottom of described groove and sidewall;
Return to carve and remove the surface of described patterned hard mask layer and the insulating barrier of bottom portion of groove, at the sidewall formation side wall of described groove.
The present invention also provides a kind of MOS transistor, comprising:
Semiconductor substrate;
Groove, is formed at described Semiconductor substrate;
Oxide layer, is formed at the bottom of described groove;
Semi-conducting material, is formed in described groove, and covers described oxide layer, and the surface of described semi-conducting material is equal with the surface of described Semiconductor substrate;
Grid structure, is formed on described semiconductor material surface, and described grid structure comprises: grid, the gate dielectric layer between described grid and described semiconductor material surface.
Optionally, comprising: the degree of depth of described groove is 200 dust-2000 dusts.
Optionally, the sidewall of described groove depart from bottom angle be greater than 85 °.
Optionally, the thickness of described oxide layer is 20 dust-1000 dusts.
Compared with prior art, the present invention has the following advantages:
The present invention forms the method for MOS transistor, in Semiconductor substrate, forms groove; Sidewall at described groove forms side wall; Be oxidized described bottom portion of groove, in the bottom of described groove, form oxide layer, this oxide layer can be used as the generation that isolation structure prevents leakage current, or at least can reduce leakage current; Remove described side wall, in described groove, form semi-conducting material, cover described oxide layer, the surface of described semi-conducting material is equal with the surface of described Semiconductor substrate; Afterwards, on the semi-conducting material above oxide layer, can form the grid structure that comprises grid and gate dielectric layer.Owing to utilizing the method for oxidation to form oxide layer, therefore can in oxide layer, not form gap; And, only need temperature, the time of controlling oxidation just can control the height of oxide layer, therefore form technique simple.
MOS transistor of the present invention, forms groove in Semiconductor substrate; Oxide layer is formed on the bottom at described groove, and this oxide layer can be used as the generation that isolation structure prevents leakage current, or at least can reduce leakage current.
Accompanying drawing explanation
Fig. 1 a～Fig. 1 e is the cross-sectional view that prior art forms MOS transistor method.
Fig. 2 is the flow chart of method of the formation MOS transistor of the specific embodiment of the present invention;
The cross-sectional view of the method for the formation MOS transistor that Fig. 3 a～Fig. 3 h is the specific embodiment of the invention.
Embodiment
The method of the formation MOS transistor of the specific embodiment of the invention, forms groove in Semiconductor substrate; Sidewall at described groove forms side wall; Be oxidized described bottom portion of groove, in the bottom of described groove, form oxide layer, this oxide layer can be used as the generation that isolation structure prevents leakage current, or at least can reduce leakage current; Remove described side wall, in described groove, form semi-conducting material, cover described oxide layer, the surface of described semi-conducting material is equal with the surface of described Semiconductor substrate; Afterwards, on the semi-conducting material above oxide layer, can form the grid structure that comprises grid and gate dielectric layer.Owing to utilizing the method for oxidation to form oxide layer, therefore can in oxide layer, not form gap; And, only need temperature, the time of controlling oxidation just can control the height of oxide layer, therefore form technique simple.
For those skilled in the art be can better understand the present invention, below in conjunction with accompanying drawing, describe the specific embodiment of the present invention in detail.
Fig. 2 is the flow chart of method of the formation MOS transistor of the specific embodiment of the present invention, ginseng figure Fig. 2, and the method for the formation MOS transistor of the specific embodiment of the invention comprises:
Step S21, provides Semiconductor substrate;
Step S22, graphical described Semiconductor substrate, forms groove;
Step S23, at the sidewall formation side wall of described groove;
Step S24, is oxidized described bottom portion of groove, in the bottom of described groove, forms oxide layer;
Step S25, removes described side wall, in described groove, forms semi-conducting material, covers described oxide layer, and the surface of described semi-conducting material is equal with the surface of described Semiconductor substrate;
Step S26 forms grid structure on described semiconductor material surface, and described grid structure comprises: grid, the gate dielectric layer between described grid and described semiconductor material surface.
The cross-sectional view of the method for the formation MOS transistor that Fig. 3 a～Fig. 3 h is the specific embodiment of the invention, in order to make those skilled in the art can better understand the present invention the method for the formation MOS transistor of embodiment, below in conjunction with specific embodiment combination, referring to figs. 2 and 3 a～Fig. 3 h, describe the method for the formation MOS transistor of the specific embodiment of the invention in detail.
In conjunction with reference to figure 2 and Fig. 3 a, perform step S21, Semiconductor substrate 30 is provided.The material of described Semiconductor substrate 30 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, III-V group element compound, monocrystalline silicon carbide or silicon-on-insulator (SOI) structure.In substrate 30, can be formed with device architecture (not shown), for example isolation trench structure.In the specific embodiment of the invention, described Semiconductor substrate 30 is monocrystalline silicon, and its indices of crystallographic plane are (100), (110) or (111).
In conjunction with reference to figure 2 and Fig. 3 c, perform step S22, graphical described Semiconductor substrate, forms groove.In the specific embodiment of the invention, graphical described Semiconductor substrate 30, forms groove 33 and comprises:
With reference to figure 3b, in described Semiconductor substrate 30, form hard mask layer 32; Graphical described hard mask layer 32, forms patterned hard mask layer 32, defines the figure (in conjunction with Fig. 3 c) of groove 33.In the specific embodiment of the invention, described hard mask layer 32 comprises: silicon oxide layer 321 and silicon nitride layer 322, and described silicon oxide layer 321 is positioned in described Semiconductor substrate 30, and described silicon nitride layer 322 is positioned on described silicon oxide layer 321.Wherein, silicon oxide layer 321 is as the stress-buffer layer between silicon nitride layer 322 and Semiconductor substrate 30.In other embodiments, hard mask layer 32 can be also single layer structure.The method of graphical described hard mask layer 32 is: on hard mask layer 32, form photoresist layer, on silicon nitride layer 322, form photoresist layer, the method that forms photoresist layer can be spin-coating method, drop-coating or spread coating, utilizes spin-coating method to form photoresist layer in the specific embodiment of the invention.Afterwards, photoresist layer is exposed, developed, form patterned photoresist layer, define the figure of groove; Then, utilize and take patterned photoresist layer as mask etching hard mask layer 32, the figure on patterned photoresist layer is transferred to hard mask layer 32, form patterned hard mask layer 32.
With reference to figure 3c, the described patterned hard mask layer 32 of take is mask, and Semiconductor substrate 30 described in etching forms groove 33.In the specific embodiment of the invention, utilize dry etching Semiconductor substrate 30 to form groove 33.And in the specific embodiment of the invention, the degree of depth of described groove 33 is 200 dust-2000 dusts, the angle that the sidewall of groove 33 departs from bottom is greater than 85 °.
In conjunction with reference to figure 2 and Fig. 3 d, perform step S23, at the sidewall formation side wall 34 of described groove 33.In the specific embodiment of the invention, form side wall 34 and be specially: form insulating barrier, cover the surface of described patterned hard mask layer 32, bottom and the sidewall of described groove 33; Return to carve and remove the surface of described patterned hard mask layer 32 and the insulating barrier of groove 33 bottoms, at the sidewall formation side wall 34 of described groove.This side wall 34 is as separator, guarantee after while being oxidized the bottom of groove 33, the Semiconductor substrate 30 of sidewall is not oxidized.In the specific embodiment of the invention, the material of described side wall 34 is silicon nitride.The method that forms insulating barrier is chemical vapour deposition (CVD) (CVD), on the surface of described patterned hard mask layer 32,, the bottom of described groove 33 and sidewall form after insulating barrier, utilizes dry etching to return and carves insulating barrier formation side wall 34.
In conjunction with reference to figure 2 and Fig. 3 e, perform step S24, be oxidized described groove 33 bottoms, in the bottom of described groove 33, form oxide layer 35.This oxide layer 35 after technique in by semi-conducting material, covered, its top forms the raceway groove between source region and drain region.The source region forming after this oxide layer 35 can be used as and the isolation structure between drain region, namely the isolation structure of raceway groove below, avoids the generation of leakage current, or at least can reduce leakage current.In the specific embodiment of the invention, can, in oxygen atmosphere, utilize thermal oxidation to form oxide layer 35 in described groove 33 bottoms.Also can, in oxygen atmosphere, utilize plasma oxidation to form oxide layer 35 in described groove 33 bottoms.The thickness of described oxide layer 35 is 20 dust-1000 dusts, the thickness of the parameter control oxide layers 35 such as the temperature that can be oxidized by control, time is height in other words, in concrete technique, select according to actual needs suitable parameter, generate the oxide layer 35 of suitable thickness.In the specific embodiment of the invention, the material of Semiconductor substrate 30 is monocrystalline silicon, and oxide layer 35 is silicon dioxide in the specific embodiment of the invention.In other embodiments of the invention, the material of Semiconductor substrate 30 is other semi-conducting material if, can generate the oxide layer of respective material, and this does not describe in detail, those skilled in the art, according to those skilled in the art's common practise, can know the material of the oxide layer 35 of formation by inference.
In conjunction with reference to figure 2 and Fig. 3 f, Fig. 3 g-1, Fig. 3 g-2, Fig. 3 g-3, and combination is with reference to figure 3e, execution step S25, remove described side wall 34, at the interior formation semi-conducting material 36 of described groove 33, cover described oxide layer 35, the surface of described semi-conducting material 36 is equal with the surface of described Semiconductor substrate 30; Described semi-conducting material is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, III-V group element compound, monocrystalline silicon carbide.In the specific embodiment of the invention, described semi-conducting material 36 monocrystalline silicon.
In the concrete enforcement of the present invention, in example, utilize epitaxial growth method to cover described oxide layer 35 at the interior formation semi-conducting material 36 of described groove 33, the surface of described semi-conducting material 36 is equal with the surface of described Semiconductor substrate 30.Described epitaxial growth method is selected from: rapid heat chemical vapour deposition, high vacuum chemical vapour deposition, molecular beam epitaxy one of them.In the specific embodiment of the invention, adopt the horizontal epitaxial growth method in epitaxial growth method to generate semi-conducting material 36.Fig. 3 g-1, Fig. 3 g-2, Fig. 3 g-3 have shown the growth course of semi-conducting material 36, the direction of growth along continuous straight runs of semi-conducting material 36, namely along the surface direction of oxide layer 35, semi-conducting material 36 is very slow in the speed of growth of vertical-horizontal direction, namely the speed of growth of the surface direction of vertical oxide layer 35 is very slow, the ratio of the speed of growth of horizontal direction and vertical-horizontal direction is 1: 0～1: 0.2, in the specific embodiment of the invention, and preferably 1: 0～1: 0.1.Epitaxially grown semi-conducting material 36 is as the raceway groove in mos transistor structure.Because semi-conducting material 36 is as raceway groove, can carry out Implantation, adjusting threshold voltage to semi-conducting material 36.
In conjunction with reference to figure 2 and Fig. 3 h, perform step S26, on the surface of described semi-conducting material 36, form grid structure, described grid structure comprises: grid 37, the gate dielectric layer 38 between described grid 37 and described semi-conducting material 36 surfaces.Grid structure also comprises side wall 39, is positioned at around grid 37 and gate dielectric layer 38.The common practise that the method that forms grid structure is those skilled in the art, is not described in detail at this.Can carry out Implantation to Semiconductor substrate 30 afterwards, form source region and drain region (not shown), and other semiconductor back-end techniques, plug and interconnection line formed.
MOS transistor in the present invention can be PMOS transistor, can be also nmos pass transistor.
Fig. 3 h is the cross-sectional view of the MOS transistor of formation, and with reference to figure 3h, MOS transistor of the present invention, comprising: Semiconductor substrate 30; Groove, is formed at described Semiconductor substrate 30; Oxide layer 35, is formed at the bottom of described groove; Semi-conducting material 36, is formed in described groove, and covers described oxide layer 35, and the surface of described semi-conducting material 36 is equal with the surface of described Semiconductor substrate 30; Grid structure, is formed on described semiconductor material surface, and described grid structure comprises: grid 37, the gate dielectric layer 38 between described grid 37 and described semi-conducting material 36 surfaces.In the specific embodiment of the invention, grid structure also comprises source region and drain region (not shown), is positioned at described Semiconductor substrate 30 and is positioned at the both sides of described semi-conducting material 35.
In the specific embodiment of the invention, the degree of depth of described groove is 200 dust-2000 dusts, and the angle that the sidewall of described groove departs from bottom is greater than 85 °, and the thickness of described oxide layer is 20 dust-1000 dusts.
MOS transistor of the present invention, forms groove in Semiconductor substrate; Oxide layer is formed on the bottom at described groove, and this oxide layer can be used as the generation that isolation structure prevents leakage current, or at least can reduce leakage current.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. a method that forms MOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
Graphical described Semiconductor substrate, forms groove;
Sidewall at described groove forms side wall;
Be oxidized described bottom portion of groove, in the bottom of described groove, form oxide layer;
Remove described side wall, in described groove, form semi-conducting material, cover described oxide layer, the surface of described semi-conducting material is equal with the surface of described Semiconductor substrate;
On described semiconductor material surface, form grid structure, described grid structure comprises: grid, the gate dielectric layer between described grid and described semiconductor material surface.
2. the method for formation MOS transistor as claimed in claim 1, is characterized in that, utilizes epitaxial growth method to form semi-conducting material in described groove.
3. the method for formation MOS transistor as claimed in claim 2, is characterized in that, described epitaxial growth method be selected from rapid heat chemical vapour deposition, high vacuum chemical vapour deposition, molecular beam epitaxy one of them.
4. the method for formation MOS transistor as claimed in claim 1, is characterized in that, in oxygen atmosphere, utilizes thermal oxidation to form oxide layer at described bottom portion of groove.
5. the method for formation MOS transistor as claimed in claim 1, is characterized in that, in oxygen atmosphere, utilizes plasma oxidation to form oxide layer at described bottom portion of groove.
6. the method for formation MOS transistor as claimed in claim 1, is characterized in that, the material of described side wall is silicon nitride.
7. the method for formation MOS transistor as claimed in claim 1, is characterized in that, the degree of depth of described groove is 200 dust-2000 dusts.
8. the method for formation MOS transistor as claimed in claim 1, is characterized in that, the angle that the sidewall of described groove departs from bottom is greater than 85 °.
9. the method for the formation MOS transistor as described in claim 1～7 any one, is characterized in that, the thickness of described oxide layer is 20 dust-1000 dusts.
10. the method for the formation MOS transistor as described in claim 1～7 any one, is characterized in that, described graphical described Semiconductor substrate forms groove and comprises:
In described Semiconductor substrate, form hard mask layer;
Graphical described hard mask layer, forms patterned hard mask layer, defines the figure of groove;
The described patterned hard mask layer of take is mask, and Semiconductor substrate described in etching forms groove.
The method of 11. formation MOS transistor as claimed in claim 10, is characterized in that, described hard mask layer comprises: silicon oxide layer and silicon nitride layer, and described silicon oxide layer is positioned in described Semiconductor substrate, and described silicon nitride layer is positioned on described silicon oxide layer.
The method of 12. formation MOS transistor as claimed in claim 10, is characterized in that, the described sidewall at described groove forms side wall and comprises:
Form insulating barrier, cover the surface of described patterned hard mask layer, the bottom of described groove and sidewall;
Return to carve and remove the surface of described patterned hard mask layer and the insulating barrier of bottom portion of groove, at the sidewall formation side wall of described groove.
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