CN105742248A - Method for forming semiconductor structure - Google Patents
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- CN105742248A CN105742248A CN201410748773.8A CN201410748773A CN105742248A CN 105742248 A CN105742248 A CN 105742248A CN 201410748773 A CN201410748773 A CN 201410748773A CN 105742248 A CN105742248 A CN 105742248A
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Abstract
The invention discloses a method for forming a semiconductor structure. The method comprises the steps: firstly providing a semiconductor substrate which is provided with an isolation structure; forming a first pseudo grid and a second pseudo grid on the semiconductor substrate, wherein at least a part of the first and second pseudo grids is located above the isolation structure; carrying out the etching of the isolation structure, so as to form a groove on the surface of the isolation structure. Afterwards, when a first main side wall and a second main side wall are formed, the first and second main side walls can be formed on inner walls of the groove, thereby protecting a high-K dielectric layer and a cap cover layer from being corroded by sulfuric acid in a subsequent process of removing a residual metal layer through sulfuric acid, preventing the semiconductor structure from being ineffective, and improving the yield of the semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the forming method of a kind of semiconductor structure.
Background technology
In conventional semiconductor processing techniques, adopt silicon oxide (SiO more2) and the gate stack structure that constitutes of polysilicon (poly-Si).Reduction along with the characteristic size of semiconductor structure, in order to significantly reduce grid leakage current and resistance, eliminate poly-Si depletion effect, improve device reliability, alleviate fermi level pinning effect, adopt high K (dielectric constant) dielectric layer (highK, and metal gates (metalgate HK), MG) gate stack structure replaces traditional silicon oxide and polysilicon gate stacked structure to become the common recognition of industry, therefore, HKMG Technology is extensively developed.
In HKMG technique, high-K dielectric layer and metal gates are most important two components, and generally also can make cap layer between high-K dielectric layer and metal gates.The effect of cap layer at least includes two aspects, on the one hand in order to protect high-K dielectric layer, is used for preventing cross-diffusion between metal gates and high-K dielectric layer on the other hand.It follows that cap layer also is able to prevent the metal in metal gates from spreading to active area.
Consider that the raising of semiconductor structure yield, cap layer and high-K dielectric layer increasingly become a success or failure factors in HKMG technique.But, in the forming method of existing semiconductor structure, easily there is loss problem in cap layer and high-K dielectric layer, cause the inefficacy of semiconductor structure, reduce the yield of semiconductor structure.
Summary of the invention
The problem that this invention address that is to provide the forming method of a kind of semiconductor structure, to prevent cap layer and high-K dielectric layer generation loss, thus improving the yield of semiconductor structure.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including:
Thering is provided Semiconductor substrate, described Semiconductor substrate has isolation structure；
Forming the first dummy grid and the second dummy grid on the semiconductor substrate, described first dummy grid and the second dummy grid are at least partially disposed on described isolation structure；
Described isolation structure is performed etching process, to form groove on described isolation structure surface；
In described semiconductor substrate surface, described first dummy grid both sides, forming the master walling bed of material in described second dummy grid both sides and described groove, the described master walling bed of material fills described groove inner wall simultaneously；
Etching the described master walling bed of material, to form the first master wall in the first dummy grid both sides, form the second master wall in described second dummy grid both sides, described first master wall and the second master wall are concurrently formed at described groove inner wall.
Optionally, the depth bounds of described groove is。
Optionally, described etching processing includes at least one of wet etching, pattern-free dry etching and SiConi etching.
Optionally, the solution that described wet etching adopts is Fluohydric acid., and the mass concentration of described Fluohydric acid. ranges for 0.1%～10%.
Optionally, the temperature that described wet etching adopts is 20 DEG C～80 DEG C, and the time that described wet etching adopts is 30s～30min.
Optionally, the gas that described pattern-free dry etching adopts include CF4, CHF3, CH2F2 and CH3F at least one, or include CH4 and coordinate at least one in HCl, HBr and SO2 three.
Optionally, the temperature range that described pattern-free dry etching adopts is 20 DEG C～80 DEG C, and the pressure range of employing is 10mTorr～1000mTorr, and the power bracket of employing is 10w～3000w.
Optionally, before etching the described master walling bed of material, also comprise the steps:
Described first dummy grid forms the first hard mask layer, described second dummy grid forms the second hard mask layer；
In described etch processes, control the thickness loss of described first hard mask layer and the second hard mask layer less than or equal to。
Optionally, after filling and leading up layer described in being formed in described groove, also comprise the steps:
Metal level is formed at described semiconductor substrate surface；
Being annealed technique makes described metal level and Semiconductor substrate form metal silicide, and adopts sulphuric acid to remove the described metal level of residual.
Optionally, after adopting sulphuric acid to remove the described metal level of residual, also include the step adopting phosphoric acid to etch described first master wall and the second master wall.
Compared with prior art, technical scheme has the advantage that
In technical scheme, first Semiconductor substrate is provided, described Semiconductor substrate has isolation structure, then the first dummy grid and the second dummy grid are formed on a semiconductor substrate, first dummy grid and the second dummy grid are at least partially disposed at above isolation structure, afterwards isolation structure is performed etching process, to form groove on isolation structure surface, when being subsequently formed the first master wall and the second master wall, first master wall and the second master wall can be formed in groove inner wall, thus preventing from removing in the process of kish layer at follow-up employing sulphuric acid, high-K dielectric layer and cap layer are corroded by sulphuric acid, thus preventing semiconductor structure to lose efficacy, improve the yield of semiconductor structure.
Further, owing to high-K dielectric layer and cap layer are not corroded by sulphuric acid, it is thus possible to enough avoid the occurrence of metal gates protrusion to be diffused into the problems such as channel region with metal gates, and then prevent the semiconductor structure of periphery from affecting adversely, improve the yield of semiconductor structure further.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is each step counter structure schematic diagram of forming method of existing semiconductor structure；
Fig. 8 to Figure 15 is each step counter structure schematic diagram of forming method of the semiconductor structure that the embodiment of the present invention provides.
Detailed description of the invention
As described in background, the forming method of existing semiconductor structure can cause high-K dielectric layer and cap layer loss, and a series of harmful effects that high-K dielectric layer and cap layer loss bring, these harmful effects all can make semiconductor structure yield reduce.It is true that the loss that high-K dielectric layer and cap layer occur in semiconductor structure formation process, having become as in HKMG technique affects topmost a kind of negative effect factor of yield.
In anticipation, PMOS transistor typically requires the embedded germanium silicon technology step of experience, therefore, isolation structure for PMOS transistor region experienced by more etching process and cleaning process in technical process, namely the isolation structure loss of nmos pass transistor is less and the isolation structure loss of PMOS transistor is more, ought to the loss of the high-K dielectric layer of PMOS transistor and cap layer more.But, different from anticipation, the loss of high-K dielectric layer and cap layer is more to occur at nmos pass transistor but not PMOS transistor.
Through adopting transmission electron microscope (Transmissionelectronmicroscope; TEM) progressively detection; discovery reason is in that: in the wet clean process that embedded germanium silicon technology step is taked; the isolation structure of PMOS transistor has had extra master wall as protective layer, and namely the bottom part down in high-K dielectric layer and cap layer protected by corresponding master wall.Detailed process refer to Fig. 1 to Fig. 7, it is shown that the forming method of existing semiconductor structure.
Refer to Fig. 1, it is provided that Semiconductor substrate (does not mark), described Semiconductor substrate has isolation structure 101, and isolation structure 101 is used for isolating active area (mark).Forming the first dummy grid 111 and the second dummy grid 121 on the semiconductor substrate, described first dummy grid 111 and the second dummy grid 121 are at least partially disposed on described isolation structure 101.Also there is between first dummy grid 111 and Semiconductor substrate the first high-K dielectric layer (mark) and the first cap layer (mark), also there is between the second dummy grid 121 and Semiconductor substrate the second high-K dielectric layer (mark) and the second cap layer (mark).In Fig. 1, it is additionally included on the first dummy grid 111 and forms the first hard mask layer 112, the second dummy grid 121 is formed the second hard mask layer 122.Wherein, the first dummy grid 111 is the dummy grid for forming PMOS transistor, and the second dummy grid 121 is the dummy grid for forming nmos pass transistor.
It should be noted that in Fig. 1, it is shown that two the first dummy grids 111, it is limited with centre position, each first dummy grid 111 in the left side and the right；Two the second dummy grids 121, are limited with centre position, each second dummy grid 121 in the left side and the right.Usual each dummy grid is at least across being isolated two active region that structure 101 separates, thus, first dummy grid 111 and the second dummy grid 121 are all at least partially disposed at above isolation structure 101, therefore, in Fig. 1 in the profile position of display, first dummy grid 111 on the left side is positioned at above isolation structure 101, and first dummy grid 111 on the right is positioned at active region；Second dummy grid 121 on the left side is positioned at above isolation structure 101, and second dummy grid 121 on the right is positioned at active region.From another angle, two, left and right the first dummy grid 111 can also regard same first dummy grid 111 cross-section structure at diverse location as；In like manner, two, left and right the second dummy grid 121 can also regard same second dummy grid 121 cross-section structure at diverse location as.
Refer to Fig. 2, form the first offset side wall 113 in the first dummy grid 111 both sides, and the first offset side wall 113 is concurrently formed at the first hard mask layer 112 both sides；Form the second offset side wall 123 in the second dummy grid 121 both sides, and the second offset side wall 123 is concurrently formed at the second hard mask layer 122 both sides.
Refer to Fig. 3, form the first side wall 114 in the first dummy grid 111 both sides, now the first side wall 114 covers the first offset side wall 113 simultaneously；Forming the second side wall 124 in the second dummy grid 121 both sides, now the second side wall 124 covers the second offset side wall 123 simultaneously.
It should be noted that, the process forming the first side wall 114 and the second side wall 124 normally comprises the process forming embedded germanium silicon in PMOS transistor region, namely this processing step can be: forms spacer material layer (not shown), photoresist layer (not shown) is adopted to cover the spacer material layer being positioned at nmos transistor region, again with described photoresist for mask, the described spacer material layer that etching is not covered by described photoresist layer, to form the first side wall 114, and form groove (not shown) in the Semiconductor substrate of the first dummy grid 111 down either side simultaneously, stress germanium silicon is filled afterwards in described groove, to form embedded germanium silicon (mark)；Then, removing described photoresist layer, adopt another photoresist layer to cover PMOS transistor region, etching is positioned on nmos transistor region remaining described spacer material layer, to form the second side wall 124.In the process; the isolation structure 101 (i.e. the isolation structure 101 of the left side the first dummy grid 111 down either side in Fig. 3) in PMOS transistor region is owing to experienced by forming process and the cleaning process of described groove; depression 1011 would generally occur, as shown in Figure 3.
It should be noted that, though Fig. 3 is formed with depression on the isolation structure 101 of not shown second dummy grid 121 down either side, but in fact, on etching nmos transistor region, remaining described spacer material layer is to be formed in the process of the second side wall 124, the isolation structure 101 of the second dummy grid 121 down either side also has part and is depleted, thus forming shallower indentation structure (not shown).
Please continue to refer to Fig. 4, above the first hard mask layer 112, above the second hard mask layer 122, the first dummy grid 111 both sides, and the second dummy grid 121 both sides formation master walling bed of material 130.Now the master walling bed of material 130 covers the first side wall 114 and the second side wall 124.Further, now the master walling bed of material 130 can be concurrently formed at depression 1011 inwalls and described indentation inner structural wall.
Refer to Fig. 5, etch the master walling bed of material 130 shown in Fig. 4, until forming the first master wall 115 being positioned at the first dummy grid 111 both sides and the second master wall 125 being positioned at the second dummy grid 121 both sides.Depression 1011 shown in Fig. 4 can be carried out by described etching process simultaneously, therefore forms depression 1012.
It should be noted that, as shown in Figure 5, owing in Fig. 4, depression 1011 has certain depth, therefore, formed after depression 1011 inwalls at the master walling bed of material 130, during then through etching to form the first master wall 115, the first master wall 115 has partially extended into below the first side wall 114 and the first offset side wall 113, and namely the first master wall 115 is enclosed in bottom the first side wall 114 and the first offset side wall 113.Reason is that the master walling bed of material 130 being originally positioned at depression 1011 is retained when.The degree of depth yet with described indentation structure is less, described indentation struc-ture can not retain the master walling bed of material 130, therefore, second master wall 125 cannot be enclosed in bottom the second side wall 124 and the second offset side wall 123, and described indentation structure also can be exposed again, namely now the second side wall 124 is hollowed out into described indentation structure (not shown) again with the isolation structure 101 bottom the second offset side wall 123.
Refer to Fig. 6, adopt phosphoric acid to clean and remove the first master wall 115 and the second master wall 125, in order to carry out follow-up stress close to (StressProximity) processing step.In the process, depression 1012 shown in Fig. 5 can be corroded the bigger depression of Formation Depth 1013 further by phosphoric acid.
Though not showing in Fig. 6, but before adopting phosphoric acid to clean, the forming method of described semiconductor structure has been also subject to remove the process of kish layer after metal silicide technology.The industrial strong phosphoric acid that this process generally adopts mass fraction to be more than 95% cleans corresponding semiconductor structure in a heated condition.Now, owing to also form described indentation structure at the isolation structure 101 of the second dummy grid 121 down either side in said process, and this indentation structure exposes bottom the second offset side wall 123, and easily exposes the second high-K dielectric layer and the second cap layer further.When removing semiconductor structure when adopting strong phosphoric acid to clean, the second high-K dielectric layer and the second cap layer below the second dummy grid 121 also can touch strong phosphoric acid.And the etch rate of the second high-K dielectric layer and the second cap layer is reached by strong phosphoric acidAbove.Once touch strong phosphoric acid, described second high-K dielectric layer and the second cap layer can be corroded rapidly, in corresponding scavenging period, substantially corroded clean completely, the region that dotted line circle (mark) surrounds in Fig. 6 there is no the second high-K dielectric layer and the second cap layer, thus causing corresponding semiconductor structural failure.
It should be noted that, although in situation shown in Fig. 5, in PMOS transistor region, first master wall 115 is enclosed in bottom the first side wall 114 and the first offset side wall 113, the effect bottom protection the first side wall 114 and the first offset side wall 113 can be played, but this situation is a kind of random situation, owing to there is no special design and control, as a rule, first master wall 115 can not be protected bottom the first side wall 114 and the first offset side wall 113 well, that is, usual first master wall 115 also cannot protect the first high-K dielectric layer and the first cap layer well.In a word, although compared to nmos pass transistor, the yield of PMOS transistor can be higher, but the yield of PMOS transistor also cannot meet requirement.
Refer to Fig. 7, removing the first master wall 115 shown in Fig. 6 and after the second master wall 125, form interlayer dielectric layer 126 and be filled in the Semiconductor substrate between each dummy grid, then remove the first dummy grid 111 and form the first groove (not shown), remove the second dummy grid 121 and form the second groove (not shown), and in described first groove, form the first metal gates 116, in described second groove, form the second metal gates 126.
Process from Fig. 1 to Fig. 7 is it can be seen that consider that the raising of yield, high-K dielectric layer and cap layer increasingly become a success or failure factors in HKMG technique.And its root is as previously described, in the forming process of whole semiconductor structure, there is many cleaning steps and etching process, in these cleaning steps and etching process, isolation structure 101 in all directions (including both horizontally and vertically) all by ceaselessly loss, thus each each described indentation structure less with the degree of depth that cave in that Formation Depth is bigger, cause after metal silicide is formed, when removing kish layer, high-K dielectric layer and cap layer are come out by described each depression and described indentation structure, when removing described kish layer, the method of sulfuric acid cleaned is generally adopted to carry out, and the seriously cleaning by sulphuric acid of high-K dielectric layer and cap layer affects, cause that high-K dielectric layer and cap layer are almost all corroded in cleaning process, thus causing the inefficacy of corresponding semiconductor structure.
When more bad; without the protection of high-K dielectric layer and cap layer, in dummy grid removal process, also can be partially removed bottom each offset side wall; therefore can protrude to both sides bottom the metal gates of follow-up filling, in Fig. 7 shown in second metal gates on the left side；In other cases, owing to not having the stop of cap layer, metal gates can spread to channel region, in Fig. 7 shown in second metal gates on the right.These metal gates protrusion and metal gates diffusion problem can further result in the semiconductor structure of periphery and be also affected by adverse effect, and yield reduces further.
nullSemiconductor structure in order to solve high-K dielectric layer and cap layer loss brings lost efficacy、Metal gates is prominent and the problem such as metal gates diffusion，The present invention proposes the forming method of a kind of new semiconductor structure，Described method is by increasing by one etching processing，Isolation structure defines groove，Therefore，In the process forming master wall，Corresponding master wall can be concurrently formed at the sidewall of described groove，Namely now described master wall is enclosed in the bottom of offset side wall and side wall simultaneously，Prevent offset side wall and side wall by follow-up sulfuric acid cleaned technique erosion damage，More importantly described master wall is formed in described groove，It is prevented from high-K dielectric layer and cap layer is exposed，And then prevent sulphuric acid from corroding high-K dielectric layer and cap layer，Thus preventing semiconductor device failure，The yield of corresponding semiconductor structure is finally greatly improved.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Refer to Fig. 8, it is provided that Semiconductor substrate (does not mark), described Semiconductor substrate has isolation structure 201, and isolation structure 201 is used for isolating active area (mark).Forming the first dummy grid 211 and the second dummy grid 221 on the semiconductor substrate, described first dummy grid 211 and the second dummy grid 221 are at least partially disposed on described isolation structure 201.Also there is between first dummy grid 211 and Semiconductor substrate the first high-K dielectric layer (mark) and the first cap layer (mark), also there is between the second dummy grid 221 and Semiconductor substrate the second high-K dielectric layer (mark) and the second cap layer (mark).In Fig. 8, it is additionally included on the first dummy grid 211 and forms the first hard mask layer 212, the second dummy grid 221 is formed the second hard mask layer 222.
It should be noted that in Fig. 8, it is shown that two the first dummy grids 211, it is limited with centre position, each first dummy grid 211 in the left side and the right；Two the second dummy grids 221, are limited with centre position, each second dummy grid 221 in the left side and the right.Usual each dummy grid is at least across being isolated two active region that structure 201 separates, thus, first dummy grid 211 and the second dummy grid 221 are all at least partially disposed at above isolation structure 201, therefore, in Fig. 8 in the profile position of display, first dummy grid 211 on the left side is positioned at above isolation structure 201, and first dummy grid 211 on the right is positioned at active region；Second dummy grid 221 on the left side is positioned at above isolation structure 201, and second dummy grid 221 on the right is positioned at active region.From another angle, two, left and right the first dummy grid 211 can also regard same first dummy grid 211 cross-section structure at diverse location as；In like manner, two, left and right the second dummy grid 221 can also regard same second dummy grid 221 cross-section structure at diverse location as.
In the present embodiment, Semiconductor substrate is silicon substrate.In other embodiments of the invention, Semiconductor substrate can also be germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or its laminated construction substrate, or silicon-on-insulator substrate, it is also possible to it is well known to a person skilled in the art other suitable semiconductive material substrate.
In the present embodiment, isolation structure 101 is specifically as follows shallow channel isolation area (STI) or field oxide isolation structure.
In the present embodiment, the first dummy grid 211 is the dummy grid for forming PMOS transistor, and the second dummy grid 221 is the dummy grid for forming nmos pass transistor.In other embodiments, the first dummy grid 211 can also be the dummy grid for forming PMOS transistor, and the second dummy grid 221 can also be the dummy grid for forming nmos pass transistor.
In the present embodiment, the first boundary layer (not shown) between the first dummy grid 211 and described first high-K dielectric layer, can also be formed.Second interface layer (not shown) can also be formed between second dummy grid 221 and described second high-K dielectric layer.The material of described each boundary layer can be silicon oxide.Chemical oxidization method or thermal oxidation method can be adopted directly to form boundary layer on substrate.Described each boundary layer can improve raceway groove (trench) carrier mobility, it is possible to the damage that repairing semiconductor substrate surface is subject to.
In the present embodiment, the material of described high-K dielectric layer can be hafnium oxide (HfO2), silicon hafnium oxide (HfSiO), nitrogen hafnium oxide (HfON), nitrogen hafnium silicon oxide (HfSiON), lanthana (La2O3), zirconium oxide (ZrO2), silicon zirconium oxide (ZrSiO), titanium oxide (TiO2) and yittrium oxide (Y2O3) in one or more combination in any.Each high-K dielectric layer can adopt sputtering, pulsed laser deposition (PulsedLaserDeposition, PLD), metallo-organic compound chemical vapor infiltration (Metal-organicChemicalVaporDeposition, MOCVD), atomic layer deposition method (Atomiclayerdeposition, ALD) or other suitable methods are formed.
The material of each cap layer can be one of them of titanium nitride and tantalum nitride, it is also possible to be both combinations.In the present embodiment, concrete employing titanium nitride is as cap layer.Titanium nitride, as a kind of P work function material, also affects the work function of PMOS transistor and nmos pass transistor simultaneously.Described each cap layer can avoid subsequent technique that each high-K dielectric layer is caused damage, and prevent the metal in follow-up each metal structure to be diffused into each high-K dielectric layer, also prevent each high-K dielectric layer to be diffused into other Rotating fields simultaneously, namely prevent each high-K dielectric layer and other Rotating fields generation cross-diffusion.It can be seen that form each cap layer can protect each high-K dielectric layer, so that the performance of the semiconductor structure formed is more stable.
Refer to Fig. 9, form the first offset side wall 213 in the first dummy grid 211 both sides, and the first offset side wall 213 is concurrently formed at the first hard mask layer 212 both sides；Form the second offset side wall 223 in the second dummy grid 221 both sides, and the second offset side wall 223 is concurrently formed at the second hard mask layer 222 both sides.
In the present embodiment, the material of the first offset side wall 213 and the second offset side wall 223 can be silicon nitride.
It should be noted that, though figure does not show, but after forming the first offset side wall 213 and the second offset side wall 223, generally carry out lightly doped drain and inject link, lightly doped drain injects link and generally includes: adopt the first photoresist layer (not shown) to cover described second area, then described first area being carried out the first lightly doped drain injection, thus forming lightly doped drain injection region (not shown), then removing described first photoresist layer；Adopt the second photoresist layer to cover described first area, then described second area being carried out the second lightly doped drain injection, thus forming lightly doped drain injection region (not shown), then removing described second photoresist layer.
Refer to Figure 10, form the first side wall 214 in the first dummy grid 211 both sides, now the first side wall 214 covers the first offset side wall 213 simultaneously；Forming the second side wall 224 in the second dummy grid 221 both sides, now the second side wall 224 covers the second offset side wall 223 simultaneously.
It should be noted that, the process forming the first side wall 214 and the second side wall 224 normally comprises the process forming embedded germanium silicon in PMOS transistor region, namely this processing step can be: forms spacer material layer (not shown), photoresist layer (not shown) is adopted to cover the spacer material layer being positioned at nmos transistor region, again with described photoresist for mask, the described spacer material layer that etching is not covered by described photoresist layer, to form the first side wall 214, and form groove (not shown) in the Semiconductor substrate of the first dummy grid 211 down either side simultaneously, stress germanium silicon is filled afterwards in described groove, to form embedded germanium silicon (mark)；Then, removing described photoresist layer, adopt another photoresist layer to cover PMOS transistor region, etching is positioned on nmos transistor region remaining described spacer material layer, to form the second side wall 224.In the process; the isolation structure 201 (i.e. the isolation structure 201 of the left side the first dummy grid 211 down either side in Figure 10) in PMOS transistor region is owing to experienced by forming process and the cleaning process of described groove; depression 2011 would generally occur, as shown in Figure 10.Due to described groove originally be shaped as bowl-type, final is shaped as Sigma (sigma) shape, therefore the forming process of described groove potentially includes repeatedly secondary cleaning process, such as include adopting diluted hydrofluoric acid that the described groove of bowl-type is carried out, and after the described groove forming Sigma's shape, it is again with the diluted hydrofluoric acid described groove to bowl-type and is carried out.Described cleaning process all can cause the formation of depression 2011.
It should be noted that, though Figure 10 is formed with depression on the isolation structure 201 of not shown second dummy grid 221 down either side, but in fact, on etching nmos transistor region, remaining described spacer material layer is to be formed in the process of the second side wall 224, the isolation structure 201 of the second dummy grid 221 down either side also has part and is depleted, thus forming shallower indentation structure (not shown).
Please continue to refer to Figure 11, isolation structure 201 is performed etching process, to form groove 2012 on isolation structure 101 surface.In fact, when there is the depression 2011 produced in aforementioned process, groove 2012 can be formed through described etching processing by above-mentioned depression 2011, and when there is the described indentation structure produced in aforementioned process, groove 2012 can also be formed through described etching processing by described indentation structure.Even if there be no above-mentioned depression 2011 and described indentation structure, through described etching processing, it is also possible to form groove 2012 on isolation structure 101 surface.
In the present embodiment, the depth bounds of groove 2012 can be.On the one hand, the severity control of described groove 2012 existsAbove, thus ensureing that the master wall being subsequently formed can extend to below offset side wall and side wall at the inwall of described groove 2012 by formation, thus to offset side wall and side wall, and high-K dielectric layer and cap layer are protected.On the other hand, the depth bounds of groove 2012 if greater than, not only need the etching intensity of described etching processing and etch period to increase accordingly, and the follow-up filling to groove 2012 require also to improve accordingly, causes the increase of technology difficulty.
In the present embodiment, described etching processing can be wet etching.The solution that described wet etching adopts can be Fluohydric acid., and the mass concentration of described Fluohydric acid. may range from 0.1%～10%.Fluohydric acid. (electronic-stage hydrofluoric acid) can remove the material such as silicon dioxide and polysilicon.Insulant in isolation structure 201 is generally silicon dioxide.It is therefore possible to use Fluohydric acid. performs etching.
In the present embodiment, the temperature that described wet etching adopts can be 20 DEG C～80 DEG C.The time that described wet etching adopts can be 30s～30min.The temperature that described wet etching adopts selects at room temperature (20 DEG C) more conveniently.Suitably improve temperature and can accelerate etching temperature.Meanwhile, in order to prevent from other structure is caused overetch, it usually needs temperature is controlled in 80 DEG C.Additionally, in described temperature range, control etch period at 30s～30min, ensure that the degree of depth of the groove formed reaches necessary requirement on the one hand, prevent depth of groove too big on the other hand or other structure is impacted, and preventing process cycle oversize.
It should be noted that in other embodiments, described etching processing can also be pattern-free dry etching.The gas that described pattern-free dry etching adopts includes CF4、CHF3、CH2F2And CH3At least one of F, or include CH4Coordinate HCl, HBr and SO2At least one in three, for instance CH4Coordinate HCl, CH4Coordinate HBr, CH4Coordinate SO2Or CH4Coordinate HBr and SO2.Additionally, the gas that described pattern-free dry etching adopts can also include adopting He or H2As assist gas.The temperature range that described pattern-free dry etching adopts can be 20 DEG C～80 DEG C, and the pressure range of employing can be 10mTorr～1000mTorr, and the power bracket of employing can be 10w～3000w.
It should be noted that in other embodiments, described etching processing can also etch for SiConi.SiConi etching can use ammonia (NH3) as the source of hydrogen, and use Nitrogen trifluoride (NF3) as the source of fluorine, both flow through remote plasma system (remoteplasmasystem, RPS) together and enter reaction zone to etch corresponding structure.
It should be noted that in other embodiments, described etching processing can also be the combination of wet etching, pattern-free dry etching and SiConi etching.
It should be noted that in described etch processes, inevitably the first hard mask layer 212 and the second hard mask layer 222 are caused certain corrasion.In order to ensure that the first hard mask layer 212 and the second hard mask layer 222 can protect corresponding dummy grid (prevent dummy grid from exposing and formed and be difficult to the metal silicide removed), the present embodiment control the thickness loss of the first hard mask layer 212 and the second hard mask layer 222 less than or equal to。
It should be noted that in described etch processes, inevitably the first side wall 214 and the second side wall 224 are also resulted in certain corrasion.The material of the first side wall 214 and the second side wall 224 is generally silicon nitride, in order to ensure that the first side wall 214 and the second side wall 224 can protect corresponding dummy grid sidewall, the present embodiment control the thickness loss of the first side wall 214 and the second side wall 224 less than or equal to。
Please continue to refer to Figure 12, above the first hard mask layer 212, above the second hard mask layer 222, the first dummy grid 211 both sides, and the second dummy grid 221 both sides formation master walling bed of material 230.Now the master walling bed of material 230 covers the first side wall 214 and the second side wall 224.Further, now the master walling bed of material 230 can be concurrently formed at groove 2012 inwall.
Refer to Figure 13, etch the master walling bed of material 230 shown in Figure 12, until forming the first master wall 215 being positioned at the first dummy grid 211 both sides and the second master wall 225 being positioned at the second dummy grid 221 both sides.Groove 2012 shown in Figure 12 can be carried out by described etching process simultaneously, therefore forms groove 2013 further.
It should be strongly noted that just as shown in Figure 13, owing to Figure 12 further groove 2012 has enough degree of depthTherefore; formed after groove 2012 inwall at the master walling bed of material 230; during then through etching to form the first master wall 215; first master wall 215 has and partially extends into below the first side wall 214 and the first offset side wall 213; namely the first master wall 215 is enclosed in bottom the first side wall 214 and the first offset side wall 213, thus the first side wall 214 and the first offset side wall 213 are protected, and protects described first high-K dielectric layer and described first cap layer further.Same; formed after groove 2012 inwall at the master walling bed of material 230; during then through etching to form the second master wall 225; second master wall 225 has and partially extends into below the second side wall 224 and the second offset side wall 223; namely the second master wall 225 is enclosed in bottom the second side wall 224 and the second offset side wall 223; thus the second side wall 224 and the second offset side wall 223 are protected, and protect described second high-K dielectric layer and described second cap layer further.
In the present embodiment, first master wall 215 and the second master wall 225 can be formed in groove 2012 inwall, this is because, the master walling bed of material 203 generally adopts chemical vapour deposition technique (CVD) to be formed, and the Technology stronger with the use of various filling capacities carries out, for instance deep vertical wide ratio technology (HARP), or atomic layer deposition method is adopted to carry out, raw material selects with disilicone hexachloride (Hexachlorodisilane, HCD).Therefore, the master walling bed of material 230 can also in the groove 2012 that isolation structure 201 is formed smooth growth, and be retained when in follow-up anisotropic dry etch process.
In the present embodiment, first master wall 215 and the second master wall 225 are formed at groove 2012 inwall, and just as shown in Figure 13, first master wall 215 and the second master wall 225 are formed in groove 2012 inwall, being positioned at each side wall (first side wall 214 and the second side wall 224) and the inwall of each offset side wall (first offset side wall 213 and the second offset side wall 223) lower section, other parts are originally arranged in the master walling bed of material 230 of groove 2012 inwall and are then removed in anisotropic dry etch process.
In the present embodiment, the degree of depth of groove 2012 ownSuitable, and, in master wall forming process, employing is anisotropic dry etch, and therefore, the part master walling bed of material 230 can be retained in groove 2012 inwall.And due in the present embodiment; groove 2012 is formed in the isolation structure 201 below whole each dummy grids; therefore; no matter it is the first dummy grid 211 or the second dummy grid 221; in the isolation structure 201 of they down either side; groove 212 inwall is all covered by described master wall, thus each offset side wall, each side wall, each high-K dielectric layer and each cap layer are played a protective role.
Refer to Figure 14, adopt phosphoric acid to clean and remove the first master wall 215 and the second master wall 225, in order to carry out follow-up stress close to processing step.In the process, groove 2012 shown in Figure 13 can be corroded the bigger groove of Formation Depth 2013 further by phosphoric acid.
In the present embodiment, the mass concentration of described phosphoric acid can be 80%, and can clean each master wall of removal under 100 DEG C～200 DEG C conditions.
Though not showing in Figure 14, but before adopting phosphoric acid to clean, the forming method of described semiconductor structure has been also subject to the formation process of metal silicide, and the formation process of described metal silicide includes the process of follow-up removal kish layer.The formation process of metal silicide generally includes multi-step cleaning process, for instance the wet clean process initially with diluted hydrofluoric acid cleans semiconductor substrate surface, then adopts SiConi cleaning to be carried out further.After forming metal silicide, need to remove the metal level (not shown) of residual, and the industrial strong phosphoric acid that the process removing kish layer generally adopts mass fraction to be more than 95% cleans corresponding semiconductor structure in a heated condition, and the described metal level of residual can be removed under 100 DEG C～200 DEG C conditions.
In summary, before removing the described metal level of residual, have at least two main cleaning steps that isolation structure 201 has comparatively serious loss effect.First cleaning step for taking in embedded germanium silicon forming process: owing to germanium silicon is selective growth, in order to ensure that corresponding described groove inner wall cleans, the cleaning step adopted is strong to the removal effect of silicon oxide, therefore, the isolation structure 201 generally made by silica material can stand more loss.Second cleaning step for taking in metal silicide forming process: when adopting metallic nickel to be used for being formed nisiloy, if semiconductor substrate surface silica, nisiloy cannot be formed, therefore corresponding cleaning step adopts stronger method to be carried out, it is carried out for example with SiConi cleaning, equally isolation structure 201 is had stronger loss effect.In fact, after dummy grid is formed, before metal gates is formed, in isolation structure 201, the loss of 90% occurs in above-mentioned two cleaning process, and the loss of 40%～70% is to occur in the cleaning step that metal silicide forming process is taked.
If groove 2012 inwall is not covered by the first master wall 215 and the second master wall 225 simultaneously, owing to experienced by each cleaning step above-mentioned, corresponding high-K dielectric layer and cap layer are very likely exposed, high-K dielectric layer and cap layer then can quickly be corroded totally (in sulphuric acid and phosphoric acid by the cleaning of this hot concentrated sulfuric acid, the damage of cap layer than high-K dielectric layer fast a lot, so in some cases, high-K dielectric layer damage does not have the cap layer so serious).
But; in the present embodiment; said process defines groove 2012 in the first dummy grid 211 down either side; the bottom of the first side wall 214 and the first offset side wall 213 protected by first master wall 215 of the first dummy grid 211 down either side; and protect described first high-K dielectric layer and described first cap layer further; therefore, described first high-K dielectric layer and described first cap layer will not wreck in this sulfuric acid cleaned step.Same; said process defines groove 2012 in the second dummy grid 221 down either side; the bottom of the second side wall 224 and the second offset side wall 223 protected by second master wall 225 of the second dummy grid 221 down either side; and protect described second high-K dielectric layer and described second cap layer further; therefore, described second high-K dielectric layer and described second cap layer will not wreck in this sulfuric acid cleaned step.As shown in Figure 14, although isolation structure 201 is formed each groove 2013, but each semiconductor structure remains intact.
Refer to Figure 15, removing the first master wall 215 shown in Figure 14 and after the second master wall 225, form interlayer dielectric layer 240 and be filled in the Semiconductor substrate between each dummy grid, then remove the first dummy grid 211 and form the first groove (not shown), remove the second dummy grid 221 and form the second groove (not shown), and in described first groove, form the first metal gates 216, in described second groove, form the second metal gates 226.
It should be noted that, the present embodiment is by increasing the step of described etching processing, not only in PMOS transistor region, add the degree of depth of original depression 2011 and form groove 2012, and in nmos transistor region, described low sunk structure less for the original degree of depth is also etched into groove 2012, therefore, the yield that can not only make PMOS transistor improves, and the yield of nmos pass transistor more can be made to improve simultaneously.
nullIn the forming method of the semiconductor structure that the embodiment of the present invention provides，First Semiconductor substrate is provided，Described Semiconductor substrate has isolation structure 201，Then the first dummy grid 211 and the second dummy grid 221 is formed on a semiconductor substrate，First dummy grid 211 and the second dummy grid 221 are at least partially disposed at above isolation structure 201，The first hard mask layer 212 is formed afterwards on the first dummy grid 211，Second dummy grid 221 is formed the second hard mask layer 222，And form the first offset side wall 213 in the first dummy grid 211 both sides，The second offset side wall 223 is formed in the second dummy grid 221 both sides，Hereafter，Isolation structure 201 is performed etching process，To form groove 2012 on isolation structure 101 surface，When being subsequently formed the first master wall 215 and the second master wall 225，First master wall 215 and the second master wall 225 can be formed in groove 2012 inwall，Thus preventing from removing in the process of kish layer at follow-up employing sulphuric acid，High-K dielectric layer and cap layer are corroded by sulphuric acid，Thus preventing semiconductor structure to lose efficacy，Improve the yield of semiconductor structure.
Owing to high-K dielectric layer and cap layer are not corroded by sulphuric acid, it is thus possible to enough avoid the occurrence of metal gates protrusion to be diffused into the problems such as channel region with metal gates, and then prevent the semiconductor structure of periphery from affecting adversely, improve the yield of semiconductor structure further.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided Semiconductor substrate, described Semiconductor substrate has isolation structure；
Forming the first dummy grid and the second dummy grid on the semiconductor substrate, described first dummy grid and the second dummy grid are at least partially disposed on described isolation structure；
Described isolation structure is performed etching process, to form groove on described isolation structure surface；
In described semiconductor substrate surface, described first dummy grid both sides, forming the master walling bed of material in described second dummy grid both sides and described groove, the described master walling bed of material fills described groove inner wall simultaneously；
Etching the described master walling bed of material, to form the first master wall in the first dummy grid both sides, form the second master wall in described second dummy grid both sides, described first master wall and the second master wall are concurrently formed at described groove inner wall.
2. forming method as claimed in claim 1, it is characterised in that the depth bounds of described groove is
3. forming method as claimed in claim 1, it is characterised in that described etching processing includes at least one of wet etching, pattern-free dry etching and SiConi etching.
4. forming method as claimed in claim 3, it is characterised in that the solution that described wet etching adopts is Fluohydric acid., and the mass concentration of described Fluohydric acid. ranges for 0.1%～10%.
5. forming method as claimed in claim 4, it is characterised in that the temperature that described wet etching adopts is 20 DEG C～80 DEG C, and the time that described wet etching adopts is 30s～30min.
6. forming method as claimed in claim 3, it is characterised in that the gas that described pattern-free dry etching adopts includes CF4、CHF3、CH2F2And CH3At least one of F, or include CH4Coordinate HCl, HBr and SO2At least one in three.
7. forming method as claimed in claim 6, it is characterised in that the temperature range that described pattern-free dry etching adopts is 20 DEG C～80 DEG C, and the pressure range of employing is 10mTorr～1000mTorr, and the power bracket of employing is 10w～3000w.
8. forming method as claimed in claim 3, it is characterised in that before etching the described master walling bed of material, also comprise the steps:
Described first dummy grid forms the first hard mask layer, described second dummy grid forms the second hard mask layer；
In described etch processes, control the thickness loss of described first hard mask layer and the second hard mask layer less than or equal to
9. forming method as claimed in claim 1, it is characterised in that after filling and leading up layer described in being formed in described groove, also comprise the steps:
Metal level is formed at described semiconductor substrate surface；
Being annealed technique makes described metal level and Semiconductor substrate form metal silicide, and adopts sulphuric acid to remove the described metal level of residual.
10. forming method as claimed in claim 9, it is characterised in that after adopting sulphuric acid to remove the described metal level of residual, also includes the step adopting phosphoric acid to etch described first master wall and the second master wall.
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