Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
  • H05K1/0203—Cooling of mounted components
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/4805—Shape
  • H01L2224/4809—Loop shape
  • H01L2224/48091—Arched
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/481—Disposition
  • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/013—Alloys
  • H01L2924/0132—Binary Alloys
  • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12041—LED
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/1515—Shape
  • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/1517—Multilayer substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3025—Electromagnetic shielding
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/06—Thermal details
  • H05K2201/066—Heatsink mounted on the surface of the printed circuit board [PCB]
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10007—Types of components
  • H05K2201/10106—Light emitting diode [LED]
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/85—Packages
  • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S362/00—Illumination
  • Y10S362/80—Light emitting diode

Definitions

• the present invention generally relates to a lighting or illumination assembly. More particularly, the present invention relates to a lighting or illumination assembly that uses an array of light emitting diodes (LEDs).
• LEDs light emitting diodes
• Illumination systems are used in a variety of diverse applications.
• Traditional illumination systems have used lighting sources such as incandescent or fluorescent lights, for example.
• lighting sources such as incandescent or fluorescent lights, for example.
• LEDs light emitting diodes
• LEDs have the advantages of small size, long life and low. power consumption. These advantages of LEDs make them useful in many diverse applications, and LEDs are frequently replacing other lighting sources.
• a plurality of LEDs supply the required light intensity and/or distribution.
• a plurality of LEDs can be assembled in an array having small dimensions to provide a high illuminance in a small area, or a plurality of LEDs can be distributed over a larger area to provide a broader and more uniform illuminance.
• LEDs in an array are commonly connected to each other and to other electrical systems by mounting on a printed circuit board.
• a printed circuit board becomes problematic for several reasons.
• printed circuit boards may be difficult to produce and/or handle in the sizes and shapes required for some display devices (e.g., very long and narrow strips).
• the rigidity of the printed circuit board material may make manufacturing or assembly difficult, especially where the printed circuit board must conform to a non-planar shape.
• the heat dissipation requirements of the LEDs may not be met by conventional printed circuit board constructions. Therefore, an illumination assembly that addresses these problems is needed.
• the assembly comprises a heat dissipating member having a plurality of circuitized strips disposed thereon a spaced relationship.
• Each circuitized strip includes an electrically insulative substrate having at least one circuit trace on a first side of the substrate and an electrically and thermally conductive layer on a second side of the substrate, such that the at least one circuit trace is electrically insulated from the second side of the substrate.
• the circuitized strips also have a plurality of vias extending from the first side to the second side of the substrate.
• a plurality of LEDs are disposed in the plurality of vias. Each of the LEDs is disposed on the electrically and thermally conductive layer on the second side of the substrate and electrically connected to the at least one circuit trace on the first side of the substrate.
• the assembly comprises a flexible circuit having an electrically insulative substrate having at least one circuit trace on a first side thereof, and a plurality of vias extending from the first side to a second side of the substrate.
• An LED is disposed in at least one of the vias, and an electrically conductive heat dissipating member is disposed proximate the second side of the flexible circuit. The LED is electrically connected to both the heat dissipating member and the at least one circuit trace.
• the method comprises providing an insulative substrate, providing a plurality of circuit traces on the insulative substrate, providing a plurality of rows of vias in the insulative substrate, each row of vias having at least one associated circuit trace, separating the substrate into a plurality of strips, each strip including one of the plurality of rows of vias and associated circuit trace, populating at least one via of each strip with an LED, the LED electrically connected to the associated circuit trace, and disposing at least two of the plurality of strips on a heat sink to form an array of LEDs, wherein the LEDs of each strip are electrically connected to the heat sink.
• Figure 1 is a perspective view of an exemplary illumination assembly.
• Figure 2 is schematic sectional view taken along lines 2-2 of FIG. 1.
• Figure 3 is a schematic sectional view of another illumination assembly.
• Figure 4 is a schematic sectional view of the embodiment of FIG. 2, using a different type of LED.
• Figure 5 is a schematic sectional view of the embodiment of FIG. 3, using a different type of LED.
• Figure 6 is a perspective view of another exemplary illumination assembly.
• Figure 7 is schematic sectional view taken along lines 7-7 of FIG. 6.
• Figure 8 is a schematic plan view of a circuitized strip having a complex side edge shape.
• Figure 9 is a schematic plan view of a substrate web before separating individual circuitized strips.
• LED and “light emitting diode” are used to refer generally to light emitting semiconductor elements with contact areas for providing power to the diode.
• inorganic semiconductor light emitting diodes may be formed, for example, from a combination of one or more Group III elements and of one or more Group V elements (HI-V semiconductor).
• III- V semiconductor materials that can be used in an LED include nitrides, such as gallium nitride or indium gallium nitride, and phosphides, such as indium gallium phosphide.
• III- V materials can also be used, as can inorganic materials from other groups of the periodic table.
• the LEDs may be in packaged or non-packaged form, including for example LED dies, surface-mounted LEDs, chip-on-board LEDs and LEDs of other configurations.
• Chip-on-board (COB) refers to a hybrid technology that employs face-up-bonded chip devices interconnected to a substrate conventionally, for example using wire bonding.
• the term LED also includes LEDs packaged or associated with a phosphor where the phosphor converts light emitted from the LED to light at a different wavelength. Electrical connections to the LED can be made by wire bonding, tape automated bonding (TAB), or flip-chip bonding.
• TAB tape automated bonding
• the LEDs are schematically depicted in the illustrations, and can be unpackaged LED dies or packaged LEDs as described herein.
• LEDs can be selected to emit at any desired wavelength, such as in the red, green, blue, ultraviolet, or infrared spectral regions. In an array of LEDs, the LEDs can each emit in the same spectral region, or can emit in different spectral regions. Different LEDs may be used to produce different colors where the color of light emitted from the light emitting element is selectable.
• FIG. 1 shows a perspective view of a portion of an illumination assembly 20.
• the illumination assembly 20 includes one or more longitudinal circuitized strips 22.
• Each circuitized strip 22 carries a plurality of LEDs 24 and is attached to a heat dissipation device 30.
• heat dissipation device is used to refer generally to any device or element that enhances heat transfer away from a hot location, such as the surface of a heat generating LED, to a cooler thermal mass,
• the cooler thermal mass can be a fluid (such as ambient air or a liquid coolant), or a solid (such as a large metal block).
• Heat dissipation devices can be passive or active, and utilize solid or fluid thermal masses alone or in combination with each other.
• Heat dissipation devices include, for example, heat sinks, heat spreaders, heat pipes, and heat exchangers. Heat dissipation devices can include radiating fins or other surfaces for enhancing heat transfer.
• the heat dissipation device 30 is made of a thermally and electrically conductive material. Suitable materials for the heat dissipation device 30 include metals such as aluminum or copper, or metal alloys including, for example, copper molybdenm. In alternate embodiments, non-metallic thermally conductive materials can be used. An exemplary non-metallic material is a graphite and silicone composite material available as 3M Flexible Heat Sink, from 3M Company of Saint Paul, Minnesota. Preferably, heat dissipation device 30 has a low thermal resistance and a low electrical resistivity. In some embodiments, heat dissipation device 30 has a thermal resistance from about 15 to 20 °C/W, and an electrical resistivity in the range of about 1.7 X 10 "8 ohm-meter or less.
• each circuitized strip 22 includes an electrically insulative dielectric substrate 32 having an electrically conductive layer 34 on at least a first side 36 thereof, and an electrically and thermally conductive layer 38 on a second side 40 thereof.
• the electrically conductive layer 34 on the first side 36 of the substrate 32 is patterned to form at least one circuit trace 42, while the layer 38 on the second side 40 of the substrate 32 can remain unpatterned.
• the layer 34 can alternatively be patterned to form a plurality of circuit traces on the first side 36 of the substrate 32, including power and signal traces for operative electrical connection to the LEDs 24.
• the electrically insulative dielectric substrate 32 may be comprised of a variety of suitable materials, including polyimide, such as Kapton-brand polyimide manufactured by Du Pont, Wilmington, Delaware, polyester, polyethyleneterephthalate (PET), multilayer optical film (as disclosed in United States Patent Nos. 5,882,774 (Jonza et al), and 5,808,794 (Weber et al)), polycarbonate, polysulfone, or FR4 epoxy composite, for example.
• substrate 32 can be flexible.
• the electrically and thermally conductive layers 34, 38 on the first and second sides 36, 40 of the substrate 32 may be comprised of a variety of suitable materials, preferably metals including but not limited to copper, nickel, gold, aluminum, tin, lead, chrome, and combinations thereof, for example. In embodiments where substrate 32 is flexible, it is preferred that the layers 34, 38 are also flexible.
• a suitable flexible material having a polyimide insulative substrate with copper conductive layers thereon is 3MTM Flexible Circuitry, available from 3M Company of Saint Paul, Minnesota.
• the multilayer optical films referred to above can be made by coextrusion of alternating polymer layers.
• polymer materials are used predominantly or exclusively in the makeup of the individual layers.
• Such films are compatible with high volume manufacturing processes, and can be made in large sheets and roll goods.
• the films comprise individual microlayers having different refractive index characteristics so that some light is reflected at interfaces between adjacent microlayers.
• the microlayers are sufficiently thin so that light reflected at a plurality of the interfaces undergoes constructive or destructive interference in order to give the film the desired reflective or transmissive properties.
• each microlayer For optical films designed to reflect light at ultraviolet, visible, or near-infrared wavelengths, each microlayer generally has an optical thickness (i.e., a physical thickness multiplied by refractive index) of less than about 1 ⁇ m. Thicker layers can, however, also be included, such as skin layers at the outer surfaces of the film, or protective boundary layers disposed within the film that separate packets of microlayers.
• the reflective and transmissive properties of multilayer optical films are a function of the refractive indices of the respective microlayers.
• Each microlayer can be characterized at least in localized positions in the film by in-plane refractive indices n x , n y , and a refractive index n z associated with a thickness axis of the film.
• the multilayer optical film can be made by co-extrusion of typically tens or hundreds of layers of two alternating polymers A, B, followed by optionally passing the multilayer extrudate through one or more multiplication die, and then stretching or otherwise orienting the extrudate to form a final film.
• the resulting film is composed of typically tens or hundreds of individual microlayers whose thicknesses and refractive indices are tailored to provide one or more reflection bands in desired region(s) of the spectrum, such as in the visible or near infrared.
• adjacent microlayers preferably exhibit a difference in refractive index ( ⁇ n x ) for light polarized along the x-axis of at least 0.05. If the high reflectivity is desired for two orthogonal polarizations, then the adjacent microlayers also preferably exhibit a difference in refractive index ( ⁇ n y ) for light polarized along the y-axis of at least 0.05.
• the refractive index difference ( ⁇ n z ) between adjacent microlayers for light polarized along the z-axis can also be tailored to achieve desirable reflectivity properties for the p-polarization component of obliquely incident light.
• the x-axis will be considered to be oriented within the plane of the film such that the magnitude of ⁇ n x is a maximum.
• the magnitude of ⁇ n y can be equal to or less than (but not greater than) the magnitude of ⁇ n x .
• the selection of which material layer to begin with in calculating the differences ⁇ n x , ⁇ n y , ⁇ n z is dictated by requiring that ⁇ n x be non-negative.
• the z-index mismatch ⁇ n z between microlayers can be controlled to be substantially less than the maximum in-plane refractive index difference ⁇ n x , such that ⁇ n z ⁇ 0.5* ⁇ n x . More preferably, ⁇ n z ⁇ 0.25 * ⁇ n x .
• a zero or near zero magnitude z-index mismatch yields interfaces between microlayers whose reflectivity for p-polarized light is constant or near constant as a function of incidence angle.
• the z- index mismatch ⁇ n z can be controlled to have the opposite polarity compared to the in-plane index difference ⁇ n x , i.e. ⁇ n z ⁇ 0. This condition yields interfaces whose reflectivity for p-polarized light increases with increasing angles of incidence, as is the case for s-polarized light.
• known self-assembled periodic structures such as cholesteric reflecting polarizers and certain block copolymers, can be considered multilayer optical films for purposes of this application.
• Cholesteric mirrors can be made using a combination of left and right handed chiral pitch elements.
• the substrate 32 further has a plurality of through-holes or vias 50 extending through the substrate 32 from the first side 36 to the second side 40 of the substrate 32.
• Each via 50 is configured to receive an LED 24 therein.
• the vias 50 can be chemically etched, plasma etched, laser milled, or punched through the insulative substrate 32, as is known in the art.
• the circuitized strips 22 have a width W sufficient to accommodate a single row of vias. In other embodiments, the width W of the circuitized strips 22 may accommodate two or more rows of vias.
• the LEDs 24 may be arranged along a given circuitized strip 22 with an LED-to-LED spacing (pitch) in the range of 3mm to 15 mm.
• the desired pitch may be less than 3 mm. In other applications, where the resolution and/or brightness requirements are low, the desired pitch may be more than 15 mm.
• the vias 50 provide the advantage of a convenient alignment point for placing the LEDs 24.
• the vias 50 do not extend through the electrically and thermally conductive layer 38 provided on the second side 40 of the substrate 32, such that LEDs 24 placed in the vias 50 may be attached to the layer 38 during the manufacturing process.
• the electrically and thermally conductive layer 38 may serve a combination of purposes, including making an electrical connection to the LEDs 24, providing a direct thermal pathway from the LEDs 24 to the underlying heat dissipation device 30, providing heat spreading laterally away from the LEDs 24, and providing electrical connections to other systems, for example.
• the LEDs 24 illustrated are of the type having one electrical contact on the base 52 of the LED 24 and another electrical contact on the opposite (top) surface of the LED 24.
• the contact on the base 52 of each LED 24 is electrically and thermally connected to the layer 38 on the second side 40 of the substrate 32, while the contact on the top of each LED 24 is electrically connected to the circuit trace 42 on the first side 36 of the substrate 32 by a wirebond 54 extending from LED 24 to a bond pad 56 on the circuit trace 42.
• Thermally and electrically conductive adhesives solder re-flow, thermosonic bonding (if the LED die has an appropriate backside metallization), and Au/Sn eutectic bonding are among the attachment methods that can be used to attach the LEDs 24 to the thermally and electrically conductive layer 38 on the second side 40 of the substrate 32.
• Solder typically has a lower thermal resistance than an adhesive, but not all LEDs 24 have solderable base metallization.
• Solder attachment also has the advantage of LED 24 self- alignment, due to the surface tension of the molten solder aligning the LED 24 during processing. However, some LEDs may be sensitive to solder reflow temperatures, making an adhesive more appropriate.
• the LEDs 24 are disposed in at least some of the vias 50. Some of the vias 50 may optionally be left unpopulated with LEDs 24. For example, in some embodiments, every other via can be left unpopulated.
• the unpopulated vias 50 are useful for several purposes. If, after populating some of the vias in the circuitized strips with LEDs, an LED is found to be defective during testing, a replacement LED may be attached in an unpopulated via next to the defective LED.
• the unpopulated vias also can be used to make appropriate power and signal connections to the circuitized strip 22, or as alignment points for registration with other elements of the assembly.
• the circuitized strips 22 with attached LEDs 24 are disposed on the heat dissipation device 30 such that the first side 36 is facing away from the heat dissipation device 30, and the electrically and thermally conductive layer 38 is adjacent the heat dissipation device 30.
• the circuit traces 42 on the first side 36 of the substrate 32 are thus electrically insulated from the electrically conductive layer 38 and the heat dissipation device 30 by the substrate 32.
• the electrically and thermally conductive layer 38 on the second side 40 of the substrate 32 is preferably mounted on the heat dissipation device 30 using an electrically and thermally conductive bond, illustrated in FIGS. 1 and 2 as bonding layer 60.
• Thermally and electrically conductive adhesives or solder are among the attachment methods that can be used to attach the layer 38 to the heat dissipation device 30.
• the heat dissipation device 30 is also an active element of the electrical circuits of the illumination assembly 20.
• the heat dissipation device 30 may provide a common electrical ground to each of the LEDs 24 in the circuitized strips 22.
• additional benefits including an even current distribution with low voltage drop, and EMI shielding are beneficially provided.
• the layer 38 on the second side 40 of the substrate 32 and the heat dissipation device 30 can both be metals, and the circuitized strips 22 can be mounted onto the heat dissipation device 30 by applying solder to at least one of the metal surfaces to be bonded, then causing the metal surfaces of layer 38 and heat dissipation device 30 to be soldered to each other.
• Suitable soldering methods include reflow soldering and wave soldering. Soldering may also be performed using solder paste and laminating the circuitized strips 22 to the metal heat dissipation device 30 with a heated nip or stamp.
• the bond between the circuitized strip 22 and the heat dissipation device 30 may extend over the entire area of the circuitized strip 22, or may cover only a portion of the circuitized strip. In some cases is it desirable for the layers or components of the illumination assembly between the LED and the heat dissipation device to provide a direct thermal pathway between the LED
• circuitized strips 22 can be mounted on the heat dissipation device 30 before populating the circuitized strips 22 with LEDs 24.
• the LEDs 24 typically are nominally 250 micrometers tall, the insulative substrate 32 is in the range of
• the thickness of conductive layers 34, 36 is in the range of 17 to 34 micrometers, but can be varied to more or less than that range based on the power requirements of the LEDs 24.
• the bond pads 56 can include a surface metallization of nickel and gold.
• the vias 50 are illustrated as having sloped side walls 62, as is typical of chemically etched vias. However, vias that are plasma etched or laser milled may have substantially vertical side walls.
• FIG. 3 is a schematic sectional view of an illumination assembly 20a similar to illumination assembly 20, but where circuitized strip 22a has been substituted for strip 22.
• the circuitized strip 22a of FIG. 3 differs from strip 22 of FIG. 2 in that the electrically and thermally conductive layer 38 on the second side 40 of the substrate 32 has been omitted.
• the circuitized strips 22a are mounted on the heat dissipation device 30 prior to populating all or a portion of the vias 50 with LEDs 24.
• the base 52 of each LED 24 is electrically and thermally connected directly to the heat dissipation device 30, while the contact on the top of each LED 24 is electrically connected to the circuit trace 42 by a wirebond 54 extending from LED 24 to a bond pad 56 on the circuit trace 42.
• the circuitized strip 22a may be attached by any suitable method, including thermally and electrically conductive adhesives, or solder. Even in cases where an adhesive is used to attach the substrate 32 to the heat dissipation device 30, a solder bond can also be formed between the LED 24 and the heat dissipation device 30 for improved thermal conductivity between the LED 24 and the heat dissipation device 30.
• the heat dissipation device 30 is thus an active thermal and electrical element of the illumination assembly 20.
• FIGS. 4 and 5 are schematic sectional views of additional illumination assemblies 20b, 20c, respectively, that utilize alternative circuitized strips 22b, 22c.
• the illustrated wirebonded LED 24a has both electrical contact pads on the same side of the LED, rather than on opposite sides of the diode as in the wirebonded LED 24 of FIGS. 1-3.
• the construction of the circuitized strip 22b of FIG. 4 is like strip 22 of FIG. 2, with the LED 24a positioned within the via 50 and thermally connected to layer 38 by the thermally conductive layer 60.
• the layer 60 may comprise adhesive, solder, a thermosonic bond, or an Au/Sn eutectic bond, for example.
• the construction of the circuitized strip 22c of FIG. 5 is like strip 22a of FIG.
• FIGS. 6 and 7 illustrate an additional illumination assembly 2Od that utilizes alternative circuitized strips 22d disposed on a combination of heat dissipation devices 30a, 30b.
• Each circuitized strip 22d includes an electrically insulative dielectric substrate 32 having a plurality of through-holes or vias 50 extending through the substrate 32 from the first side 36 to the second side 40 of the substrate 32.
• Each via 50 is configured to receive an LED 24b therein.
• An electrically and thermally conductive layer 38d is disposed on the second side 40 and extends across vias 50.
• the electrically and thermally conductive layer 38d is patterned to form a plurality of discrete sections 64, with each via 50 being associated with one of the sections 64.
• the sections 64 of layer 38d may serve a combination of purposes, including making an electrical connection to the LEDs, providing a thermal pathway from the LEDs to the underlying heat dissipation devices 30a, 30b, providing heat spreading laterally away from the LEDs, and providing electrical connections to other systems, for example.
• the LEDs 24b illustrated are of the type having one electrical contact on the base 52 of the LED and another electrical contact on the opposite (top) surface of the LED. The contact on the base 52 of each LED is electrically and thermally connected to the associated section 64 of layer 38d, while the contact on the top of each LED is electrically connected to an adjacent section 64 by a wirebond 54 extending from LED 24b to filled via 66 extending through substrate 32.
• via 66 may not be filled, and wirebond 54 can connect directly to the adjacent section 64.
• the discrete sections 64 of layer 38d allow the LEDs to be connected in series, which may be desirable in certain applications.
• layer 38d can be a metal and can be attached to the LEDs 24b by attachment methods including thermally and electrically conductive adhesives, solder re- flow, thermosonic bonding (if the LED die has an appropriate backside metallization), and Au/Sn eutectic bonding.
• each first heat dissipation device 30a is electrically and thermally connected to an associated section 64 of layer 38d, but electrically isolated from the second heat dissipation device 30b.
• each section 64 and the associated first heat dissipation device 30a can be thermally and electrically bonded by applying solder to at least one of the metal surfaces to be bonded, then causing the metal surfaces of layer 38d and first heat dissipation device 30a to be soldered to each other. Soldering may also be performed using solder paste and laminating the sections 64 of the circuitized strips 22d to the metal first heat dissipation devices 30a with a heated nip or stamp.
• First heat dissipation devices 30a are electrically separated from second heat dissipation device 30b by thermally conductive, electrically insulative layer 69.
• the material of layer 69 can be, for example, a thermally conductive adhesive such as a boron nitride loaded polymer, like that available as 3M 2810 from 3M Company, of Saint Paul, Minnesota.
• the circuitized strips of FIG. 1 and 6 are illustrated as having straight side edges 70 as formed, for example, by slitting the substrate. In other embodiments, the circuitized strips may have a complex side edge formed, for example, by die cutting or etching processes.
• FIG. 8 an exemplary circuitized strip 22e having a complex side edge 70a is illustrated in top or plan view.
• Strip 22e includes a plurality of relatively wide enlarged regions 72 separated by a plurality of relatively narrow necked regions 74.
• a plurality of power and signal conductive traces 42a are provided on the first surface of the substrate 32.
• the enlarged regions 72 each include a via 50 for receiving an LED (not shown), and bonding pads 56 for making electrical connections to the LEDs and other electrical systems.
• FIGS. 1-8 can be manufactured from a sheet or web of the insulative dielectric substrate.
• FIG. 9 illustrates one method for manufacturing the circuitized strips 22e of FIG. 8.
• a web or sheet 80 of the insulative dielectric substrate 32 is metallized and patterned to have a plurality of conductive traces 42a thereon.
• the web or sheet 80 is then slit, die cut, provided with zipped perforations and torn, or etched to separate the individual circuitized strips 22e.
• FIG. 9 it can be seen how the complex side edge 70a shape beneficially minimizes unused areas of the substrate 32.
• LEDs can be attached to the circuitized strips 22e by mounting in some or all of the vias as described above, and the strips 22e are mounted on the heat dissipation device in a desired arrangement and spacing.
• the disclosed circuitized strips, or LEDs, or both can be combined with other optical devices, films, or other elements on the illumination assembly.
• Such devices, films, or other elements may include, for example, light absorbing masking components, highly reflective materials, and encapsulants, and phosphors.
• Encapsulants can be directly applied to all or some of the LEDs, prior to or after separating the circuitized strips from the web 80. Encapsulants can cover the LEDs individually, or as groups of two or more LEDs. The shape and position of the encapsulants can provide desired light guiding or light extraction effects. The encapsulant can form the final desired shape of the LED, or may be later covered with another encapsulant layer. Covering the initial encapsulant layer with another encapsulant layer allows more expensive, high refractive index, slow curing encapsulants, and generic encapsulant shapes to be generated while the LED populated circuitized strips are easily handled, and allows more complex encapsulant shapes to be applied at a later time.
• the shape of the encapsulant may distribute light through a combination of refraction and reflection.
• the encapsulant may also produce the desired light output profile in combination with other optical components.
• Other optical elements can be applied between the circuitized strips, over the LEDs or between the LEDs, depending upon the desired optical properties of the illumination assembly.
• the assembly 2Od of FIG. 6 illustrates an optical film layer 82 disposed between first heat dissipation devices 30a of adjacent circuitized strips 22d.
• layer 82 can extend over first heat dissipation devices 30a, or entirely over the circuitized strips if layer 80 is provided with apertures at the positions of the LEDs.
• an optional encapsulant 84 is illustrated extending over the first side 36 of the substrate 32.
• optical film layer 82 and encapsulant 84 can be used in conjunction with any of the illumination assemblies described herein.
• specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present invention.
• Those with skill in the chemical, mechanical, electro-mechanical, and electrical arts will readily appreciate that the present invention may be implemented in a very wide variety of embodiments. This application is intended to cover any adaptations or variations of the preferred embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Non-Portable Lighting Devices Or Systems Thereof (AREA)
• Fastening Of Light Sources Or Lamp Holders (AREA)
• Arrangement Of Elements, Cooling, Sealing, Or The Like Of Lighting Devices (AREA)
• Led Device Packages (AREA)

Priority Applications (2)

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Publications (2)

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• 2004
  • 2004-11-05 US US10/982,651 patent/US7303315B2/en not_active Expired - Lifetime
• 2005
  • 2005-09-27 WO PCT/US2005/034501 patent/WO2006052330A2/en not_active Ceased
  • 2005-09-27 KR KR1020077012559A patent/KR101206209B1/ko not_active Expired - Fee Related
  • 2005-09-27 CN CNB2005800416800A patent/CN100517779C/zh not_active Expired - Fee Related
  • 2005-09-27 JP JP2007540306A patent/JP4763709B2/ja not_active Expired - Fee Related
  • 2005-10-14 TW TW094135798A patent/TW200628725A/zh unknown

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