WO2006050690A2 - Elektronisches bauteil und verfahren zur herstellung des elektronischen bauteils - Google Patents
Elektronisches bauteil und verfahren zur herstellung des elektronischen bauteils Download PDFInfo
- Publication number
- WO2006050690A2 WO2006050690A2 PCT/DE2005/001921 DE2005001921W WO2006050690A2 WO 2006050690 A2 WO2006050690 A2 WO 2006050690A2 DE 2005001921 W DE2005001921 W DE 2005001921W WO 2006050690 A2 WO2006050690 A2 WO 2006050690A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- electronic component
- adhesion promoter
- solder
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/12—Containers or parts thereof characterised by their shape
- H10W76/13—Containers comprising a conductive base serving as an interconnection
- H10W76/134—Containers comprising a conductive base serving as an interconnection having other interconnections parallel to the conductive base
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/479—Leadframes on or in insulating or insulated package substrates, interposers, or redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/60—Seals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
- H10W72/07532—Compression bonding, e.g. thermocompression bonding
- H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/17—Containers or parts thereof characterised by their materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/60—Seals
- H10W76/63—Seals characterised by their shape or disposition, e.g. between cap and walls of a container
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Definitions
- the present invention relates to an electronic component, in particular a high-frequency power module, having a plastic walls and a metal frame having housing frame, wherein the plastic walls and the metal frame are connected via a solder joint.
- the invention further relates to a method for producing a solder connection between a thermoset component and a metal part.
- High-frequency power modules are often housed in cavity housings made of ceramic due to the high heat development and high-frequency properties.
- ceramic cavity housings are expensive and expensive to manufacture.
- Other materials which can also be used in conjunction with the high-frequency properties of the module to be accommodated in the housing would, as already mentioned, be plastic materials such as thermoplastics or thermosetting plastics. Duroplastics would be particularly suitable because they do not soften due to their stable after the curing process structure when heated in contrast to thermoplastics.
- the cavity housing also metallic components, for. As metal frame in the foot area, which must be adherent and tightly connected to the plastic walls, and this connection must also withstand the loads that act on wire bonding with ultrasound on the component and thus also on the connection point.
- an electronic component in particular a high-frequency power module, has the following features: a cavity housing with a housing frame with plastic walls, a metal housing bottom with at least one chip island, at least one semiconductor chip arranged on the chip island, wherein the
- Plastic walls are made of a thermosetting plastic and have surfaces that are connected to surfaces of the metal housing bottom via a solder joint.
- thermosets have, on account of their stable structure after curing, the properties desired for the high-frequency application and temperature ranges of the application.
- thermoplastic In contrast to the thermoplastic They are temperature and dimensionally stable and generally withstand higher loads.
- thermoplastic resins are inexpensive and easy to process or process.
- the Duroplastwandept of the housing could be easily produced either as a molding compound or by injection molding.
- solder joint according to the invention between the Duroplastwan ⁇ and the housing bottom of the electronic component generates a strong bond, which is more reliable than a conventional adhesive bond. Also, the solder joint, which is produced in particular by means of soft soldering, is stable over a relatively high temperature range and long-term reliable than the hinge connection known from the prior art between plastic part and metal part.
- the surfaces of the plastic walls connected to the surfaces of the metal frame have a solderable layer structure with a first adhesion promoter layer, which comprises Cr.
- the layer structure further comprises a second adhesion promoter layer which comprises Cu. It is particularly preferred if the soldered connection is produced by soft soldering.
- the layer structure further comprises a diffusion barrier layer which comprises Ni or a Ni alloy.
- the layer structure preferably has a solder layer comprising Sn.
- solder layer can also have other materials; For example, it is also possible to use gold-tin solder.
- the first adhesion promoter layer preferably has a thickness of 0.05 ⁇ m, and the second adhesion promoter layer has a thickness of 0.5-1 ⁇ m.
- the diffusion barrier has a thickness of 1.0 ⁇ m and the solder layer has a thickness of 1.0 ⁇ m.
- thermoset or the KunststoffStoffWandungen the Ge housing frame of the electronic component are made of at least one of these materials. But it can also be any Liehe other thermosets such.
- KMC 180-7 molding compound from Shin-Etsu
- the method according to the invention for producing a solder joint between a thermoset component and a metal part comprises the following steps: cleaning a surface of the thermoset component provided for the solder connection; Preparing the surface of the thermoset component for metallization by means of a plasma pretreatment; Metallizing the surface of the thermoset component, wherein a layer structure with at least one first adhesion promoter layer and at least one solder layer is produced.
- the solderable layer structure on the thermoset component creates a tight and tight connection.
- the solder joint is more reliable than an adhesive bond. It is also, as already mentioned, stable over a larger temperature range. Furthermore, so provided solder joint provides a stiff
- the process time for producing the compound is in the range of seconds compared with up to 1.5 hours curing temperature of an adhesive.
- the soldering process is identical to a chip mounting process, so that both assembly processes can be carried out in parallel and thus the assembly time and thus the costs can be reduced.
- the surface of the thermoset component is cleaned in the cleaning step with alcohol.
- thermosetting component is carried out by means of glow discharge.
- the plasma pre-treatment of the surface of the thermoset component is carried out by means of metal ion treatment.
- the metallization step is carried out by means of a highly active PVD process.
- the solder layer is applied galvanically. This is off Cost reasons advantageous, especially when layer thicknesses of tens of microns are required.
- Particularly preferred here is a vacuum arc process.
- the first primer layer comprises Cr, and the first primer layer is applied in a thickness of 0.05 ⁇ m.
- the solder layer comprises Sn and is applied in a thickness of 0.5-1 ⁇ m.
- At least one diffusion barrier layer is applied over the first adhesion promoter layer and / or second adhesion promoter layer.
- the second adhesion promoter layer preferably comprises Cu and is applied in a thickness of 0.5 to 1.0 ⁇ m.
- FIG. 1 shows a schematic cross section through an electronic component with a cavity housing according to FIG.
- FIG. 2 shows a schematic cross section through an electronic component with a cavity housing according to the invention
- FIGS. 3 a, b, c show a schematic cross section through layer structures according to the invention.
- Figure 4 shows a schematic cross section through the device construction, which is used for a vacuum arc process.
- FIG. 1 shows a schematic cross section through an electronic component 1 with a cavity housing 3.
- the cavity housing 3 has a housing frame 4 which is open at the top and at the bottom.
- a cavity enclosed by the housing frame 4 is surrounded by plastic walls 5, wherein in the foot region of the plastic walls 5 a metal frame 6 is arranged, which adjoins the foot frame 22 of the housing frame 4 with its upper side 7.
- the cavity housing 3 is closed at the bottom by a metallic housing bottom 9 which is formed here as a heat sink 16 Aus ⁇ .
- the housing bottom 9 is connected via a Lötfuge 15 with the back 38 of the metal frame 6.
- the metal frame 6 has anchoring elements 14, which are designed as a dovetail, so that a positive anchoring of the metal frame 6 in the foot region 22 of the plastic walls 5 is present.
- the housing bottom 9 three chip islands 10 are arranged, which consist of a gold coating, while the Gerissause ⁇ bottom 9 is made of a copper alloy.
- the silicon of the semiconductor chips 11 forms a eutectic alloy during application under correspondingly high temperatures, so that the semiconductor chips 11 are securely connected to the housing bottom 9 and when soldering the housing base 9 to the metal frame 6 on the chip islands 10 remain fixed.
- the anchor elements 14 ensure that when soldering the housing bottom 9 to the metal frame 6, the metal frame 6 does not come off the plastic walls 5.
- the housing bottom 9 has a metal base 17, which together with the thickness of the chip island 10 has a height h which is dimensioned such that the thickness d of the semiconductor chips 11 plus the height H of the metal base 17 reaches the level n of the flat conductor 18.
- the electronic component 1 with the high-frequency power module 2 in the cavity 25 is closed off at the top by a housing cover 26 which is formed from a copper or nickel alloy or thermoplastic / or duroplastic / or ceramic and with a step-shaped projection 20 of the housing frame 4 is in intervention. Due to the metallic design of the housing cover 26 as well as of the housing bottom 9, the high-frequency power module 2 is shielded against electrical outer stray fields.
- FIG. 2 shows a schematic cross section through an electronic component 1 with a cavity housing 3 according to the invention.
- the housing frame 4 plastic walls 5, which are made of a thermosetting plastic.
- the foot region 22 of the housing frame 4 is coated with a solderable layer structure 8, by way of which the metallic housing bottom 9 can be soldered to the foot region 22 in an adhesive and temperature-stable manner.
- FIGS. 3 a to c show a schematic cross section through various layer structures according to the invention.
- the first layer which is applied directly to the thermoset of the plastic wall 5 in the foot region 22 of the housing frame 4 (see FIG. 2), is a first adhesion promoter layer 13 of Cr.
- the solder layer 30, which in this case consists of Sn, applied.
- the thickness of the first adhesion promoter layer 13 is 0.05 ⁇ m and the thickness of the solder layer 30 is 1.0 ⁇ m.
- the second example of a layer structure according to the invention as shown in FIG. 3 b, three layers 13, 28 and 30 are applied to the surface 36 of the foot region 22 of the housing frame 4 (see FIG. 2).
- the first layer which in turn is in direct contact with the thermosetting plastic, is the first adhesion promoter layer 13.
- Affixed thereto is a second adhesion promoter layer 28 made of Cu.
- a solder layer 30 made of Sn is applied to this second adhesion promoter layer 28.
- first adhesion promoter layer 13 which is in direct contact with the thermoplastic
- second adhesion promoter layer 28 which is overlaid by a diffusion barrier layer 29.
- solder layer 30 is then applied.
- the first adhesion promoter layer 13 consists of Cr
- the second adhesion promoter layer 28 consists
- the Ni diffusion barrier layer 29 serves as a barrier for the Cu of the second adhesion promoter layer 28.
- the solder layer 30 is again made of Sn.
- the plastic so the thermoset, see ver ⁇ with a solderable layer structure.
- the thermoset components 31 are subjected to a preprocessing, which is carried out as follows: First, the thermoset component surface is chemically cleaned. In particular, cleaning with alcohol is suitable. Then, the thermoset members 31 are installed in a vacuum chamber. When the working pressure is reached, a plasma pretreatment occurs. This takes place immediately before the start of the coating. For this purpose, primarily glow discharges (normal glow discharge or arc enhanced glow discharge (AEGD) with different plasma gases are used.) Another possibility is the metal ion treatment of the thermoset components 31. High-energy metal ions are used for cleaning and activating the substrate surface.
- AEGD arc enhanced glow discharge
- thermoset component surfaces are formed, which is carried out with metals according to the desired solderable layer structure 8.
- the vacuum arc process verwen ⁇ be used.
- FIG. 4 shows a schematic cross section through the device structure used for the vacuum arc process.
- the device construction comprises: a gas inlet 32, an evaporator 33, a bias source 35 and a vacuum system 34.
- the thermoplastic components 31 are inserted into a vapor deposition chamber in the sample chamber and vapor-deposited there.
- the evaporator 33 cathode of the arc discharge
- the cathode material is vaporized by an arc discharge and ionized.
- the metal plasma produced in this way is used to coat the samples. Possible coating materials are: Cr, Cu, Ni, Sn, NiV7.
- the advantage of this method is that the coating material is completely ionized. This can u. a. very dense layers with very good adhesion to the substrate, in this case on the Duroplastteil 31, are generated.
- solder layer 30 which consists for example of tin, can then be enhanced by a galvanic Ver ⁇ drive.
- thermoset components 31 provided with a layer structure produced according to the method described above are therefore readily solderable to metal parts, so that a permanently adherent bond is provided.
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Casings For Electric Apparatus (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102004054597.9A DE102004054597B4 (de) | 2004-11-11 | 2004-11-11 | Elektronisches Bauteil und Verfahren zum Herstellen eines elektronischen Bauteils |
| DE102004054597.9 | 2004-11-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2006050690A2 true WO2006050690A2 (de) | 2006-05-18 |
| WO2006050690A3 WO2006050690A3 (de) | 2006-08-31 |
Family
ID=35559329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE2005/001921 Ceased WO2006050690A2 (de) | 2004-11-11 | 2005-10-26 | Elektronisches bauteil und verfahren zur herstellung des elektronischen bauteils |
Country Status (2)
| Country | Link |
|---|---|
| DE (1) | DE102004054597B4 (de) |
| WO (1) | WO2006050690A2 (de) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6107362B2 (ja) * | 2013-04-18 | 2017-04-05 | 富士電機株式会社 | 半導体装置の製造方法及び半導体装置 |
| US9768077B1 (en) | 2016-06-02 | 2017-09-19 | International Business Machines Corporation | Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3407480A1 (de) * | 1984-02-29 | 1985-09-05 | Siemens AG, 1000 Berlin und 8000 München | Elektrisches oberflaechenwellenfilter |
| CA1302947C (en) * | 1985-09-13 | 1992-06-09 | Jerome S. Sallo | Copper-chromium-polyimide composite |
| EP0386458A1 (de) * | 1989-03-04 | 1990-09-12 | Oerlikon-Contraves AG | Verfahren zum Herstellen von Dünnschichtschaltungen mit Zinnstrukturen |
| CN1166912A (zh) * | 1995-03-02 | 1997-12-03 | 电路元件股份有限公司 | 供频率范围高达90GHz的微波电路用低成本、高性能封装 |
| DE19718177A1 (de) * | 1997-04-29 | 1998-11-05 | Fraunhofer Ges Forschung | Verfahren zur Aufrauhung von Kunststoffen |
| DE10060571A1 (de) * | 2000-12-06 | 2002-06-20 | Bosch Gmbh Robert | Präpolymer und daraus hergestelltes dielektrisches Material |
| US20030178718A1 (en) * | 2001-11-05 | 2003-09-25 | Ehly Jonathan P. | Hermetically enhanced plastic package for microelectronics and manufacturing process |
| DE502004000545D1 (de) | 2003-02-13 | 2006-06-14 | Infineon Technologies Ag | Elektronisches bauteil mit halbleiterchip und verfahren zur herstellung desselben |
-
2004
- 2004-11-11 DE DE102004054597.9A patent/DE102004054597B4/de not_active Expired - Fee Related
-
2005
- 2005-10-26 WO PCT/DE2005/001921 patent/WO2006050690A2/de not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| DE102004054597A1 (de) | 2006-05-24 |
| DE102004054597B4 (de) | 2019-07-25 |
| WO2006050690A3 (de) | 2006-08-31 |
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