WO2006015642A3 - Elektrisches bauelement in flip-chip-bauweise - Google Patents

Elektrisches bauelement in flip-chip-bauweise Download PDF

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Publication number
WO2006015642A3
WO2006015642A3 PCT/EP2005/006165 EP2005006165W WO2006015642A3 WO 2006015642 A3 WO2006015642 A3 WO 2006015642A3 EP 2005006165 W EP2005006165 W EP 2005006165W WO 2006015642 A3 WO2006015642 A3 WO 2006015642A3
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WO
WIPO (PCT)
Prior art keywords
chip
flip
electric component
orientation
thermal expansion
Prior art date
Application number
PCT/EP2005/006165
Other languages
English (en)
French (fr)
Other versions
WO2006015642A2 (de
Inventor
Hans Krueger
Karl Nicolaus
Juergen Portmann
Peter Selmeier
Original Assignee
Epcos Ag
Hans Krueger
Karl Nicolaus
Juergen Portmann
Peter Selmeier
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epcos Ag, Hans Krueger, Karl Nicolaus, Juergen Portmann, Peter Selmeier filed Critical Epcos Ag
Priority to KR1020077002497A priority Critical patent/KR101148542B1/ko
Priority to JP2007524192A priority patent/JP2008508739A/ja
Priority to US11/659,146 priority patent/US7518249B2/en
Publication of WO2006015642A2 publication Critical patent/WO2006015642A2/de
Publication of WO2006015642A3 publication Critical patent/WO2006015642A3/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14132—Square or rectangular array being non uniform, i.e. having a non uniform pitch across the array
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L2924/00013—Fully indexed content
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

Die Erfindung betrifft ein elektrisches Bauelement mit einem Trägersubstrat (1), der einen thermischen Ausdehnungskoeffizient αp aufweist, und einem Chip (2), der auf dem Trägersubstrat (1) in Flip-Chip-Bauweise mittels Bumps (31 bis 34) befestigt ist. Der Chip (2) weist in einer ersten Vorzugsrichtung x1 einen thermischen Ausdehnungskoeffizient α1 auf, wobei Δα1 = |αp - α1| die erste Ausdehnungsdifferenz ist. Der Chip (2) weist in einer zweiten Vorzugsrichtung x2 einen thermischen Ausdehnungskoeffizient α2 auf, wobei Δα2 = |αp - α2| die zweite Ausdehnungsdifferenz ist. Δx1 ist der Abstand zwischen den Mitten (310, 320) der endständigen Bumps (31, 32) in Richtung x1. Δx2 ist der Abstand zwischen den Mitten (330, 340) der endständigen Bumps (33, 34) in Richtung x2. Dabei gilt Δx1 < Δx2 bei Δαx1 > Δα2 und Δx1 > Δx2 bei Δα1 < Δα2. Dadurch gelingt es, die bei Temperaturänderungen entstehende und auf die endständigen Bumps wirkende Scherkraft zu minimieren.
PCT/EP2005/006165 2004-08-04 2005-06-08 Elektrisches bauelement in flip-chip-bauweise WO2006015642A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020077002497A KR101148542B1 (ko) 2004-08-04 2005-06-08 플립 칩 구성을 갖는 전기 소자
JP2007524192A JP2008508739A (ja) 2004-08-04 2005-06-08 フリップチップ構造の電気素子
US11/659,146 US7518249B2 (en) 2004-08-04 2005-06-08 Electric component with a flip-chip construction

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004037817.7 2004-08-04
DE102004037817.7A DE102004037817B4 (de) 2004-08-04 2004-08-04 Elektrisches Bauelement in Flip-Chip-Bauweise

Publications (2)

Publication Number Publication Date
WO2006015642A2 WO2006015642A2 (de) 2006-02-16
WO2006015642A3 true WO2006015642A3 (de) 2006-09-08

Family

ID=34971557

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/006165 WO2006015642A2 (de) 2004-08-04 2005-06-08 Elektrisches bauelement in flip-chip-bauweise

Country Status (5)

Country Link
US (1) US7518249B2 (de)
JP (1) JP2008508739A (de)
KR (1) KR101148542B1 (de)
DE (1) DE102004037817B4 (de)
WO (1) WO2006015642A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10301934A1 (de) * 2003-01-20 2004-07-29 Epcos Ag Elektrisches Bauelement mit verringerter Substratfläche
US7608789B2 (en) * 2004-08-12 2009-10-27 Epcos Ag Component arrangement provided with a carrier substrate
DE102005008512B4 (de) 2005-02-24 2016-06-23 Epcos Ag Elektrisches Modul mit einem MEMS-Mikrofon
DE102005008511B4 (de) * 2005-02-24 2019-09-12 Tdk Corporation MEMS-Mikrofon
DE102005008514B4 (de) * 2005-02-24 2019-05-16 Tdk Corporation Mikrofonmembran und Mikrofon mit der Mikrofonmembran
DE102005053765B4 (de) * 2005-11-10 2016-04-14 Epcos Ag MEMS-Package und Verfahren zur Herstellung
DE102005053767B4 (de) * 2005-11-10 2014-10-30 Epcos Ag MEMS-Mikrofon, Verfahren zur Herstellung und Verfahren zum Einbau
US7858438B2 (en) * 2007-06-13 2010-12-28 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
JP6099116B2 (ja) * 2011-12-12 2017-03-22 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． バンプ付きｉｃチップの回路基板上への実装装置及び実装方法
DE102013106353B4 (de) * 2013-06-18 2018-06-28 Tdk Corporation Verfahren zum Aufbringen einer strukturierten Beschichtung auf ein Bauelement
TWI681524B (zh) 2017-01-27 2020-01-01 日商村田製作所股份有限公司 半導體晶片
JP6963448B2 (ja) * 2017-09-13 2021-11-10 太陽誘電株式会社 電子部品
US11244876B2 (en) 2019-10-09 2022-02-08 Microchip Technology Inc. Packaged semiconductor die with micro-cavity

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000070671A1 (en) * 1999-05-17 2000-11-23 Telefonaktiebolaget Lm Ericsson Mounting arrangement for a semiconductor element
EP1333494A2 (de) * 2002-01-25 2003-08-06 Texas Instruments Incorporated Halbleiterbauelement und Fertigungsverfahren für die Halbleiteranordnung
US20040094842A1 (en) * 1999-05-10 2004-05-20 Jimarez Miguel A. Flip chip C4 extension structure and process

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JP2000114916A (ja) * 1998-09-29 2000-04-21 Nec Corp 表面弾性波デバイス及びその製造方法
JP2001267881A (ja) * 2000-03-17 2001-09-28 Fujitsu Media Device Kk 弾性表面波デバイス及びこれを用いた通信装置、並びにアンテナデュプレクサ
JP2002124848A (ja) * 2000-10-17 2002-04-26 Tdk Corp 表面弾性波素子、電子部品及びその搭載方法
JP2002344284A (ja) * 2001-03-14 2002-11-29 Murata Mfg Co Ltd 弾性表面波装置、および、これを搭載した通信装置
JP2002299996A (ja) * 2001-03-30 2002-10-11 Kyocera Corp 電子部品装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040094842A1 (en) * 1999-05-10 2004-05-20 Jimarez Miguel A. Flip chip C4 extension structure and process
WO2000070671A1 (en) * 1999-05-17 2000-11-23 Telefonaktiebolaget Lm Ericsson Mounting arrangement for a semiconductor element
EP1333494A2 (de) * 2002-01-25 2003-08-06 Texas Instruments Incorporated Halbleiterbauelement und Fertigungsverfahren für die Halbleiteranordnung

Also Published As

Publication number Publication date
US7518249B2 (en) 2009-04-14
KR101148542B1 (ko) 2012-05-29
KR20070040382A (ko) 2007-04-16
DE102004037817A1 (de) 2006-03-16
US20080048317A1 (en) 2008-02-28
JP2008508739A (ja) 2008-03-21
WO2006015642A2 (de) 2006-02-16
DE102004037817B4 (de) 2014-08-07

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