WO2006012847A1 - Composant a semi-conducteur de puissance vertical comprenant une puce a semi-conducteur, et procede pour le realiser - Google Patents

Composant a semi-conducteur de puissance vertical comprenant une puce a semi-conducteur, et procede pour le realiser Download PDF

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Publication number
WO2006012847A1
WO2006012847A1 PCT/DE2005/001296 DE2005001296W WO2006012847A1 WO 2006012847 A1 WO2006012847 A1 WO 2006012847A1 DE 2005001296 W DE2005001296 W DE 2005001296W WO 2006012847 A1 WO2006012847 A1 WO 2006012847A1
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Prior art keywords
power semiconductor
semiconductor chip
metal plate
semiconductor device
upper side
Prior art date
Application number
PCT/DE2005/001296
Other languages
German (de)
English (en)
Inventor
Khalil Hosseini
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Infineon Technologies Ag
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Publication of WO2006012847A1 publication Critical patent/WO2006012847A1/fr

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Definitions

  • the invention relates to a vertical deskleiterbau ⁇ part with a semiconductor chip and method for producing the same.
  • Vertical power semiconductor components have semiconductor chips whose semiconductor elements, such as diodes and transistors, are vertically structured, the back side of the semiconductor chip forming a large-area electrode of the vertical structure.
  • Such vertical power semiconductor components with a corresponding semiconductor chip structure are also known as "COOL-MOS" semiconductor elements.
  • the publication DE 101 34 943 discloses a vertical power semiconductor component in which no solder balls are used between the semiconductor chip and the flat conductors, but a multiplicity of parallel connected bonding connections, in the form of thermocompression heads on the top side of a
  • the upper side of the semiconductor chip is not sufficient to apply a sufficient number of bonding connections.
  • the power semiconductor component known from DE 101 34 943 has the disadvantage that the power supply can not be uniformly distributed to the active top side of the semiconductor chip, so that local overheating can occur.
  • the known structure has the disadvantage that in the production of the multiplicity of bonding connections, the semiconductor chip is subject to multiple mechanical high loads locally, which is too high
  • Microcracks and thus can lead to failure of the power semiconductor component.
  • the object of the invention is to overcome the disadvantages of the prior art and to provide a vertical cruschleiter ⁇ component, and a method for its preparation, so that the mechanical stress is reduced in the manufacture. Furthermore, the number of parallel bond connections should be made possible regardless of the size of the surface of the semiconductor chip. Finally, local overheating of the active top side of the semiconductor chip during operation of the power semiconductor device should be prevented.
  • a vertical power semiconductor component is created with a semiconductor chip and a method for its production.
  • the semiconductor chip has on its upper side a multiplicity of distributed contact surfaces of a common upper-side electrode.
  • a counterelectrode is arranged on the rear side and connected to a first external connection of the power semiconductor component.
  • the upper side of the semiconductor chip has a metal plate, the back side of which is connected to the plurality of contact surfaces of the top side electrode in a materially bonded manner.
  • An upper side of the metal plate opposite the rear side has bonding connections to contact connection surfaces, which are electrically connected to at least one common second external connection of the power semiconductor component.
  • Such a power semiconductor device has the advantage that a plurality of a few square micrometer-sized Kon ⁇ contact surfaces on the upper side of the semiconductor device can be connected in parallel through the metal plate to a common upper side electrode.
  • This metal plate is self-supporting, so that the size of its top is independent of the size of the top of the semiconductor chip.
  • the number of bond connections and thus of the bond connections on the upper side of the metal plate can be increased as desired so that the maximum permissible current density per boron connection is not exceeded and premature failure of the power semiconductor device due to overloading of one of these bond connections is thus prevented.
  • a further advantage of this solution is that the common upper-side electrode in the form of a metal plate seals the current densities onto the multiplicity of contact areas on the upper side of the semiconductor chip which are only a few square micrometers in size evenly distributed, thus preventing local current density peaks and thus local overheating of the power semiconductor elements of the power semiconductor chip.
  • the metal plate compares advantageously the heat distribution on the upper side of the semiconductor chip and additionally ensures a uniform current distribution.
  • the material of this metal plate preferably has copper or a copper alloy, especially since this material is characterized by its high electrical and thermal conductivity compared to other metals.
  • the planar extent of this metal plate is greater than the areal extent of the semiconductor chip. The bond connections originating from the upper side of the metal plate are connected to contact connection surfaces.
  • der ⁇ like contact pads are arranged on comb-shaped flat conductors. These comb-shaped flat conductors have inner comb conductors with the contact pads for the bond connections as comb teeth. The comb back closes these inner flat conductors and merges into an outer flat conductor as a second outer connection.
  • This embodiment of the invention has the advantage that the sensitive Bondverbin ⁇ applications and the transition to inner flat conductors are still arranged within a plastic housing, while outwardly only a single second outer terminal is guided by corre sponding training of the comb back.
  • the power semiconductor device is a vertically structured power diode.
  • the first external connection is the cable
  • the mode of the power diode and the second external terminal forms the anode of the power diode.
  • the anode of such a power semiconductor device has a multiplicity of a few square micrometre-sized contact surfaces, which are joined together by the metal plate of the component according to the invention to form a common top side electrode and are then led via a corresponding number of bond connections to the second external connection.
  • the metal plate As a common anode of a plurality of anode electrodes of the semiconductor chip, local forward current peaks are prevented, especially as the metal plate distributes the current supply via the bond bonds uniformly to the multiplicity of a few square micrometer-sized anode electrodes. By avoiding local current peaks, local overheating of the power semiconductor diode is avoided at the same time.
  • the first outer terminal which is connected to the rear side of the semiconductor chip, is a drain outer terminal of a semiconductor chip with vertically structured MOS elements.
  • the second outer terminal is a source outer terminal which is electrically connected via a plurality of bond connections and via the metal plate to a multiplicity of source contact areas of the semiconductor chip distributed on the upper side of the semiconductor chip.
  • this embodiment of the invention has at least one further external connection as a gate external connection, which is electrically connected via at least one bond connection to a gate contact surface on the upper side of the semiconductor chip. This gate contact surface is in turn connected to a plurality of gate electrodes on the
  • the rear side of the semiconductor chip which is connected as a cathode or as a drain electrode of the power semiconductor component, may preferably have a solderable metallization, so that soldering on a chip island of a printed circuit board or a flat conductor structure is possible.
  • the chip island can be designed as a heat conduction block, which at the same time forms the first external connection of the power semiconductor component.
  • Such a structure of the power semiconductor device has the advantage that to even out the current and heat distribution on the upper side of the semiconductor chip through the metal plate, a further dissipation of heat loss through the heat conduction block is now possible. Due to the massive homogenization of heat and heat dissipation, it is possible to allow a higher current density in the semiconductor chip and thus smaller structures in the semiconductor chip.
  • a metal diffusion-inhibiting multilayer coating is arranged between the metal plate on the upper side of the semiconductor chip and the bonding connections on the upper side of the metal plate. This metal-diffusion-inhibiting multi-layer coating ensures that metal atoms do not diffuse into the boundary layer for bonding the bonding wires and embrittle the bonding connections.
  • such a metal diffusion-inhibiting multilayer coating improves the adhesion of the bonding wires on the metal plate.
  • the metal layers of the multilayer coating improve bonding when bonding the bonding wires to the metal plate.
  • a so-called "purple plague" namely an effect in which a diffusion of copper ions from the metal plate takes place into the surface of the bonding connection takes place.
  • gold ions may also diffuse from the bonding pad into the surface of the metal plate.
  • Such diffusion is prevented, for example, by a nickel layer or a titanium or tungsten layer.
  • the additional working steps to be provided for the diffusion barrier on the metal plate are not particularly expensive.
  • Such diffusion barriers may, for example, be sputtered, applied chemically or electrochemically by deposition.
  • the metal diffusion-inhibiting coating has a lower layer Layer of titanium or titanium alloy on.
  • This titanium layer serves mainly to improve the adhesion of the metal-diffusion-inhibiting coating.
  • a middle layer represents the actual metal-diffusion-inhibiting metallization, while an upper layer improves the bondability of the entire metal-diffusion-inhibiting coating.
  • the top layer of the diffusion-inhibiting coating has a layer of gold, silver, aluminum, palladium or alloys thereof. These layers are characterized by being bondable and undergoing intermetallic or eutectic bonding with the bonding wire material.
  • the bonding wires themselves have gold, aluminum, palladium or alloys thereof. These materials have the advantage that they are electrically highly conductive and have a low contact resistance.
  • the bonding wires are led from the metal plate to corresponding contact pads. These contact pads are arranged on inner flat conductors or on a wiring structure of a printed circuit board.
  • the contact pads preferably have a coating of gold, silver, aluminum, Ni, NiP, palladium or alloys thereof.
  • the type of coating for the contact pads depends on the material of the bonding wires and is adapted according to the bonding wires. In a further embodiment, it is provided that the cohesive connection between the back of the metal plate and the contact surfaces has a conductive adhesive.
  • This solution has the advantage that the conductive adhesive can be applied over a large area to the large number of contact areas on the top side of the semiconductor chip, which are only a few square micrometers in size, without already exerting locally a bond compression pressure.
  • a eutectic solder connection or a diffusion solder connection can also be provided for this coherent connection between the rear side of the metal plate and the multiplicity of contact surfaces.
  • the corresponding components of a eutectic solder connection or a diffusion solder connection both on the back of the metal plate and on the entire surface of the semiconductor chip, leaving contact surfaces that are not datazupar applied.
  • the advantage here is that both the eutectic solder connection and the diffusion solder connection can be performed simultaneously for a multiplicity of contact surfaces.
  • the design of the external connections is relatively variable.
  • the outer terminals of a plastic housing composition protrude laterally at the level of the underside of the power semiconductor component. This has the advantage that the plastic housing compound can mechanically fix and anchor these outstanding external connections via corresponding internal flat conductors in the plastic housing.
  • the outer terminals are on the underside, e.g. in
  • the structure of the power semiconductor component preferably corresponds to a "COOL-MOS" power semiconductor element.
  • Derar ⁇ term "COOL-MOS" power semiconductor elements are characterized by their high withstand voltage at the same time high permissible current density.
  • a method for producing a power semiconductor component from a plurality of component components comprises the following method steps. First, a semiconductor chip is produced. This semiconductor chip has on its upper side a multiplicity of contact surfaces which belong to a common upper-side electrode. Furthermore, the semiconductor chip has a rear side, on which a back side contact is arranged as a counterelectrode.
  • either a flat conductor frame or a printed circuit board can be produced. These have at least one chip island, which is connected to a first external connection. Furthermore, they have contact connection surfaces for bond connections, which are electrically connected to at least one second external connection. After producing the leadframe or a circuit board, the semiconductor chip can be fi xed with its rear side on the chip island and is thus connected to the first external terminal of the power semiconductor component.
  • a material-locking connection of a metal plate as a common upper-side electrode is materially connected to the plurality of contact surfaces on the upper side of the semiconductor chip.
  • a common upper side electrode is created for the semiconductor chip, which in its planar extent is independent of the semiconductor chip.
  • a plurality of bond connections are now attached, which connect the metal plate to the contact connection surfaces of the second external connection.
  • the components of the component are connected in a plastic housing composition leaving the external connections free.
  • a power semiconductor diode having a cathode as the first external terminal and an anode as the second external terminal can preferably be produced. While the cathode is connected to the first outer terminal via the rear side of the semiconductor chip, the anode is connected to the metal plate and is connected to the corresponding outer terminal via a plurality of bonding wires.
  • the surface of the metal plate is crucial for a secure bond.
  • the metal plate is a free-floating plate, so that bond connections outside the planar extent of the semiconductor chip are also possible.
  • an increased current density as occurs in a miniaturized semiconductor chip, can still be produced with correspondingly many bond connections to the second external connection.
  • the reliability of the bond connection can be further increased by coating the metal plate selectively or as a whole with a multilayer metal diffusion-inhibiting coating for bonding with the subsequent process steps in a method example.
  • the top of the metal plate is cleaned by back sputtering or dry etching.
  • a first lower Layer of titanium or a titanium alloy applied to the metal plate to improve adhesion.
  • the actual metal diffusion-inhibiting layer is applied to the adhesion-promoting layer as a second middle layer of nickel, vanadium or alloys thereof.
  • a third upper layer of gold, silver, aluminum, palladium or alloys thereof is applied as a bonding agent and / or as a metal connector for corresponding bonding wires.
  • This application of the first to third layers can also be done selectively by applying the three metal layers only at the positions where bonding wires are subsequently connected to the metal plate.
  • a selective application of the layers can be done by photolithography. Such selective application of the layers can also be achieved by means of
  • Printing technique with a screen printing technique and / or a stencil printing technique are preferred.
  • the application of the layers can also be realized selectively by means of a jet printing technique. If no selective application takes place, the bonding connections on the metal plate can be randomly distributed.
  • the contact pads on corresponding inner flat conductors or on a corresponding wiring structure of a printed circuit board can be coated with a gold and / or aluminum alloy to improve the bondability.
  • This has the advantage that the bonded wires of an aluminum or gold alloy can enter into a eutectic connection whose melting point is lower than the melting points of gold or aluminum.
  • a heat conduction block are applied, which also forms the first outer terminal. This has the advantage that the dissipation of heat from the rear side of the semiconductor chip for the power semiconductor component is improved.
  • the service life of the power semiconductor component can thus be extended considerably or specific values, such as, for example, the power loss, can be correspondingly increased without damaging the component and without reducing the service life of the power semiconductor component.
  • FIG. 1 schematically shows a perspective view of components of a power semiconductor component of a first embodiment of the invention before being packaged in a plastic housing composition
  • FIG. 2 shows a schematic cross section through the power semiconductor component of the first embodiment according to FIG.
  • FIG. 1 A first figure.
  • FIG. 3 shows a schematic perspective view of FIG
  • FIG. 4 shows a schematic cross section through the power semiconductor component of the first embodiment of the invention according to FIG. 3;
  • FIGS. 5 to 8 show schematic, perspective views of the assembly of the components of a power semiconductor device according to the first embodiment of the invention
  • FIG. 5 shows a schematic, perspective view of a heat conduction block with chip island and applied semiconductor chip
  • FIG. 6 shows a schematic, perspective view according to FIG. 5 after applying a cohesive material to the active upper side of the semiconductor chip
  • FIG. 7 shows a schematic, perspective view according to FIG. 6 after application of a metal plate as upper side electrode to the active upper side of FIG
  • FIG. 8 shows a schematic, perspective view according to FIG. 7 after application of bonding connections to the metal plate according to the embodiment according to FIG. 1.
  • FIG. 1 shows a schematic, perspective view of components of a power semiconductor component of a first embodiment of the invention prior to packaging of the components in a plastic housing composition.
  • the components are constructed in this embodiment of the invention on a dressinglei ⁇ processing block 20, which is formed at the same time as Drainauße- nan gleich 19 and forms part of the underside 22 'of the power semiconductor device.
  • This heat conduction block 20 is connected to the rear side 7 of the semiconductor chip 2 via a chip island 9.
  • the semiconductor chip 2 via a rear side contact 8 on its back 7 and the chip island 9 and the heat conduction block 20 are electrically connected to the drain outer terminal 19.
  • a gate contact surface 6 is arranged, which is guided via a bond connection 26 to a gate external connection.
  • This gate contact surface 6 is connected to a multiplicity of gate electrodes of the vertical power semiconductor component via printed conductors (not shown) on the upper side 3 of the semiconductor chip 2. Since the gate of such a power semiconductor component is potential-controlled, the switching currents are relatively low, so that a single bond connection 26 can ensure the supply of the gate electrodes.
  • the total current between source and drain to be switched via the source electrodes is substantially greater, so that a multiplicity of bond connections 14 is required in order to conduct the source-drain current.
  • the few square-micron-sized source electrodes on the upper side 3 of the semiconductor chip 2 are connected in parallel through a metal plate 10 to a common upper-side electrode 30.
  • this metal plate 10 is larger in its planar extent than the active upper side 3 of the semiconductor chip 2.
  • a top electrode 30 can be provided whose areal extent is independent of the planar extent of the upper side 3 of the semiconductor chip 2.
  • a plurality of bonding connections 36 are arranged on the upper side 11 of the metal plate 10, which pass into bonding connections 14 and supply the metal plate 10 formed as a top side electrode 30 with current.
  • this metal plate 10 provides a uniform distribution of the current density from the discrete bonding connections 14 to the multiplicity of source electrodes, so that current peaks which could lead to thermal overheating are avoided.
  • the metal plate 10 provides for a thermal and also for an electrical equal distribution of the energy flows into the semiconductor chip.
  • FIG. 2 shows a schematic cross section through the power semiconductor component 1 of the first embodiment of the invention according to FIG. 1. This cross section illustrates that the components shown in FIG. 1 are now packaged in a plastic housing composition 21. Furthermore, the construction of the power semiconductor device 1 according to the invention is shown in detail.
  • the heat conduction block 20 forms the drain outer terminal 19 and at the same time a part of the lower side 22 of the power semiconductor component 1.
  • a gate outer terminal 18 and a source outer terminal 15 are led out laterally from the semiconductor component 1, which are in turn connected to corresponding inner flat conductors 16.
  • coatings 24 are arranged as contact pads 13, these coatings 24 consisting of a bondable material, preferably of a silver alloy.
  • the gate outer terminal 18 is connected via the inner flat conductor 16, the coating 24 and the bonding connection 26 to the gate contact surface 6 on the active upper side 3 of the semiconductor chip 2.
  • the outer external contact connection 15 is connected via an inner flat conductor 16, a coating 24 and a contact terminal surface 13 via a plurality of bond connections.
  • gene 14 connected to the metal plate 10, wherein this Metall ⁇ plate 10 has a multi-layer, not shown metal diffusion-inhibiting coating, which ensures that the Me ⁇ tallmaterial of the bond 14 is not embrittled by diffusion processes of the metal material of the metal plate 10.
  • the multi-layer coating of the metal plate 10 promotes the bonding process.
  • the metal plate 10 is connected to the plurality of source contact areas 5 on the upper side 3 of the semiconductor chip 2 via a substance-coherent connection 25.
  • the rear side 7 of the semiconductor chip 2 is electrically connected via a coating 23 to the upper side 34 of the heat conduction block 20 and thus to the drain outer connection 19.
  • FIG. 3 shows a schematic, perspective view of components of a power semiconductor component of a second embodiment of the invention prior to packaging the components in a plastic housing composition.
  • Components with the same functions as in the preceding figures are identified by the same reference numerals and are not discussed separately.
  • the components form a vertical power semiconductor diode.
  • the common top contact 30 in the form of a metal plate 10 forms the anode 27, which is composed on the upper side 3 of the semiconductor chip 2 of a plurality of anode electrodes. These anode electrodes of a few square microns in size are closed in parallel via the common top electrode 30 in the form of the metal plate 10, so that a plurality of
  • Bond connections 14 can lead the diode current.
  • the bonding connections 14 are in electrical contact via bonding connections 36 with the metal plate 10.
  • the cathode 28 of this The power semiconductor diode is formed by the rear side 7 of the semiconductor chip 2 and is electrically connected via a rear-side contact 8 to a chip island 9, which merges into a heat conduction block 20.
  • the heat conduction block 20 is in turn connected to an outer flat conductor 17 as the cathode connection 37 and forms a counter electrode 29 to the upper side electrode 30.
  • FIG. 4 shows a schematic cross section through the vertical power semiconductor component 40 of the second embodiment of the invention according to FIG. 3.
  • the plurality of anode electrodes 38 form contact surfaces 4 on the top side of the semiconductor chip 2 and become a common top side electrode 30 the metal plate 10 interconnected.
  • the underside 12 of the metal plate 10 has a material-like connection 25 with the contact surfaces 4.
  • This cohesive connection 25 may be a conductive adhesive or a eutectic solder connection or else a diffusion solder connection.
  • the metal plate 10 can be connected to the plurality of anode electrodes 38 as a common top electrode 30 via the integral connection 25.
  • a plurality of bonding connections 36 are arranged, which are connected via bonding wires 33 and corresponding contact pads 13 to an inner flat conductor 16, which merges into an outer flat conductor 17 and forms a second outer connection 32, which is connected to the Anode 27 of the vertical power semiconductor device 40 is connected.
  • the heat conduction block 20 passes directly into a first Cru ⁇ connection 31, which is designed as discourseflachleiter 17 and has a bore 39, with which the cathode 28 of vertical power semiconductor diode, for example, with a Massepo ⁇ potential, can be connected.
  • FIGS. 5 to 8 show schematic, perspective views of the assembly of the components of a vertical one
  • FIG. 5 shows a schematic, perspective view of a heat conduction block 20 with chip island 9 and applied semiconductor chip 2.
  • This semiconductor chip 2 is connected with its rear side 7 to the chip island 9 via a back side contact 8.
  • the semiconductor chip 2 On its upper side 3, the semiconductor chip 2 has a plurality of source electrodes which are a few square microns in size.
  • the upper side 3 has a single gate contact surface 6, via which a multiplicity of gate electrodes can be reached on the upper side 3 of the semiconductor chip 2.
  • FIG. 6 shows a schematic, perspective view according to FIG. 5 after applying a material-locking material 35 to the active upper side 3 of the semiconductor chip 2.
  • This material-locking material 35 is applied only to the region of the upper side 3 of the semiconductor chip 2, which is the source - Contact surfaces 5, as shown in Figure 2, auf ⁇ has.
  • This cohesive material 35 may be a conductive adhesive or a solder material.
  • FIG. 7 shows a schematic, perspective view according to FIG. 6 after applying a metal plate 10 as upper side electrode 30 to the active upper side 3 of the semiconductor chip 2.
  • the metal plate 10 almost completely covers the upper side 3 of the semiconductor chip 2 and leaves only in one Recess 41 access to the gate contact surface 6 to.
  • the self-supporting metal plate 10 is larger than the upper side 3 of the semiconductor chip 2 and can thus accommodate a plurality of bonding connections.
  • FIG. 8 shows a schematic, perspective view according to FIG. 7 after application of bonding connections 36 to the metal plate 10 according to the first embodiment of the invention according to FIG. 1.
  • Components having the same functions as in the preceding figures are identified by the same reference numerals and not discussed separately. A de ⁇ detailed description of Figure 8 is unnecessary, since this embodiment of the invention corresponds exactly to the representation of Figure 1.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un composant à semi-conducteur de puissance vertical (1) comprenant une puce à semi-conducteur (2) qui présente une pluralité de faces de contact (4) d'une électrode de côté supérieur commune (30), réparties sur le côté supérieur (3). Le côté arrière (7) de la puce à semi-conducteur, forme une contre-électrode (29) avec une première borne de connexion extérieure du composant à semi-conducteur de puissance, alors que le côté supérieur (3) de la puce à semi-conducteur (2) présente une plaque métallique (10) en tant qu'électrode de côté supérieur commune (30), ladite plaque métallique étant reliée par liaison de matière aux faces de contact. Le côté supérieur (11) de la plaque métallique est connecté électriquement à une seconde borne de connexion du composant à semi-conducteur de puissance, par des liaisons de métallisation (14).
PCT/DE2005/001296 2004-07-29 2005-07-21 Composant a semi-conducteur de puissance vertical comprenant une puce a semi-conducteur, et procede pour le realiser WO2006012847A1 (fr)

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US7851927B2 (en) 2006-12-19 2010-12-14 Infineon Technologies Ag Semiconductor component comprising a semiconductor chip and semiconductor component carrier with external connection strips
EP2290683A1 (fr) * 2009-08-27 2011-03-02 ABB Research Ltd Interconexion d'un module électronique
US8013441B2 (en) 2005-10-14 2011-09-06 Infineon Technologies Ag Power semiconductor device in lead frame employing connecting element with conductive film
US9318421B2 (en) 2011-10-15 2016-04-19 Danfoss Silicon Power Gmbh Power semiconductor chip with a metallic moulded body for contacting thick wires or strips and method for the production thereof
US9786627B2 (en) 2011-10-15 2017-10-10 Danfoss Silicon Power Gmbh Method for creating a connection between metallic moulded bodies and a power semiconductor which is used to bond to thick wires or strips
EP3385983A1 (fr) * 2017-04-04 2018-10-10 Heraeus Deutschland GmbH & Co. KG Système adaptateur destiné à agrandir la zone de contact d'au moins une surface de contact sur au moins un composant électronique et procédé d'agrandissement de zone de contact
US10607962B2 (en) 2015-08-14 2020-03-31 Danfoss Silicon Power Gmbh Method for manufacturing semiconductor chips
WO2020201005A1 (fr) * 2019-04-05 2020-10-08 Danfoss Silicon Power Gmbh Module semi-conducteur et procédé destiné à le fabriquer

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DE102006015447B4 (de) 2006-03-31 2012-08-16 Infineon Technologies Ag Leistungshalbleiterbauelement mit einem Leistungshalbleiterchip und Verfahren zur Herstellung desselben
DE102016106113A1 (de) 2016-04-04 2017-10-05 Infineon Technologies Austria Ag Halbbrückenschaltung und Clip-Draht-Packung

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US8013441B2 (en) 2005-10-14 2011-09-06 Infineon Technologies Ag Power semiconductor device in lead frame employing connecting element with conductive film
US7851927B2 (en) 2006-12-19 2010-12-14 Infineon Technologies Ag Semiconductor component comprising a semiconductor chip and semiconductor component carrier with external connection strips
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US9786627B2 (en) 2011-10-15 2017-10-10 Danfoss Silicon Power Gmbh Method for creating a connection between metallic moulded bodies and a power semiconductor which is used to bond to thick wires or strips
US10607962B2 (en) 2015-08-14 2020-03-31 Danfoss Silicon Power Gmbh Method for manufacturing semiconductor chips
EP3385983A1 (fr) * 2017-04-04 2018-10-10 Heraeus Deutschland GmbH & Co. KG Système adaptateur destiné à agrandir la zone de contact d'au moins une surface de contact sur au moins un composant électronique et procédé d'agrandissement de zone de contact
WO2018184755A1 (fr) * 2017-04-04 2018-10-11 Heraeus Deutschland GmbH & Co. KG Système adaptateur servant à agrandir une zone de contact d'au moins une surface de contact sur au moins un composant électronique et procédé servant à agrandir une zone de contact
WO2020201005A1 (fr) * 2019-04-05 2020-10-08 Danfoss Silicon Power Gmbh Module semi-conducteur et procédé destiné à le fabriquer

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