WO2006012847A1

WO2006012847A1 - Vertical power semiconductor component comprising a semiconductor chip, and method for producing the same

Info

Publication number: WO2006012847A1
Application number: PCT/DE2005/001296
Authority: WO
Inventors: Khalil Hosseini
Original assignee: Infineon Technologies Ag
Priority date: 2004-07-29
Filing date: 2005-07-21
Publication date: 2006-02-09
Also published as: DE102004036905A1

Abstract

The invention relates to a vertical power semiconductor component (1) comprising a semiconductor chip (2) provided with a plurality of contact surfaces (4) of a common upper side electrode (30), distributed over the upper side (3). The rear side (7) of the semiconductor chip forms a counter-electrode (29) with a first outer terminal of the power semiconductor component, while the upper side (3) of the semiconductor chip (2) comprises a metal plate (10) as a common upper side electrode (30), that is connected to the contact surfaces in a material fit. The upper side (11) of the metal plate is electrically connected to a second outer terminal of the power semiconductor component by means of bond connections (14).

Description

description

Vertical power semiconductor device with a Halbleiter¬ chip and method for producing the same

The invention relates to a vertical Leistungshalbleiterbau¬ part with a semiconductor chip and method for producing the same. Vertical power semiconductor components have semiconductor chips whose semiconductor elements, such as diodes and transistors, are vertically structured, the back side of the semiconductor chip forming a large-area electrode of the vertical structure. Such vertical power semiconductor components with a corresponding semiconductor chip structure are also known as "COOL-MOS" semiconductor elements.

Another power semiconductor device is known from the Druck¬ font PCT / US 99/12411 with Figure 3, in which a semiconductor chip 202 is attached via solder balls to flat conductors 206 and 208. A disadvantage of this design is that the contacts via solder balls are not particularly reliable. Particularly at higher temperatures and longer operating times, there is the danger of precipitation of these power semiconductor components due to increased thermal stresses between solder balls and flat conductors.

The publication DE 101 34 943 discloses a vertical power semiconductor component in which no solder balls are used between the semiconductor chip and the flat conductors, but a multiplicity of parallel connected bonding connections, in the form of thermocompression heads on the top side of a

Power semiconductor chips are arranged. However, this technical solution can only be used if a sufficiently large semiconductor chip top for attaching the plurality of bond leads and the size of the contact pads is sufficient to bond to bond leads.

With constantly decreasing structures and simultaneously increasing current densities of the power semiconductor chips, the upper side of the semiconductor chip is not sufficient to apply a sufficient number of bonding connections. Furthermore, the power semiconductor component known from DE 101 34 943 has the disadvantage that the power supply can not be uniformly distributed to the active top side of the semiconductor chip, so that local overheating can occur. Finally, the known structure has the disadvantage that in the production of the multiplicity of bonding connections, the semiconductor chip is subject to multiple mechanical high loads locally, which is too high

Microcracks and thus can lead to failure of the power semiconductor component.

The object of the invention is to overcome the disadvantages of the prior art and to provide a vertical Leistungshalbleiter¬ component, and a method for its preparation, so that the mechanical stress is reduced in the manufacture. Furthermore, the number of parallel bond connections should be made possible regardless of the size of the surface of the semiconductor chip. Finally, local overheating of the active top side of the semiconductor chip during operation of the power semiconductor device should be prevented.

This object is achieved with the subject of the independent claims. Advantageous developments of the invention will become apparent from the dependent claims. According to the invention, a vertical power semiconductor component is created with a semiconductor chip and a method for its production. The semiconductor chip has on its upper side a multiplicity of distributed contact surfaces of a common upper-side electrode. A counterelectrode is arranged on the rear side and connected to a first external connection of the power semiconductor component. The upper side of the semiconductor chip has a metal plate, the back side of which is connected to the plurality of contact surfaces of the top side electrode in a materially bonded manner. An upper side of the metal plate opposite the rear side has bonding connections to contact connection surfaces, which are electrically connected to at least one common second external connection of the power semiconductor component.

Such a power semiconductor device has the advantage that a plurality of a few square micrometer-sized Kon¬ contact surfaces on the upper side of the semiconductor device can be connected in parallel through the metal plate to a common upper side electrode. This metal plate is self-supporting, so that the size of its top is independent of the size of the top of the semiconductor chip. The number of bond connections and thus of the bond connections on the upper side of the metal plate can be increased as desired so that the maximum permissible current density per boron connection is not exceeded and premature failure of the power semiconductor device due to overloading of one of these bond connections is thus prevented.

A further advantage of this solution is that the common upper-side electrode in the form of a metal plate seals the current densities onto the multiplicity of contact areas on the upper side of the semiconductor chip which are only a few square micrometers in size evenly distributed, thus preventing local current density peaks and thus local overheating of the power semiconductor elements of the power semiconductor chip. Thus, the metal plate compares advantageously the heat distribution on the upper side of the semiconductor chip and additionally ensures a uniform current distribution.

The material of this metal plate preferably has copper or a copper alloy, especially since this material is characterized by its high electrical and thermal conductivity compared to other metals. In order to provide a sufficient number of bonding connections on the upper side of the metal plate, the planar extent of this metal plate is greater than the areal extent of the semiconductor chip. The bond connections originating from the upper side of the metal plate are connected to contact connection surfaces.

In a preferred embodiment of the invention der¬ like contact pads are arranged on comb-shaped flat conductors. These comb-shaped flat conductors have inner comb conductors with the contact pads for the bond connections as comb teeth. The comb back closes these inner flat conductors and merges into an outer flat conductor as a second outer connection. This embodiment of the invention has the advantage that the sensitive Bondverbin¬ applications and the transition to inner flat conductors are still arranged within a plastic housing, while outwardly only a single second outer terminal is guided by corre sponding training of the comb back.

In a further preferred embodiment of the invention, the power semiconductor device is a vertically structured power diode. The first external connection is the cable The mode of the power diode and the second external terminal forms the anode of the power diode. The anode of such a power semiconductor device has a multiplicity of a few square micrometre-sized contact surfaces, which are joined together by the metal plate of the component according to the invention to form a common top side electrode and are then led via a corresponding number of bond connections to the second external connection. Due to the metal plate as a common anode of a plurality of anode electrodes of the semiconductor chip, local forward current peaks are prevented, especially as the metal plate distributes the current supply via the bond bonds uniformly to the multiplicity of a few square micrometer-sized anode electrodes. By avoiding local current peaks, local overheating of the power semiconductor diode is avoided at the same time.

In a further embodiment of the invention, the first outer terminal, which is connected to the rear side of the semiconductor chip, is a drain outer terminal of a semiconductor chip with vertically structured MOS elements. The second outer terminal is a source outer terminal which is electrically connected via a plurality of bond connections and via the metal plate to a multiplicity of source contact areas of the semiconductor chip distributed on the upper side of the semiconductor chip. In addition, this embodiment of the invention has at least one further external connection as a gate external connection, which is electrically connected via at least one bond connection to a gate contact surface on the upper side of the semiconductor chip. This gate contact surface is in turn connected to a plurality of gate electrodes on the

Semiconductor chip via a structured interconnect layer in conjunction. Since the gate electrodes of such a power semiconductor component require only a negligible small switching current, all the gate electrodes of the semiconductor chip can be combined to form a gate contact on the top side of the semiconductor chip and led to a gate external connection via a single bonding wire. This low current consumption is due to the fact that the gate electrodes of the semiconductor chip are potential-controlled and consequently extremely low currents are required in order to maintain the electronic power semiconductor component via the gate electrodes. Accordingly, a recess is provided in the metal plate on the upper side of the semiconductor chip, leaving the gate contact area free for attaching a single bonding wire for supplying the gate electrodes.

The rear side of the semiconductor chip, which is connected as a cathode or as a drain electrode of the power semiconductor component, may preferably have a solderable metallization, so that soldering on a chip island of a printed circuit board or a flat conductor structure is possible. In addition, the chip island can be designed as a heat conduction block, which at the same time forms the first external connection of the power semiconductor component.

Such a structure of the power semiconductor device has the advantage that to even out the current and heat distribution on the upper side of the semiconductor chip through the metal plate, a further dissipation of heat loss through the heat conduction block is now possible. Due to the massive homogenization of heat and heat dissipation, it is possible to allow a higher current density in the semiconductor chip and thus smaller structures in the semiconductor chip. In a further preferred embodiment of the invention, a metal diffusion-inhibiting multilayer coating is arranged between the metal plate on the upper side of the semiconductor chip and the bonding connections on the upper side of the metal plate. This metal-diffusion-inhibiting multi-layer coating ensures that metal atoms do not diffuse into the boundary layer for bonding the bonding wires and embrittle the bonding connections. Furthermore, such a metal diffusion-inhibiting multilayer coating improves the adhesion of the bonding wires on the metal plate. Finally, the metal layers of the multilayer coating improve bonding when bonding the bonding wires to the metal plate. With such a diffusion-inhibiting coating, a so-called "purple plague", namely an effect in which a diffusion of copper ions from the metal plate takes place into the surface of the bonding connection takes place. On the other hand, gold ions may also diffuse from the bonding pad into the surface of the metal plate.

Within the metal diffusion-inhibiting multilayer coating, such diffusion is prevented, for example, by a nickel layer or a titanium or tungsten layer. The additional working steps to be provided for the diffusion barrier on the metal plate are not particularly expensive. Such diffusion barriers may, for example, be sputtered, applied chemically or electrochemically by deposition. With such a configuration of the upper side of the metal plate, it is possible in a particularly simple manner to produce an electrical component which can be reliably operated even at high temperatures for a long time.

In a further embodiment of the invention, the metal diffusion-inhibiting coating has a lower layer Layer of titanium or titanium alloy on. This titanium layer serves mainly to improve the adhesion of the metal-diffusion-inhibiting coating. A middle layer represents the actual metal-diffusion-inhibiting metallization, while an upper layer improves the bondability of the entire metal-diffusion-inhibiting coating.

As a middle layer and thus as a metal diffusion-inhibiting layer, a material consisting of titanium, nickel, vanadium or alloys thereof is used. These materials, as a closed layer, prevent the penetration of copper atoms into the bonding connections, for example from gold. In a further embodiment of the invention, the top layer of the diffusion-inhibiting coating has a layer of gold, silver, aluminum, palladium or alloys thereof. These layers are characterized by being bondable and undergoing intermetallic or eutectic bonding with the bonding wire material.

The bonding wires themselves have gold, aluminum, palladium or alloys thereof. These materials have the advantage that they are electrically highly conductive and have a low contact resistance. The bonding wires are led from the metal plate to corresponding contact pads. These contact pads are arranged on inner flat conductors or on a wiring structure of a printed circuit board. The contact pads preferably have a coating of gold, silver, aluminum, Ni, NiP, palladium or alloys thereof. The type of coating for the contact pads depends on the material of the bonding wires and is adapted according to the bonding wires. In a further embodiment, it is provided that the cohesive connection between the back of the metal plate and the contact surfaces has a conductive adhesive. This solution has the advantage that the conductive adhesive can be applied over a large area to the large number of contact areas on the top side of the semiconductor chip, which are only a few square micrometers in size, without already exerting locally a bond compression pressure. In addition, a eutectic solder connection or a diffusion solder connection can also be provided for this coherent connection between the rear side of the metal plate and the multiplicity of contact surfaces. For this purpose, the corresponding components of a eutectic solder connection or a diffusion solder connection, both on the back of the metal plate and on the entire surface of the semiconductor chip, leaving contact surfaces that are not zusammenzuschalten parallel applied. The advantage here is that both the eutectic solder connection and the diffusion solder connection can be performed simultaneously for a multiplicity of contact surfaces.

The design of the external connections is relatively variable. In a preferred embodiment of the invention, the outer terminals of a plastic housing composition protrude laterally at the level of the underside of the power semiconductor component. This has the advantage that the plastic housing compound can mechanically fix and anchor these outstanding external connections via corresponding internal flat conductors in the plastic housing. In alternative embodiments of the invention, the outer terminals are on the underside, e.g. in

Form of BGA arrangements (Ball Grid Array) arranged. In other housing forms, it is provided that external connections are arranged ange¬ both on the bottom and on the edge sides.

The structure of the power semiconductor component preferably corresponds to a "COOL-MOS" power semiconductor element. Derar¬ term "COOL-MOS" power semiconductor elements are characterized by their high withstand voltage at the same time high permissible current density.

A method for producing a power semiconductor component from a plurality of component components comprises the following method steps. First, a semiconductor chip is produced. This semiconductor chip has on its upper side a multiplicity of contact surfaces which belong to a common upper-side electrode. Furthermore, the semiconductor chip has a rear side, on which a back side contact is arranged as a counterelectrode.

For receiving the semiconductor chip, either a flat conductor frame or a printed circuit board can be produced. These have at least one chip island, which is connected to a first external connection. Furthermore, they have contact connection surfaces for bond connections, which are electrically connected to at least one second external connection. After producing the leadframe or a circuit board, the semiconductor chip can be fi xed with its rear side on the chip island and is thus connected to the first external terminal of the power semiconductor component.

Subsequently, a material-locking connection of a metal plate as a common upper-side electrode is materially connected to the plurality of contact surfaces on the upper side of the semiconductor chip. With this cohesive connection From a plurality of contact surfaces through the metal plate, a common upper side electrode is created for the semiconductor chip, which in its planar extent is independent of the semiconductor chip. On the upper side of this metal plate, a plurality of bond connections are now attached, which connect the metal plate to the contact connection surfaces of the second external connection. Finally, the components of the component are connected in a plastic housing composition leaving the external connections free.

With such a method, a power semiconductor diode having a cathode as the first external terminal and an anode as the second external terminal can preferably be produced. While the cathode is connected to the first outer terminal via the rear side of the semiconductor chip, the anode is connected to the metal plate and is connected to the corresponding outer terminal via a plurality of bonding wires. The surface of the metal plate is crucial for a secure bond. For this purpose, the metal plate is a free-floating plate, so that bond connections outside the planar extent of the semiconductor chip are also possible. Thus, an increased current density, as occurs in a miniaturized semiconductor chip, can still be produced with correspondingly many bond connections to the second external connection.

The reliability of the bond connection can be further increased by coating the metal plate selectively or as a whole with a multilayer metal diffusion-inhibiting coating for bonding with the subsequent process steps in a method example. First, the top of the metal plate is cleaned by back sputtering or dry etching. Subsequently, a first lower Layer of titanium or a titanium alloy applied to the metal plate to improve adhesion. Thereafter, the actual metal diffusion-inhibiting layer is applied to the adhesion-promoting layer as a second middle layer of nickel, vanadium or alloys thereof. Finally, a third upper layer of gold, silver, aluminum, palladium or alloys thereof is applied as a bonding agent and / or as a metal connector for corresponding bonding wires.

This application of the first to third layers can also be done selectively by applying the three metal layers only at the positions where bonding wires are subsequently connected to the metal plate. A selective application of the layers can be done by photolithography. Such selective application of the layers can also be achieved by means of

Printing technique, with a screen printing technique and / or a stencil printing technique are preferred. However, the application of the layers can also be realized selectively by means of a jet printing technique. If no selective application takes place, the bonding connections on the metal plate can be randomly distributed.

The contact pads on corresponding inner flat conductors or on a corresponding wiring structure of a printed circuit board can be coated with a gold and / or aluminum alloy to improve the bondability. This has the advantage that the bonded wires of an aluminum or gold alloy can enter into a eutectic connection whose melting point is lower than the melting points of gold or aluminum.

Even before packaging the power semiconductor device components in a plastic housing composition can on the back the chip island, a heat conduction block are applied, which also forms the first outer terminal. This has the advantage that the dissipation of heat from the rear side of the semiconductor chip for the power semiconductor component is improved. The service life of the power semiconductor component can thus be extended considerably or specific values, such as, for example, the power loss, can be correspondingly increased without damaging the component and without reducing the service life of the power semiconductor component.

The invention will now be explained in more detail with reference to the accompanying figures.

FIG. 1 schematically shows a perspective view of components of a power semiconductor component of a first embodiment of the invention before being packaged in a plastic housing composition;

FIG. 2 shows a schematic cross section through the power semiconductor component of the first embodiment according to FIG

FIG. 1;

FIG. 3 shows a schematic perspective view of FIG

Components of a power semiconductor device of a second embodiment of the invention before Ver¬ pack in a plastic housing composition;

FIG. 4 shows a schematic cross section through the power semiconductor component of the first embodiment of the invention according to FIG. 3;

FIGS. 5 to 8 show schematic, perspective views of the assembly of the components of a power semiconductor device according to the first embodiment of the invention;

FIG. 5 shows a schematic, perspective view of a heat conduction block with chip island and applied semiconductor chip;

FIG. 6 shows a schematic, perspective view according to FIG. 5 after applying a cohesive material to the active upper side of the semiconductor chip;

FIG. 7 shows a schematic, perspective view according to FIG. 6 after application of a metal plate as upper side electrode to the active upper side of FIG

Semiconductor chips;

FIG. 8 shows a schematic, perspective view according to FIG. 7 after application of bonding connections to the metal plate according to the embodiment according to FIG. 1.

FIG. 1 shows a schematic, perspective view of components of a power semiconductor component of a first embodiment of the invention prior to packaging of the components in a plastic housing composition. The components are constructed in this embodiment of the invention on a Wärmelei¬ processing block 20, which is formed at the same time as Drainauße- nanschluss 19 and forms part of the underside 22 ^'of the power semiconductor device. This heat conduction block 20 is connected to the rear side 7 of the semiconductor chip 2 via a chip island 9. Thus, the semiconductor chip 2 via a rear side contact 8 on its back 7 and the chip island 9 and the heat conduction block 20 are electrically connected to the drain outer terminal 19.

On the upper side 3 of the semiconductor chip 2, a gate contact surface 6 is arranged, which is guided via a bond connection 26 to a gate external connection. This gate contact surface 6 is connected to a multiplicity of gate electrodes of the vertical power semiconductor component via printed conductors (not shown) on the upper side 3 of the semiconductor chip 2. Since the gate of such a power semiconductor component is potential-controlled, the switching currents are relatively low, so that a single bond connection 26 can ensure the supply of the gate electrodes.

In contrast, the total current between source and drain to be switched via the source electrodes is substantially greater, so that a multiplicity of bond connections 14 is required in order to conduct the source-drain current. The few square-micron-sized source electrodes on the upper side 3 of the semiconductor chip 2 are connected in parallel through a metal plate 10 to a common upper-side electrode 30. In this embodiment, this metal plate 10 is larger in its planar extent than the active upper side 3 of the semiconductor chip 2. In principle, therefore, a top electrode 30 can be provided whose areal extent is independent of the planar extent of the upper side 3 of the semiconductor chip 2.

While the rear side 12 of the metal plate 10 is connected to the multiplicity of source electrodes, a plurality of bonding connections 36 are arranged on the upper side 11 of the metal plate 10, which pass into bonding connections 14 and supply the metal plate 10 formed as a top side electrode 30 with current. On the one hand, this metal plate 10 provides a uniform distribution of the current density from the discrete bonding connections 14 to the multiplicity of source electrodes, so that current peaks which could lead to thermal overheating are avoided. Thus, the metal plate 10 provides for a thermal and also for an electrical equal distribution of the energy flows into the semiconductor chip.

FIG. 2 shows a schematic cross section through the power semiconductor component 1 of the first embodiment of the invention according to FIG. 1. This cross section illustrates that the components shown in FIG. 1 are now packaged in a plastic housing composition 21. Furthermore, the construction of the power semiconductor device 1 according to the invention is shown in detail.

The heat conduction block 20 forms the drain outer terminal 19 and at the same time a part of the lower side 22 of the power semiconductor component 1. At the same level, a gate outer terminal 18 and a source outer terminal 15 are led out laterally from the semiconductor component 1, which are in turn connected to corresponding inner flat conductors 16. On the inner flat conductors 16, coatings 24 are arranged as contact pads 13, these coatings 24 consisting of a bondable material, preferably of a silver alloy. In the case of the gate outer terminal 18, the latter is connected via the inner flat conductor 16, the coating 24 and the bonding connection 26 to the gate contact surface 6 on the active upper side 3 of the semiconductor chip 2.

In the case of the outer external contact connection 15, the latter is connected via an inner flat conductor 16, a coating 24 and a contact terminal surface 13 via a plurality of bond connections. gene 14 connected to the metal plate 10, wherein this Metall¬ plate 10 has a multi-layer, not shown metal diffusion-inhibiting coating, which ensures that the Me¬ tallmaterial of the bond 14 is not embrittled by diffusion processes of the metal material of the metal plate 10. In addition, the multi-layer coating of the metal plate 10 promotes the bonding process. The metal plate 10 is connected to the plurality of source contact areas 5 on the upper side 3 of the semiconductor chip 2 via a substance-coherent connection 25. In addition, the rear side 7 of the semiconductor chip 2 is electrically connected via a coating 23 to the upper side 34 of the heat conduction block 20 and thus to the drain outer connection 19.

FIG. 3 shows a schematic, perspective view of components of a power semiconductor component of a second embodiment of the invention prior to packaging the components in a plastic housing composition. Components with the same functions as in the preceding figures are identified by the same reference numerals and are not discussed separately.

In this embodiment of the invention, the components form a vertical power semiconductor diode. The common top contact 30 in the form of a metal plate 10 forms the anode 27, which is composed on the upper side 3 of the semiconductor chip 2 of a plurality of anode electrodes. These anode electrodes of a few square microns in size are closed in parallel via the common top electrode 30 in the form of the metal plate 10, so that a plurality of

Bond connections 14 can lead the diode current. The bonding connections 14 are in electrical contact via bonding connections 36 with the metal plate 10. The cathode 28 of this The power semiconductor diode is formed by the rear side 7 of the semiconductor chip 2 and is electrically connected via a rear-side contact 8 to a chip island 9, which merges into a heat conduction block 20. The heat conduction block 20 is in turn connected to an outer flat conductor 17 as the cathode connection 37 and forms a counter electrode 29 to the upper side electrode 30.

FIG. 4 shows a schematic cross section through the vertical power semiconductor component 40 of the second embodiment of the invention according to FIG. 3. The plurality of anode electrodes 38 form contact surfaces 4 on the top side of the semiconductor chip 2 and become a common top side electrode 30 the metal plate 10 interconnected. For this purpose, the underside 12 of the metal plate 10 has a material-like connection 25 with the contact surfaces 4. This cohesive connection 25 may be a conductive adhesive or a eutectic solder connection or else a diffusion solder connection.

The metal plate 10 can be connected to the plurality of anode electrodes 38 as a common top electrode 30 via the integral connection 25. On the upper side 11 of the metal plate 10, a plurality of bonding connections 36 are arranged, which are connected via bonding wires 33 and corresponding contact pads 13 to an inner flat conductor 16, which merges into an outer flat conductor 17 and forms a second outer connection 32, which is connected to the Anode 27 of the vertical power semiconductor device 40 is connected. The heat conduction block 20 passes directly into a first Außen¬ connection 31, which is designed as Außenflachleiter 17 and has a bore 39, with which the cathode 28 of vertical power semiconductor diode, for example, with a Massepo¬ potential, can be connected.

FIGS. 5 to 8 show schematic, perspective views of the assembly of the components of a vertical one

Power semiconductor device according to the first embodiment of the invention.

FIG. 5 shows a schematic, perspective view of a heat conduction block 20 with chip island 9 and applied semiconductor chip 2. This semiconductor chip 2 is connected with its rear side 7 to the chip island 9 via a back side contact 8. On its upper side 3, the semiconductor chip 2 has a plurality of source electrodes which are a few square microns in size. Furthermore, the upper side 3 has a single gate contact surface 6, via which a multiplicity of gate electrodes can be reached on the upper side 3 of the semiconductor chip 2.

FIG. 6 shows a schematic, perspective view according to FIG. 5 after applying a material-locking material 35 to the active upper side 3 of the semiconductor chip 2. This material-locking material 35 is applied only to the region of the upper side 3 of the semiconductor chip 2, which is the source - Contact surfaces 5, as shown in Figure 2, auf¬ has. This cohesive material 35 may be a conductive adhesive or a solder material.

FIG. 7 shows a schematic, perspective view according to FIG. 6 after applying a metal plate 10 as upper side electrode 30 to the active upper side 3 of the semiconductor chip 2. The metal plate 10 almost completely covers the upper side 3 of the semiconductor chip 2 and leaves only in one Recess 41 access to the gate contact surface 6 to. The self-supporting metal plate 10 is larger than the upper side 3 of the semiconductor chip 2 and can thus accommodate a plurality of bonding connections.

FIG. 8 shows a schematic, perspective view according to FIG. 7 after application of bonding connections 36 to the metal plate 10 according to the first embodiment of the invention according to FIG. 1. Components having the same functions as in the preceding figures are identified by the same reference numerals and not discussed separately. A de¬ detailed description of Figure 8 is unnecessary, since this embodiment of the invention corresponds exactly to the representation of Figure 1.

Claims

claims

1. Vertical power semiconductor component with a semiconductor chip (2), which has a multiplicity of contact surfaces (4) of a common upper side electrode (30) distributed on the upper side (3) and an opposing electrode (29) on the rear side (7). with a first outer terminal (31) of the power semiconductor component (1), wherein the upper side (3) of the semiconductor chip (2) has a metal plate (10) whose lower side (12) is in contact with the contact surfaces (4) of the upper side electrode ( 30) is connected in a material-locking manner and wherein an upper side (11) of the metal plate (10) opposite the underside (12) has bonding connections (14) to contact connection surfaces (13) which are connected to at least one common second outer connection (13). 32) of the power semiconductor device (1) are electrically connected.

2. power semiconductor device according to claim 1, characterized in that the second outer terminal (32) has a comb-shaped Flach¬ conductor whose comb teeth inner flat conductor (16) with contact pads (13) for bonding (14) and whose comb back an outer flat conductor (17 ) as a second external connection (32).

3. power semiconductor device according to claim 1 or claim 2, characterized in that the planar extension of the metal plate (10) is greater than the areal extent of the semiconductor chip (2).

4. power semiconductor device according to any one of the preceding claims, characterized in that the first outer terminal (31) a cathode (28) of a semiconductor chip (2) with vertically structured power diode and the second outer terminal (32) an anode (27) of the semiconductor chip ( 2) with vertically structured power diode.

5. power semiconductor device according to one of the preceding claims, characterized in that the first outer terminal (31) has a Drainaußenanschluss (19) of a semiconductor chip (2) with vertically structured MOS elements and the second outer terminal (32) a Sourceaußenanschluss (15), which is electrically connected via a plurality of bonding connections (14) and via the metal plate (10) to a multiplicity of source contact areas (5) of the semiconductor chip (2) distributed on the upper side (3) of the semiconductor chip (2).

6. power semiconductor device according to one of the preceding claims, characterized in that the power semiconductor device (1) at least one wei¬ teren outer terminal than Gateaußenanschluss (18) auf¬ has, via at least one bonding connection (26) with a gate contact surface (6) on the top (3) of the semiconductor chip (2) is electrically connected.

7. Power semiconductor device according to one of the preceding claims, characterized in that the semiconductor chip (2) with its rear side (7) is arranged on a heat conduction block (20) which forms the first external connection (31) of the power semiconductor component (1).

8. power semiconductor device according to one of the preceding claims, characterized in that the semiconductor chip (2) on its back (7) has a solderable metallization, which allows a soldering on ei¬ ner chip island (9) of a circuit board or a Flachleiter¬ structure.

9. power semiconductor device according to one of the preceding claims, characterized in that between the metal plate (10) and the bonding connections (14) a metal diffusion-inhibiting multi-layer coating is arranged.

10. power semiconductor device according to one of the preceding claims, characterized in that the metal diffusion-inhibiting coating has a layer of titanium or of a Titanle¬ alloy as a lower layer.

11. Power semiconductor device according to one of the preceding claims, characterized in that the metal diffusion-inhibiting coating has as middle layer a layer of titanium, nickel, vanadium or alloys thereof.

12. power semiconductor device according to one of the preceding claims, characterized in that the metal diffusion-inhibiting coating as the top

Layer has a layer of gold, silver, aluminum, palladium or alloys thereof.

13. Electronic power semiconductor component according to one of the preceding claims, characterized in that the bond connections (14) have bonding wires (33) made of gold, aluminum, palladium or alloys thereof.

14. Power semiconductor component according to one of claims 2 to 13, characterized in that the contact pads (13) on Innenflachleiter (16) or on a wiring structure of a board having a coating (24) made of silver or a Silberle¬ government.

15. Power semiconductor device according to one of the preceding

Claims, characterized in that the cohesive connection (25) between the underside (12) of the metal plate (10) and the contact surfaces (4) has a conductive adhesive.

16. power semiconductor device according to one of the preceding claims, characterized in that the material connection (25) between the sub- Side (12) of the metal plate (10) and the contact surfaces (4) has a eutectic solder connection or a diffusion Lotverbindung.

17. Power semiconductor device according to one of the preceding claims, characterized in that the outer terminals (17) protrude laterally from a Kunststoffgehäusemas- se (21) at the level of the underside (22) of the power semiconductor device (1).

18. Power semiconductor device according to one of the preceding claims, characterized in that external connections (17) are arranged on the underside (22) and / or the edge sides of the power semiconductor component (1).

19. Power semiconductor device according to one of the preceding claims, characterized in that the structure and the structure of the Leistungshalbleiterbau¬ part (1) corresponds to a "COOL-MOS" - power semiconductor element.

20. A method for producing a power semiconductor component (1) from a plurality of component components, comprising the following method steps:

Producing a semiconductor chip (2), on its upper side (3) a plurality of contact surfaces

(4) has a common upper side electrode (30) auf¬ and whose rear side (7) has a Rückseitenkon¬ clock (8); Producing a leadframe or a board with a chip island (9), which is connected to a first external terminal (31), and with contact connection surfaces (13) for bond connections (14), which have at least one second external terminal

(32) communicate electrically; Fixing the semiconductor chip (2) with its Rück¬ page (7) on the chip island (9); Joining a metal plate (10) as a common upper side electrode (30) with the

A plurality of contact surfaces (4) on the upper side (3) of the semiconductor chip (2);

Producing a plurality of bond connections (14) between the upper side (11) of the metal plate (10) and contact connection surfaces (13) of the second outer connection (32);

Packaging the component components in a Kunst¬ stoffgehäusemasse (34) leaving the Außen¬ connections (17).

21. The method according to claim 20, characterized in that the metal plate (10) is selectively coated with a multi-layer metal-diffusion-inhibiting coating for bonding with the following steps: cleaning the top (11) of the metal plate (10) by back sputtering or dry etching; selectively applying a first lower layer of titanium or a titanium alloy as a primer to the metal plate (10); selectively applying a second middle layer of nickel, vanadium, or alloys thereof as a metal diffusion-inhibiting layer on the Haftver¬ mittlage; selectively applying a third top layer of gold, silver, aluminum, palladium or alloys thereof as adhesion promoters or metal connectors to respective bond wires (33).

22. The method according to claim 20 or claim 21, characterized in that the selective application of the layers takes place by means of photolithography technique.

23. The method according to claim 20 or claim 21, characterized in that the selective application of the layers takes place by means of printing technology.

24. The method according to claim 20 or claim 21, characterized in that the selective application of the layers by means of screen printing or stencil printing takes place.

25. The method according to any one of claims 20 to 24, characterized in that the contact pads (13) before applying a semiconductor chip (2) are coated with a gold and / or Alu¬ miniumlegierung.

26. The method according to any one of claims 20 to 25, characterized in that prior to packaging to power semiconductor components (1) on the back of the chip island (9) a heat conduction block (20) is applied, which also serves as a first external connection (31).