DE102007036841B4 - Semiconductor device with semiconductor chip and method for its production - Google Patents

Abstract

Semiconductor component comprising: - a semiconductor chip (3) having at least a first contact (5) and a second contact (7) on its upper side (8), wherein the semiconductor chip (3) has a rear side (9) on which a third contact ( 6), external contact elements (14 to 18, 30 to 33), a structural element (25) comprising connecting elements (24) which are arranged together on an insulating base part (23) of the structural element (25) and which comprise the first Contact (5) and the second contact (7) of the top (8) of the semiconductor chip (3) with the external contacts (30 to 33) connect, wherein the structural element (25) has a thermal expansion coefficient of less than 10 ppm / K, and wherein the structural element (25) has a step (34), wherein the step height (h) is adapted to the thickness (D) of the semiconductor chip (3).

Description

Background of the Invention

The invention relates to a semiconductor device with a semiconductor chip and a method for its production.

A semiconductor chip is typically provided as a component of a semiconductor device having external contact surfaces and a housing. The semiconductor chip is arranged inside the housing, so that the housing protects the semiconductor chip.

The external contact surfaces of the semiconductor device enable functional access to the semiconductor chip outside the housing. Consequently, the semiconductor device has an electrically conductive redistribution, which is arranged within the housing and electrically connects the contact surface on the semiconductor chip with the external contact surfaces of the semiconductor device.

The semiconductor device also typically includes a circuit carrier that provides the external contact surface and on which the semiconductor chip is mounted. The circuit carrier may be a leadframe or a wiring substrate. The contact surfaces of the semiconductor chip are electrically connected via inner connecting elements with inner contact surfaces of the circuit carrier. These inner connecting elements can be bonding wires or flip-chip contacts in the form of solder balls. The circuit carrier and the inner connecting elements provide the inner rewiring of the semiconductor device.

From the DE 10 2004 031 592 A1 an electronic module assembly with two substrates is known, between which a chip and spacer elements are arranged.

The US 5 139 972 A discloses semiconductor devices having "tub-shaped" metallic package elements in which a semiconductor chip is disposed. A similar arrangement is also from the US 4 646 129 A known.

The US 2007/0 096 274 A1 and the US 5 578 869 A disclose Verbindungselelemente with a structured substrate, connect the contact surfaces on the top of a semiconductor chip with external contacts.

Summary of the invention

An embodiment of the invention comprises a semiconductor device with a semiconductor chip. The semiconductor chip has at least a first contact and a second contact on its top side. Furthermore, the semiconductor chip has a rear side, on which a third contact is arranged. The semiconductor device also has external contacts. The semiconductor device has a structural element with connecting elements, wherein the connecting elements are arranged jointly on an insulating base part of the structural element and connect the first contact and the second contact of the top side of the semiconductor chip to the external contacts. The structural element has a thermal expansion coefficient of less than 10 ppm / K and a step, wherein the step height is adapted to the thickness of the semiconductor chip.

The invention will now be explained in more detail with reference to the attached figures.

list of figures

• 1 shows a schematic perspective view of a semiconductor device according to an embodiment of the invention;
• 2 to 7 show schematic views of components for producing a semiconductor device according to 1 ;
• 2 shows a schematic perspective view of a semiconductor device position of a lead frame;
• 3 shows a schematic perspective view of the semiconductor device position after application of a semiconductor chip;
• 4 shows a schematic side view of a connecting bracket;
• 5 shows a schematic bottom view of the connecting bracket of 4 ;
• 6 shows a schematic perspective view of the connecting bracket according to 4 ;
• 7 shows a schematic perspective view of the semiconductor device position after applying the connecting bracket according to 6 ,

1 shows a schematic perspective view of a semiconductor device 1 according to an embodiment of the invention. In this perspective view, the housing has been omitted to the components of the semiconductor device 1 to show. The semiconductor device 1 is on flat flat conductors 11 . 12 and 13 built up. For this purpose, the flat conductor 12 a contact pad 10 on its top 45 on, in their areal extension of a power electrode 6 on the back side 9 a semiconductor chip 3 equivalent. In addition, the flat conductor has 12 the external contacts 14 . 15 . 16 . 17 and 18 on top of that on the bottom 36 of the semiconductor device 1 are freely accessible and in addition to the here Not shown edge sides of the semiconductor device 1 can be contacted.

Another flat conductor 11 also has a large contact pad 29 for connection to a power electrode 5 on, with the external contacts 31 . 32 and 33 both from the bottom 36 , as well as from an edge side of the semiconductor device 1 are accessible. The third flat conductor 13 is for connecting a control electrode 7 provided and has a contact pad 28 on. Also this flat conductor 13 has an external contact 30 that from both the bottom 36 , as well as from the edge side of the semiconductor device 1 is surface mountable to a parent circuit board. On the contact pad 10 of the flat conductor 12 is with his back 9 a semiconductor chip 3 arranged, with the back 9 a power electrode 6 comprising, either via a conductive adhesive or via diffusion solder layers or via a simple solder layer or via a low-temperature connection in particular via sintering processes of nanoparticles with the flat conductor 12 electrically connected.

On the top 8th has the semiconductor chip 3 a large power electrode 5 and a control electrode 7 on. Both electrodes 5 and 7 stand with a textured coating 27 a thickness d of a structural element or a connecting bracket 25 , which is an insulating base part 23 electrically connected, wherein the structured coating 27 of the structural element four contact surfaces 19 . 20 . 21 and 22 has, via conductor tracks 26 the structured coating 27 are connected. The insulating base part 23 of the connection bracket 25 is self-supporting and dimensionally stable and has, for example, a step 34 on that with her obtuse angled paragraph 35 the height difference between the electrodes 5 and 7 the top 8th of the semiconductor chip 3 and the flat conductors 11 and 13 overcomes. For this purpose, the step height h corresponds to the thickness D of the semiconductor chip 3 ,

When applying a control voltage to the external contact 30 , is via the control electrode 7 the semiconductor chip 3 switched through, leaving a vertical current path 4 from the power electrode 5 on top of the semiconductor chip 3 to the power electrode 6 is formed, over which a current from the external contacts 31 to 33 of the flat conductor 11 to the external contacts 14 to 18 of the flat conductor 12 flows.

The structure of this semiconductor device 1 exists next to the flat conductors 11 . 12 and 13 only from two other components, namely the semiconductor chip 3 and the connection bracket or structural element 25 , which must be assembled during assembly of the semiconductor device 1. Single assemblies of bond wires, bonding tapes or other fasteners can be omitted, so that only two joining steps, namely the placement of the semiconductor chip 3 on the flat conductor 12 and the application of the connecting bracket 25 on the semiconductor chip 3 and on the flat conductors 11 and 13 , are to be carried out. This show in detail the following 2 to 7 ,

The semiconductor device thus has the structural element 25 on, on which at least a part of the inner redistribution of the first contact and the second contact is arranged. At least two different and electrically separate inner rewirings are on a structural element 25 intended. This has the advantage that at least two connections by the application of a single structural element 25 can be generated. The first contact and the second contact can be electrically connected in a method step with the external contacts of the semiconductor device. Compared with a serial bonding wire method, manufacturing is simplified.

The electrically conductive rewiring of the two contacts may be on one side of an electrically insulating structural element 25 be arranged. The connecting elements 24 can be provided in the form of contact surfaces and tracks. In one of the embodiments, the structural element is 25 integrally.

The structural element 25 may be made of a DCB (direct copper bonded) material. Such a DCB material has a one-sided or double-sided copper-coated ceramic plate which consists of aluminum oxide and / or aluminum nitride. In order to realize the connection elements, the DCB material has a structured copper layer with a thickness d in micrometers between 100 μm ≦ d ≦ 600 μm. This ceramic plate ensures that the structural element is potential-free and enables high electrical insulation. The structured copper coating in turn has the advantage that can be dispensed with gold or aluminum wire bonds for a power semiconductor device.

Further, the alumina-based DCB material has a thermal expansion coefficient of 7.1 ppm / K and, based on aluminum nitride, a thermal expansion coefficient of 4.1 ppm / K, so that with appropriate mixing of the ceramics of the DCB material, the thermal expansion coefficient of the structural element is matched to the thermal expansion coefficient of silicon can be. The structure of the copper layer on the structure element of DCB material is adapted to the structure of electrodes on the upper side of a power semiconductor chip and thus has signal conductors for connecting a Gate electrode and power conductor tracks for connecting a power electrode. In addition, the upper side of such interconnects of the structured copper layer may have a refining coating of nickel and / or nickel / gold.

The on the bottom of the structural element 25 arranged contact surfaces can be compressed to a rewiring structure with contact surfaces, wherein at one end of the conductor tracks of the wiring structure contact surfaces are provided to the electrodes on the upper side of the semiconductor chip and on the other end of the conductor tracks contact surfaces are arranged to the flat conductors with external contacts.

In one embodiment, the structural element extends 25 between the top of the semiconductor chip and at least two external contacts. The external contacts can be electrically connected to each other, so that the access to a contact of the semiconductor chip via two external contacts is possible. This is advantageous in the case of power semiconductor components, since the load contacts carry high currents.

In a further embodiment, the structural element extends 25 between the top of the semiconductor chip and at least two separate external contacts. Separate external contacts are understood to mean external contacts which are not electrically connected to one another. The structural element extends between the outer contact of the first contact and the outer contact of the second contact and between the outer contacts and the semiconductor chip.

The structural element 25 has a thermal expansion coefficient of less than 10 ppm / K, preferably less than 6 ppm / K. The difference between the thermal expansion coefficients of the structural element and the semiconductor chip is reduced compared to a metallic structural element. This increases the reliability of the semiconductor device because the shearing voltages on the connection between the contact surfaces of the structure element and the contacts on the top side of the semiconductor chip are reduced.

Preferably, the structural element 25 a preformed base part made of plastic, which has insulating fillers and whose thermal expansion coefficient is adapted to the thermal expansion coefficient of the semiconductor material of the semiconductor chip. By means of this insulated base part, it is possible to arrange a multiplicity of contact surfaces and conductor tracks on the lower side of this base part in the form of a conductive structured coating, so that only a single joining step for the material connection of the contact surfaces with the electrodes of the upper side of the semiconductor chip or the contact connection surfaces of the External contacts is necessary.

In a further embodiment of the invention, the structural element 25 a preformed base part of sintered ceramic whose thermal expansion coefficient is adapted to the thermal expansion coefficient of the semiconductor material of the semiconductor chip. Even with such a base part made of ceramic material, a plurality of contact surfaces and conductor tracks may be arranged on the underside of the connection bracket in order to establish the connection to the top side of the semiconductor chip and to the corresponding external contacts of the semiconductor component in a single joining step. In both cases, the desired adaptation of the coefficient of thermal expansion of the base part to the thermal expansion coefficient of the semiconductor material of the semiconductor chip advantageously increases the reliability of the semiconductor component since shearing stresses on the material connection between contact surfaces of the structural element and the contacts on the upper side of the semiconductor chip are minimized.

The cross section of the conductor tracks is preferably adapted to the current density which flows via the contacts, in particular via power electrodes. In this case, an allowable current density and a permissible heating of the conductor tracks is not exceeded in order to avoid destruction of the conductor track connections. The cross section also depends on the specific resistance of the coating material used. The coating of the base part preferably comprises a metal or an alloy from the group Cu, Al, Ag, Au, Pd, Pt or Ni. These materials require different coating thicknesses and coating methods to conduct current between contacts on the top side of the semiconductor chip and the contact pads on the external contacts, especially if these metals and metal alloys tend to form oxide or sulfide layers during storage in air.

The external contacts preferably form surface-mountable, flat external contacts on the underside of the semiconductor component, while the top sides of the external contacts have contact connection surfaces which are connected in a material-locking manner to the connection bracket. In this case, the external contacts can be accessed both from the underside of the semiconductor component and from the edge sides of the semiconductor component.

To the structural element 25 only with a manufacturing step both with the contacts of the top of the semiconductor chip and with the To connect contact pads on the external contacts materially, the structural element has two Kontaktanschlussebenen, which are arranged on the one hand on the level of the contact pads of the external contacts and on the other hand in semiconductor chip height, for connection to top contacts of the semiconductor chip. The height difference between the contact terminal level of the external contacts and the top of the semiconductor chip is overcome by a step in the structural element. This step can have a right-angled or obtuse-angled shoulder, wherein the height of the shoulder is adapted to the thickness of the semiconductor chip.

In a further embodiment of the invention, the contacts of the upper side of the semiconductor chip and / or the contact surfaces of the structural element have coatings with diffusion solder components for forming intermetallic phases. If the semiconductor chip has a third contact on its rear side, the semiconductor device may have at least one diffusion solder layer between the third contact of the semiconductor chip and an associated chip carrier or lead with external contacts.

Such a diffusion solder bond has the advantage that the melting point of the diffusion solder material is lower than the melting point of the intermetallic phases forming in the diffusion soldering in the diffusion solder layer. Such intermetallic phases preferably belong to the group AuSn, AgSn, CuSn and / or AgIn.

In one embodiment, a semiconductor device is provided with a vertical semiconductor chip, such as a vertical transistor, wherein the structure element according to one of the above-described embodiments is provided in the form of a connection bracket and the external contacts in the form of a flat conductor. A third contact is arranged on the back side of the semiconductor chip.

The semiconductor chip has at least one vertical current path between power electrodes, which is switched by a control electrode. The control electrode and a first power electrode are arranged on the upper side of the semiconductor chip. A second power electrode covers the back side of the semiconductor chip. The semiconductor chip is arranged with the second power electrode on a contact pad of a single flat conductor having external contacts. The control electrode and the first power electrode are electrically connected via contact surfaces of separate flat conductor interconnect elements having inner contact pads and outer outer contacts. A common one-piece connection bracket having different contact surfaces electrically connects the electrodes of the top side of the semiconductor chip to the contact connection surfaces of the separate flat conductors.

This semiconductor device has the advantage that planar flat conductors can be used and that the number of connecting elements with their high risk of mounting is reduced to a single connecting element in the form of a connecting bar and yet a plurality of top electrodes of the semiconductor chip is reliably connected to corresponding flat conductors. The current conductivity is not limited by the cross section of bonding wires or bonding tapes and also not limited by the cross section of a connecting element, but rather can be optimized by an adaptable in their thickness of the current carrying capacity coating of the connecting bracket, wherein the electrically conductive coating from the top electrodes to the Flat conductors extends and increases the current conductivity of the dimensionally stable connection bracket due to high current conductivity.

In one embodiment of the invention, the connection bracket further contact surfaces for signal and / or supply electrodes of the top of the semiconductor chip, said signal and / or supply electrodes with monolithically integrated control or logic circuits of the semiconductor chip cooperate. Especially in this embodiment of the invention, the advantages of the one-piece connecting bracket are shown. The arranged on the underside of the connecting bracket contact surfaces can be compressed to a rewiring structure with contact surfaces, wherein at one end of the tracks of the wiring structure contact surfaces to the electrodes on the top of the semiconductor chip are present and disposed on the other end of the conductor pads contact surfaces to the flat conductors with external contacts are.

In a further embodiment of the invention, the electrodes of the upper side of the semiconductor chip and / or the contact surfaces of the connecting bracket have coatings with diffusion solder components for forming intermetallic phases. For this purpose, the semiconductor component has at least one diffusion solder layer between the second power electrode of the semiconductor chip and the associated flat conductor with external contacts.

Such a diffusion solder bond has the advantage that the melting point of the diffusion solder material is lower than the melting point of the intermetallic phases forming in the diffusion soldering in the diffusion solder layer. Such intermetallic phases preferably belong to the group AuSn, AgSn, CuSn and / or AgIn.

The control electrode is preferably an insulated gate electrode. Although the gate electrode is smaller in area than the power electrodes, it is still connected with the same coating as the power electrode to ensure the common contact pads both at the surface level of the semiconductor chip and at the top level of the leads. The power MOSFET in turn can have a monolithically integrated gate driver, which significantly increases the number of signal and supply electrodes on the top side of the semiconductor chip and thus also the complexity of the connection bar.

In another embodiment of the invention, the first power electrode is an emitter electrode and the second power electrode is a collector electrode of a vertical insulated gate bipolar transistor (IGBT), and the control electrode is again an insulated gate electrode. This gate electrode may also be formed as a vertical Tenchgateelektrode. The individual components of the semiconductor component, such as semiconductor chip, flat conductor and connection bracket can be arranged in a cavity housing, wherein external contacts of the leads on the bottom and / or the edge sides of the semiconductor device are freely accessible. It is also possible for these components, a plastic housing, leaving free external contacts of the leads on the bottom and / or on the edge sides of the semiconductor device and / or leaving a top of the structural element 25 to provide on the top of the semiconductor device in a plastic housing composition.

In one embodiment, the semiconductor device has a chip carrier with an upper side and a rear side, wherein the semiconductor chip is arranged on the upper side of the chip carrier. The chip carrier can be provided as part of a leadframe. If the semiconductor device has a plastic housing, the rear side of the chip carrier can be freely accessible from the plastic housing compound. The back side of the chip carrier may form an external contact of the semiconductor device which lies in the same plane of the other external contacts.

2 to 7 show schematic views of components for producing a semiconductor device according to 1 ,

2 shows a schematic perspective view of a semiconductor device position 43 a lead frame 42 , In this semiconductor component position 43 are the flat conductors 11 . 12 and 13 spaced from each other and have on their tops 45 the contact pads 10 . 28 and 29 on, with the contact pads 10 and 29 are prepared for receiving large-area connections. At the same time are the flat conductors 11 . 12 and 13 with external contacts on the bottom 36 and the edge sides provided, wherein the flat conductor 12 the external contacts 14 to 18 and the flat conductor 11 the external contacts 31 to 33 and the flat conductor 13 the external contact 30 exhibit.

3 shows a schematic perspective view of the semiconductor device position 43 after application of a semiconductor chip 3 with that on his back 9 arranged power electrode 6 on the contact pad 10 of the flat conductor 12 , The semiconductor chip 3 has a thickness D, so that the power electrode 5 and the control electrode 7 on the top 8th of the semiconductor chip and the associated contact pads 28 and 29 on the flat conductors 13 respectively. 11 via correspondingly bent connecting tracks with the higher electrodes 5 and 7 the top 8th of the semiconductor chip 3 to connect. Instead of several connecting elements show the 4 to 6 a single connection bracket 25 which allows the electrodes to be connected in a single joining step 5 and 7 the top 8th of the semiconductor chip with the contact pads 28 and 29 the flat conductor 11 and 13 connect to.

In addition shows 4 a schematic side view of a connecting bracket 25 , The connection bracket 25 consists of an insulating base part 23 , which consists of a filled plastic or a sintered ceramic and, for example, a step 34 having a step height h, which the in 3 shown height difference between the electrodes 5 and 7 the top 8th of the semiconductor chip 3 and the contact pads 28 and 29 the flat conductor 11 and 13 can overcome. In this embodiment of the connecting bracket 25 assigns the level 34 an obtuse-angled paragraph 35 on. On the bottom 44 of the base part 23 is a structured coating 27 arranged with a thickness d. The coating 27 has two tracks 26 on, at the ends of contact surfaces, for example 19 and 21 are arranged.

5 shows a schematic bottom view of the connection bracket 25 of the 4 , with two tracks 26 , where a narrow trace 26 the contact surfaces 19 and 21 for a control electrode connects together and a wider trace 26 the contact surfaces 20 and 22 connects, and where the tracks 26 through the base part 23 supported and held together.

6 shows a schematic perspective view of the connecting bracket 25 according to 4 so that the arrangement of the four contact surfaces 19 to 22 becomes visible. This connection bracket 25 will then be on the in 3 shown assembly in a semiconductor component position 43 applied.

7 shows a schematic perspective view of the semiconductor device position 43 after applying the connecting bracket 25 according to 6 so that the components of the semiconductor device are now fully assembled. This assembly takes place via a surface mounting of the connecting bracket 25 on the semiconductor chip 3 and on the flat conductors 11 and 13 in a single joining step, wherein for joining a conductive adhesive or a solder material can be used. With the dash-dotted line 46 Be the outlines of a plastic housing 40 from a plastic housing compound 41 shown in which the components of the semiconductor device 1 by releasing the external contacts 14 to 18 and 30 to 33 on the bottom 36 and the edge sides 38 and 39 of the semiconductor device 1 be embedded. This covers the top 37 of the semiconductor device 1 the top 47 the base part of the connecting bracket 25 from.

The method for producing a component accordingly has the following method steps. First, at least one semiconductor chip having at least a first contact and a second contact on an upper side and a third contact on its rear side as well as external contacts and a structural element which has connecting elements and a self-supporting, insulating base part are provided. The structural element is applied to the semiconductor chip and to the external contacts and thereby the first contact and the second contact is connected to the external contacts.

In detail, the structure element is produced by first producing a self-supporting insulating base part which has, for example, a filled plastic or a sintered ceramic, and which is subsequently provided on its underside with an electrically conductive coating. The thickness of this coating is adapted to the current load of the semiconductor device and then structured to contact surfaces with interconnects arranged therebetween.

For this purpose, metals of the group Cu, Al, Ag, Au, Pd, Pt or Ni can be deposited chemically or galvanically on a lower side of the base part for the coating. The structuring can then take place after application of a structured protective layer by means of screen printing, stencil printing or jet printing by subsequent etching of the unprotected metal coating.

In order to produce a structural element made of sintered ceramic material, a green body is first shaped and then fired to form an insulating sintered ceramic part. Care is taken here that the expansion coefficient of the base part is adapted to the thermal expansion coefficient of the semiconductor material of the semiconductor chip. When casting resin is used to make such a base, the casting resin is filled with particles having the coefficient of thermal expansion of the semiconductor material so that stresses due to shearing stresses are minimized.

The application of the structural element takes place simultaneously in two contact terminal planes, namely once between contact surfaces and the contacts of the upper side of the semiconductor chip and on the other between contact surfaces and the contact pads of the external contacts. In this case, the contact surfaces of the structural element can be surface-mounted by means of soldering or gluing. During the application of the structural element, a diffusion solder material may also be preliminarily applied to the contact surfaces of the structural element and then diffusion-soldered at the corresponding diffusion soldering temperatures under contact pressure of the connecting clip on the external contacts or the contacts of the upper side of the semiconductor chip.

For packaging the semiconductor chips with a structural element an injection molding technique or a Spritzpresstechnik is used, wherein the structural element and the semiconductor chip and tops of the flat conductors are embedded in a plastic housing composition and only the outer contacts on the lower sides and the edge sides of the semiconductor device of plastic material are kept free. On the other hand, it is also possible to introduce the components of such a semiconductor device after the application of the structural element in a cavity housing.

This can be carried out several times in each of the semiconductor component positions of a leadframe, wherein subsequently the leadframe is separated into individual semiconductor components by means of laser separation technology or an etching process or by means of sawing or punching technology. The leadframe frame provides the external contacts of the semiconductor device, which may be in the form of a chip carrier and / or a flat conductor. The underside of the leadframe frame provides the outer contact surface of the component, while the upper side of the leadframe frame provides the inner contact surface of the outer contacts.

In one embodiment, the method is used to fabricate a plurality of semiconductor components in a flat conductor technology with at least one vertical current path through a semiconductor chip. This method has the following Procedural steps on. First, a semiconductor chip having a first power electrode and a control electrode on the top side and a second power electrode on the back side of the semiconductor chip is produced. In parallel, a flat conductor frame with flat conductors can be produced which has inner contact pads and outer outer contacts in a plurality of semiconductor device positions. Also in parallel with this, it is possible to produce a structural element or a connecting bracket according to one of the above-described embodiments, which has different contact surfaces which are congruent with the electrodes of the upper side and with the contact connection areas of the separate flat conductors.

After these preparations of manufacturing the semiconductor chips, the lead frame and the connection bracket, individual semiconductor chips are fixed in the semiconductor device positions by integrally connecting the back sides of the semiconductor chips to a contact pad of a central lead of the lead frame. Subsequently, a cohesive connection of the connecting bracket to the electrodes of the upper side of the semiconductor chip and the contact pads on the separate flat conductors. Thereafter, the semiconductor chips are packaged with the connection bracket in a housing in the semiconductor device positions, and finally the leadframe is split into individual semiconductor devices.

1. 1. Durch das vorbereitend strukturierte Beschichten mit einem elektrisch leitenden Material auf der Unterseite des isolierenden Basisteils des Verbindungsbügels bzw. des Strukturelements wird ein „Clip“ geschaffen, der durch einen einzigen Oberflächenmontageschritt mehrere Oberflächenelektroden mit entsprechenden Kontaktflächen von Flachleitern verbinden kann.
2. 2. Durch das Verfahren wird eine bessere Prozesssicherheit erreicht, zumal im Vergleich zum Bonden die Verbindung über den Verbindungsbügel stabiler ist und ein derartiger Verbindungsbügel optimal positioniert werden kann.
3. 3. Ein weiterer Vorteil liegt in einer niedrigen Prozesstemperatur, wenn die Kontaktflächen des Verbindungsbügels mittels eines Leitklebers mit den entsprechenden Elektroden des Halbleiterchips bzw. den Kontaktanschlussflächen der Flachleiter verbunden werden.
4. 4. Die Verunreinigungsgefahr, wie sie beispielsweise bei Lotpasten auftreten kann, ist bei dem erfindungsgemäßen Verbindungsprozess insbesondere bei einer Diffusionslotverbindung vermindert.
5. 5. Ferner wird eine verbesserte Haftung zwischen dem Oberseitenkontakt und dem Verbindungsbügel über die elektrisch leitende strukturierte Beschichtung erreicht und die Zuverlässigkeit erhöht, wenn der thermische Ausdehnungskoeffizient des Verbindungsbügels an den thermischen Ausdehnungskoeffizienten des Halbleiterchips angepasst wird.
6. 6. Durch Strukturieren der elektrisch leitenden Beschichtung kann beispielsweise die Leitfähigkeit der Leiterbahnen der Beschichtung des Verbindungsbügels gezielt mit Hilfe der Abstimmung zwischen Länge und Breite der Leiterbahnen und entsprechender Dicke der Beschichtung an die Strombelastbarkeit angepasst werden. Auch eine Umverdrahtung für die oben erwähnten Elektroden kann geschaffen werden, so dass auf einen Drahtbondprozess bei einem Halbleiterbauteil vollständig verzichtet werden kann. Dazu kann der Halbleiterchip auf seiner Oberseite mit mehreren Signal- und Steuerelektroden sowie Leistungselektroden ausgestattet sein.

Such a method has the following advantages:

1. 1. The preparatively structured coating with an electrically conductive material on the underside of the insulating base part of the connection bracket or the structural element, a "clip" is created, which can connect a plurality of surface electrodes with corresponding contact surfaces of flat conductors by a single surface mounting step.
2. 2. By the method, a better process reliability is achieved, especially as compared to bonding the connection via the connection bracket is more stable and such a connection bracket can be optimally positioned.
3. 3. Another advantage lies in a low process temperature when the contact surfaces of the connection bracket are connected by means of a conductive adhesive with the corresponding electrodes of the semiconductor chip and the contact pads of the flat conductor.
4. 4. The risk of contamination, as may occur, for example, in the case of solder pastes, is reduced in the case of the bonding process according to the invention, in particular in the case of a diffusion solder bond.
5. 5. Furthermore, an improved adhesion between the top contact and the connection bracket via the electrically conductive structured coating is achieved and the reliability increased when the thermal expansion coefficient of the connection bracket is adapted to the thermal expansion coefficient of the semiconductor chip.
6. 6. By structuring the electrically conductive coating, for example, the conductivity of the conductor tracks of the coating of the connecting bracket can be specifically adapted to the current-carrying capacity by means of the coordination between the length and width of the conductor tracks and the corresponding thickness of the coating. It is also possible to create a rewiring for the abovementioned electrodes, so that a wire bonding process in the case of a semiconductor component can be completely dispensed with. For this purpose, the semiconductor chip may be equipped on its upper side with a plurality of signal and control electrodes and power electrodes.

For producing a leadframe with flat conductors having inner contact pads and outer outer contacts in a plurality of semiconductor device positions, a metal plate, preferably a flat copper plate, is patterned. This is possible by virtue of the fact that the electrodes of the upper side of the semiconductor chip can be connected to such flat conductors from a flat metal plate with the aid of the connection bracket. For structuring the planar metal plate, a punching process or a dry or wet etching process is preferably used. The structuring can also be done by laser ablation.

An alternative method for producing a leadframe is to deposit the lead structure galvanically or chemically on a subcarrier and then to remove the subcarrier.

The application of the semiconductor chip with its rear side onto a flat conductor in one of the semiconductor device positions of the leadframe can be effected by means of soldering or by gluing, wherein a conductive adhesive can be used for the electrical connection. On the other hand, it is also advantageous to apply to the second power electrode on the rear side of the semiconductor chip and to the contact pad of the associated flat conductor diffusion solder layers of a diffusion solder material having at least one of AuSn, AgSn, CuSn and / or InAg. Subsequently, at a Diffusionslöttemperatur T _D between 180 ° C ≤ T ≤ 450 ° C _D performed a diffusion soldering of the superimposed and pressed together layers.

As semiconductor chips MOSFETs are preferably used in which a vertical drift path and a lateral gate structure and a source electrode are arranged as a first power electrode on the upper side of the semiconductor chip, wherein the second electrode is formed by the drain electrode on the back side of the semiconductor chip, and the semiconductor chip with this Rear side is applied to a contact pad of a flat conductor. Instead of MOSFETs, IGBT semiconductor chips (insulated gate bipolar transistor), which likewise have a vertical drift path and a lateral gate structure and an emitter electrode as a first power electrode on the top, with a collector electrode on the back of the semiconductor chip on a contact pad of a Flat conductor are applied.

When manufacturing a connection bracket, contact surfaces are provided for connection to at least one power electrode and a control electrode in a contact surface plane of the connection bracket. In addition, contact surfaces for signal and / or supply electrodes of monolithically integrated control and logic circuits can be provided on this contact level of the connection bracket.

Claims (59)

Semiconductor component comprising: - a semiconductor chip (3) having at least a first contact (5) and a second contact (7) on its upper side (8), wherein the semiconductor chip (3) has a rear side (9) on which a third contact ( 6), external contact elements (14 to 18, 30 to 33), a structural element (25) comprising connecting elements (24) which are arranged together on an insulating base part (23) of the structural element (25) and which comprise the first Contact (5) and the second contact (7) of the top (8) of the semiconductor chip (3) with the external contacts (30 to 33) connect, wherein the structural element (25) has a thermal expansion coefficient of less than 10 ppm / K, and wherein the structural element (25) has a step (34), wherein the step height (h _s ) is adapted to the thickness (D) of the semiconductor chip (3). Semiconductor device after Claim 1 , wherein each connecting element has two contact surfaces (19, 21, 20, 22) and a conductor track (26). Semiconductor device after Claim 1 or Claim 2 , wherein the structural element is in one piece. Semiconductor component according to one of the preceding claims, wherein the structural element (25) comprises a DCB (direct copper bonded) material. Semiconductor device according to Claim 4 wherein the DCB material comprises an at least one sided copper coated alumina or aluminum nitride based ceramic plate. Semiconductor device according to Claim 4 or Claim 5 wherein the DCB material comprises a patterned copper layer having a thickness d in microns between 100 μm ≤ d ≤ 600 μm. Semiconductor component according to one of Claims 4 to 6 , wherein the coefficient of thermal expansion of the DCB material with 7.1 ppm / K for Al ₂ O ₃ and 4.1 ppm / K for AlN with a suitable mixture of the ceramics is adapted to the thermal expansion coefficient of silicon. Semiconductor device according to Claim 6 or Claim 7 wherein the structure of the copper layer is matched to the electrodes on the upper side of a power semiconductor chip and has a signal trace for connecting a gate electrode and a power semiconductor trace for connecting a power electrode. Semiconductor component according to one of Claims 6 to 8th wherein the top of the patterned copper layer comprises a nickel, palladium / gold, nickel / palladium / gold or nickel / gold coating. Semiconductor component according to one of Claims 1 to 3 in that the structural element (25) has a preformed base part (23) made of plastic, which has insulating fillers and whose coefficient of thermal expansion is adapted to the thermal expansion coefficients of the semiconductor material of the semiconductor chip (3). Semiconductor component according to one of Claims 1 to 3 in which the structural element (25) has a preformed base part (23) made of sintered ceramic whose thermal expansion coefficient is matched to the thermal expansion coefficient of the semiconductor material of the semiconductor chip (3). Semiconductor component according to one of the preceding claims, wherein the structural element (25) extends between the upper side (8) of the semiconductor chip (3) and at least two outer contacts (31 to 33). Semiconductor device after Claim 12 , wherein the structural element (25) extends between the upper side (8) of the semiconductor chip (3) and at least two separate external contacts (30 to 33). Semiconductor component according to one of the preceding claims, wherein the first contact (5) of the semiconductor chip (3) via a conductor track (26) of a Connecting element (24) with at least two external contacts (31 to 33) is electrically connected. Semiconductor component according to one of the preceding claims, wherein the structural element (25) conductor tracks (26) and contact surfaces (19 to 23), and wherein the cross-section of the conductor tracks (26) to the current density which flows through the contacts (5, 7), is adjusted. Semiconductor component according to one of the preceding claims, wherein the structural element (25) has a coating (27) structured to strip conductors (26) and contact surfaces (19 to 23) with a metal or an alloy of metals of the group Cu, Al, Ag, Au, Pd , Pt or Ni. Semiconductor component according to one of the preceding claims, wherein flat conductors (11, 12, 13) form the external contacts which form surface-mountable flat external contacts (19 to 18 and 30 to 33) of the semiconductor device. Semiconductor component according to one of the preceding claims, wherein the first contact (5) and the second contact (7) of the upper side (8) of the semiconductor chip (3) with the associated contact surfaces (19, 20) of the structural element (25) form a common Kontaktanschlussebene and are surface mountable. Semiconductor component according to one of the preceding claims, wherein the contacts (5, 7) of the upper side (8) of the semiconductor chip (3) and the contact surfaces (19, 20) of the structural element (25) have coatings (27) with diffusion solder components for forming intermetallic phases. Semiconductor component according to one of the preceding claims, wherein the structural element (25) has an obtuse-angled shoulder (35) and the height of the shoulder (h _S ) is adapted to the thickness (D) of the semiconductor chip (3). Semiconductor component according to one of the preceding claims, wherein the third contact (6) almost covers the rear side (9) as a single backside electrode. Semiconductor device after Claim 21 wherein the semiconductor device (1) has at least one diffusion solder layer between the third contact (6) of the semiconductor chip (3) and an associated chip carrier. Semiconductor device after Claim 22 , wherein the diffusion solder material has an intermetallic phase from the group AuSn, AgSn, CuSn or AgIn. Semiconductor component according to one of the preceding claims, wherein the first contact (5) is a first power electrode and the second contact (7) is a control electrode. Semiconductor device after Claim 24 wherein the first power electrode (5) is a source electrode and a second power electrode is a drain electrode of a vertical power MOSFET and the control electrode (7) is an insulated gate electrode. Semiconductor component according to one of the preceding claims, wherein the structural element (25) further contact surfaces for signal and / or supply electrodes of the upper side (8) of the semiconductor chip (3), which is provided with monolithically integrated control or logic circuits. Semiconductor device after Claim 25 or Claim 26 wherein the power MOSFET comprises a monolithically integrated gate driver. Semiconductor device after Claim 24 wherein the first contact (5) is an emitter electrode and the third contact (6) is a collector electrode of a vertical insulated gate bipolar transistor (IGBT) and the second contact (7) is an insulated gate electrode. Semiconductor component according to one of Claims 24 to 28 wherein the control electrode (7) of the semiconductor chip (3) has a vertical trench gate electrode. Semiconductor component according to one of the preceding claims, wherein the semiconductor component (1) comprises a cavity housing, in which the semiconductor chip (3), the structural element (25) and tops of the external contacts (10, 11, 12) are arranged, and wherein undersides (36) the external contacts (10, 11, 12) on the underside (36) and / or the edge sides (38, 39) of the semiconductor device (1) are freely accessible. Semiconductor component according to one of Claims 1 to 29 in which the semiconductor component (1) has a plastic housing (40) in whose plastic housing composition (41) the semiconductor chip (3), the structural element (25) and surfaces of the external contacts (11, 12, 13) are embedded, and undersides of the external contacts (14 to 18 and 30 to 33) of the flat conductor on the underside (36) of the semiconductor device (1) and / or an upper surface of the structural element (25) on the upper side of the semiconductor device (1) of plastic housing material (41) are kept free. Semiconductor component according to one of the preceding claims, wherein the semiconductor device has a chip carrier having an upper side and a rear side, wherein the semiconductor chip is arranged on the chip carrier. Semiconductor device after Claim 31 or Claim 32 , wherein the back of the chip carrier is freely accessible from the plastic housing composition. Semiconductor device after Claim 33 wherein the backside of the chip carrier forms an external contact of the semiconductor device. Method for producing a component, comprising the following method steps: Providing at least one semiconductor chip (3) with at least one first contact (5) and a second contact (7) on an upper side (8), the rear side (9) of the semiconductor chip (3) having a third contact (6), - Providing external contacts (14 to 18, 30 to 33); - Providing a structural element (25) having connecting elements (24) and a cantilevered insulating base part (23), and - Applying the structural element (25) on the semiconductor chip (3) and on the external contacts (14 to 18, 30 to 33) with connection of the first contact (5) and the second contact (7) with the external contacts (30 to 33) for the production of the structural element (25) first the self-supporting insulating base part (23) is produced, which is then provided on its underside (44) with an electrically conductive coating (27) whose thickness (d) to the current load of the semiconductor device (1) and is subsequently patterned into contact pads (19-22) with interconnects (26) therebetween, with a rectangular or obtuse step (34) imprinted into the cantilevered insulating base (23) prior to application of the coating (27) wherein the step height (h) is adapted to the thickness (D) of the semiconductor chip (3) and wherein the thermal expansion coefficient of the structural element (25) to the thermal Ausdehn ungskoeffizienten the semiconductor chip (3) is adjusted. Method according to Claim 35 in that the structural element (25) has different contact surfaces (19 to 22) which are congruent with the respective electrodes (5, 7) of the upper side (8) and with contact connection surfaces (28, 29) of the outer contacts (11, 13). Method according to Claim 35 or Claim 36 , wherein the structural element (25) with the contacts (5, 7) of the upper sides (8) and the contact pads (28, 29) on the separate outer contacts (11, 13) is materially connected. Method according to one of Claims 35 to 37 , wherein the first contact (5 ·) is electrically connected via a connecting element (24) with at least two external contacts (31 to 33). Method according to claim one of Claims 35 to 38 , wherein a flat conductor frame (42) with flat conductors (11, 12, 13) is provided for producing the external contacts, the inner contact connection surface (10, 28, 29) and outer external contacts (14 to 18 and 30 to 33) in a plurality of semiconductor device positions (43 ), and for producing the leadframe (42) with flat conductors (11, 12, 13), a metal plate, preferably a flat copper plate, is structured. Method according to Claim 39 , wherein for structuring the flat metal plate is punched. Method according to Claim 39 in which, for structuring, the flat metal plate is etched wet or dry. Method according to Claim 39 in which, for producing a leadframe (42), the leadframe structure is galvanically deposited on an auxiliary carrier and subsequently removed from the auxiliary carrier. Method according to one of Claims 39 to 42 , wherein for applying the semiconductor chip (3) with its rear side (9) to a flat conductor (12) in a semiconductor component position (43) of the leadframe (42) the semiconductor chip (3) is soldered or glued. Method according to one of Claims 39 to 43 in which diffusion solder layers of a diffusion solder material are applied to the third contact (6) of the semiconductor chips (3) and to the contact connection surface (10) of the associated flat conductor (12), comprising at least one of AuSn, AgSn, CuSn and / or InAg form intermetallic phases in a diffusion soldering whose melting points are higher than a diffusion soldering temperature. Method according to Claim 44 , wherein a diffusion soldering temperature T _D between 180 ° C ≤ T _D ≤ 450 ° C is used in the diffusion soldering. Method according to Claim 44 or Claim 45 in which the semiconductor chip (3) is a MOSFET having a vertical drift path and a lateral gate structure and a source electrode as the first power electrode (5) on the upper side (8) with its drain electrode on its rear side (9) onto a contact pad (10). a flat conductor (12) is applied. Method according to Claim 44 or Claim 45 wherein as semiconductor chip (3) an IGBT (insulated gate bipolar transistor type) having a vertical drift path and a lateral gate structure and an emitter electrode as the first power electrode (5) on the upper side (8), with its Collector electrode (7) is applied to a contact pad (10) of a flat conductor (12). Method according to Claim 46 or Claim 47 in that, when producing a structural element (25), contact surfaces (19, 20) are provided for connection to at least one power electrode (5) and a control electrode (7). Method according to one of Claims 46 to 48 in that, when producing a structural element (25), contact surfaces (19) for signal and / or supply electrodes of monolithically integrated control or logic circuits are provided. Method according to one of Claims 35 to 49 , wherein for the coating metals of the group Cu, Al, Ag, Au, Pd, Pt or Ni are chemically or galvanically deposited on the underside (44) of the base part (23) and wherein the structuring after application by means of screen printing, stencil printing or jet printing structured protective layer by subsequent etching of the unprotected metal coating takes place. Method according to one of Claims 35 to 50 in which, for producing the structural element (25), a green body of sintered ceramic material is formed and subsequently fired to form an insulating sintered ceramic part, the thermal expansion coefficient of which is adapted to the thermal expansion coefficient of the semiconductor material of the semiconductor chip (3). Method according to one of Claims 35 to 50 in which, for producing the structural element, a casting resin with filler is pressed or extruded into a casting mold to form an insulating base part (23). Method according to one of Claims 35 to 52 , wherein the structural element (25) with the contact surfaces (19 to 22) at the same time on the contacts (5, 7) of the upper side (8) of the semiconductor chip (3) and on the outer contacts (11, 13) is surface-mounted by means of soldering or gluing. Method according to one of Claims 35 to 53 , wherein on the contacts (5, 7) of the upper side (8) of the semiconductor chip (3) and on the contact pads (28, 29) of the external contacts (11, 13), and on the contact surfaces (19 to 22) of the structural element (25 ) Coatings (27) are applied with Diffusionslotkomponenten to form intermetallic phases and then at a diffusion brazing temperature T _D between 180 ° C ≤ T _D ≤ 450 ° C under contact pressure, the superposed coatings (27) are diffusion soldered. Method according to one of Claims 35 to 54 in which for packaging the semiconductor chips (3) with attached structural element in a plastic housing composition (41), leaving undersides of the external contacts (31 to 33) on the undersides (36) of the semiconductor components (1) and / or leaving an upper side of the structural element ( 25) on the top of the semiconductor device (1) an injection molding or injection molding technique can be used. Method according to one of Claims 35 to 55 in which, for producing a semiconductor component (1), a leadframe with a plurality of semiconductor device positions is used. Method according to Claim 56 in which a laser separation technique is used to separate the leadframe (42) into individual semiconductor components (1). Method according to Claim 56 in which an etching method is used for separating the leadframe (42) into individual semiconductor components (1). Method according to Claim 56 , wherein the separation of the leadframe (42) into individual semiconductor components by means of sawing or punching technology takes place.

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