WO2005122271A1 - Soi vertikales bipolares leistungsbauelement - Google Patents
Soi vertikales bipolares leistungsbauelement Download PDFInfo
- Publication number
- WO2005122271A1 WO2005122271A1 PCT/DE2005/001036 DE2005001036W WO2005122271A1 WO 2005122271 A1 WO2005122271 A1 WO 2005122271A1 DE 2005001036 W DE2005001036 W DE 2005001036W WO 2005122271 A1 WO2005122271 A1 WO 2005122271A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- soi
- strip
- doping
- side wall
- isolation trench
- Prior art date
Links
- 238000002955 isolation Methods 0.000 claims abstract description 33
- 239000002800 charge carrier Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 17
- 235000012431 wafers Nutrition 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 9
- 238000009413 insulation Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000001427 coherent effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Definitions
- the invention relates to a vertical SOI component which is suitable for power applications, for example an IGBT (insulated gate bipolar transistor) or power diodes, the SOI component having a vertical drift zone and an emitter configuration which is of a construction based on the (Silicon on Insulator ) SOI technology can be implemented with isolation trenches.
- IGBT insulated gate bipolar transistor
- the SOI component having a vertical drift zone and an emitter configuration which is of a construction based on the (Silicon on Insulator ) SOI technology can be implemented with isolation trenches.
- the IGBT offers significant advantages in terms of lower volume resistance compared to the unipolar DMOS transistor, especially in the higher voltage range from around 600 volts.
- compared to the unipolar vertical NDMOS transistor usually emits additional positive charge carriers from a specially designed back into the device.
- the highly doped rear emitter is produced at the end of the wafer processing process. So that will be
- the emitter is no longer arranged in volume but on the front side and can therefore be produced using the customary doping processes.
- the lateral arrangement of the transistor is disadvantageous in that a larger area on the SOI disk is required for a transistor of the same resistance than in a corresponding vertical arrangement.
- Vertical IGBTs usually have a homogeneous doping over the entire back.
- components are known in the prior art in which the rear side emitter is locally doped differently.
- a structure is known from US Pat. No. 6,259,123 in which the rear side structure is constructed from highly n-doped island regions which are arranged within a highly p-doped continuous region.
- a diode structure is known from B. Jayant Baliga, "Power Semiconductor Devices", PWS Publishing Company Bosten, 1995, page 180, in which the cathode as backside doping is alternately both n + and p + .
- the object is achieved by an SOI component with an isolation trench which defines a vertical drift zone, the component furthermore having a buried insulating layer to which the isolation trench extends.
- a charge carrier-emitting electrode region is also provided, which is formed adjacent to the insulating layer and is in contact with the drift zone, the electrode region having first strip-shaped regions with a first doping type and second strip-shaped regions with a second inverse doping type.
- a first side wall doping of the first doping type is provided, which is formed on a first side wall of the isolation trench, and a second side wall doping of the second doping type is provided, which is formed on a second side wall of the isolation trench, the first strip-shaped regions with the first side wall doping and the second strip-shaped regions are in contact with the second sidewall doping.
- an SOI component structure is thus shown in which a vertical drift zone with a differently doped buried emitter region is designed in such a way that integration into an SOI silicon wafer is possible without the essential interactions of the actual semiconductor manufacturing processes with the properties of the emitter affect, as previously explained in relation to the two known devices.
- the first and the second strip-shaped regions form a coherent area. In this way, further efficient utilization of the semiconductor area is achieved.
- first side wall and the second side wall face each other and are essentially parallel. In this way, at least for the side walls of the Isolation trench use a shape compatible with conventional isolation trench arrangements.
- two first and two second side walls are provided. This results in a substantially rectangular configuration for the buried emitter region, so that essentially existing designs for conventional SOI components with corresponding isolation trenches can be used.
- each of the first and second strip-shaped regions is in contact with the first and the second side wall, respectively. Because of this structure, a high area utilization of the buried electrode area can be achieved, because due to the special doping of the side walls, a suitable electrical connection is nevertheless achieved even with simultaneous contact by a first and a second area.
- the insulation structure has four side walls arranged essentially at right angles, and the first and second strip-shaped regions are arranged parallel to one another and parallel to a diagonal of a base area defined by the side walls.
- the component represents an IGBT. In a further embodiment, the component represents a diode.
- FIG. 1 is a sectional illustration of a known discrete IGBT structure, in which the rear side emitter is made up of n-doped island regions which lie within a highly p-doped region with a larger area fraction.
- FIG. 2 is an IGBT structure with an emitter divided into regularly alternating high-n-doped and high-p-doped regions;
- FIG. 3 is a contacting of an emitter lying in the volume of an SOI wafer, which has n + and p + regions according to FIG. 2, different doping being provided on opposite side walls of a relation trench according to the invention with regard to the conductivity type.
- FIG. 4 is a top view of the buried emitter region with the isolation trench according to section line A-A in FIG. 3.
- FIG. 1 shows an IGBT component which is implemented in an Si substrate 1 with low n-doping.
- a weakly p-doped well region 5 is provided in the substrate 1, in which a heavily n-doped source region and a heavily p-doped well contact region are formed.
- a gate insulation layer 3 is formed over the well region 5 and the substrate 1, which is followed by a gate electrode 4 made of polysilicon.
- a continuously formed p-doped rear-side emitter region 21 is provided on the rear side of the substrate 1, in which n + -doped island regions 22 are formed.
- FIG. 2 shows an IGBT component, which is likewise produced in a silicon substrate 1, which can be used for producing an SOI substrate according to the present invention, strip-shaped regions 31 and 32 with doping inverse to one another on the back of the substrate 1 correspondingly Form electrode area.
- FIG. 3 shows the structure of an SOI component according to the present invention, in which an electrode region composed of the strip-shaped regions 31 and 32 is arranged adjacent to a buried insulation layer 42.
- the insulation layer 42 is formed over a substrate 41, which can be provided in the form of a silicon substrate or the like.
- the component has an isolation trench 43 which defines a vertical drift region 46 which, for example, can correspond to a weakly doped silicon region in the substrate, for example the silicon substrate from FIGS. 1 and 2.
- Corresponding side wall dopings 44, 45 are formed on mutually facing but opposite side walls of the isolation trench 43, which differ in their doping type and thus represent an inverse conductivity type.
- the emitter structure ie the strip-shaped regions 31 and 32 being located in the wafer volume
- these are first introduced into the surface of a first low-n-doped silicon wafer in strips , as shown for example in FIG. 2 for the substrate 1.
- the substrate 41 with the insulation layer 42 produced thereon which is provided, for example, as an oxide layer, can be connected to the semiconductor wafer 1, which carries the emitter structures 31 and 32.
- the wafer composite is then thinned and polished to the required extent from the first silicon wafer 1.
- FIGS. 1 and 2 Corresponding structures for forming an IGBT, as is shown, for example, in FIGS. 1 and 2, i.e. the weakly p-doped well region 5, the heavily n-doped source region 6, the heavily p-doped well contact region 7, are also the gates - Insulation layer 3 and the guest polysilicon 4, as shown in FIGS. 1 and 2, produced.
- the electrical connection of the n + and p + strips 31 and 32 takes place through the differently doped side wall doping regions 44 and 45 of the isolation trench 43, as shown in FIG. 3.
- the emitter strips 31 and 32 are suitably designed diagonally and the isolation trenches are each provided with a side wall doping that is different on both sides of the trench in terms of the conduction type, a high area utilization can be achieved, the emitter strips 31 and 32 via the respective side wall doping regions 44 and 45 are electrically contacted from the surface of the component. In this way, the strips 31 and 32 are in each case contacted on one side with a corresponding side wall doping region 44 or 45 of the isolation trench 43, ie with an area of the same conductivity type.
- FIG. 4 shows a corresponding surface-optimized configuration with an essentially rectangular structure of the isolation trench 43 and a rectangular base area defined by the isolation trench, in which the strip-shaped regions 31 and 32 are arranged essentially parallel to a diagonal of this base area. If the strips 31 and 32 were guided from the top left to the bottom right with the same side wall doping as shown in the figure, half of the strips would not be connected.
- the SOI component shown in FIGS. 2 to 4 which in this embodiment represents an IGBT structure, can be implemented on SOI wafers due to the improved emitter design in smart power circuits. Due to the vertical alignment of the drift zone 46, a significantly smaller area requirement can be realized for a given component volume resistance.
- a power component that is capable of being integrated into SOI disks is described, in which a contiguous electrode region is provided adjacent to a vertical drift zone, which is composed of strip-shaped regions of different conduction types and which in the volume of the active semiconductor layer adjoins the insulating layer of the SOI -Arrangement is adjacent, these areas have an electrical connection to contacts on the surface.
- Isolation trench area of the same line type connects and meets the area of the opposite line type on the other side.
- This is advantageously an IGBT, the strip-shaped regions of the buried emitter being located diagonally to the rectangular or rectangular insulation trench and being contacted by the side wall doping regions with the corresponding mutual delimitations along the insulation trench.
- the line component is a diode.
- drift zone 46 drift zone 46 gate polysilicon 4
- Isolation layer 3 heavily p-doped well contact region 7 n-doped source region 6 stripe-shaped regions 31 and 32 isolation trenches 43
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05759586A EP1766687A1 (de) | 2004-06-11 | 2005-06-10 | Soi vertikales bipolares leistungsbauelement |
US11/629,022 US7989921B2 (en) | 2004-06-11 | 2005-06-10 | Soi vertical bipolar power component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004028474A DE102004028474B4 (de) | 2004-06-11 | 2004-06-11 | Integriertes Bauelement in einer SOI-Scheibe |
DE102004028474.1 | 2004-06-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005122271A1 true WO2005122271A1 (de) | 2005-12-22 |
Family
ID=34981646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2005/001036 WO2005122271A1 (de) | 2004-06-11 | 2005-06-10 | Soi vertikales bipolares leistungsbauelement |
Country Status (5)
Country | Link |
---|---|
US (1) | US7989921B2 (de) |
EP (1) | EP1766687A1 (de) |
CN (1) | CN101002329A (de) |
DE (1) | DE102004028474B4 (de) |
WO (1) | WO2005122271A1 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8759942B2 (en) * | 2009-05-22 | 2014-06-24 | X-Fab Semiconductor Foundries Ag | Semiconductor device comprising an isolation trench including semiconductor islands |
US8604513B2 (en) * | 2009-09-30 | 2013-12-10 | Denso Corporation | Semiconductor device having SOI substrate |
CN101719503B (zh) * | 2009-11-10 | 2012-07-04 | 上海宏力半导体制造有限公司 | 一种共电极薄soi纵向双极型晶体管器件及其制造方法 |
JP5605073B2 (ja) * | 2010-08-17 | 2014-10-15 | 株式会社デンソー | 半導体装置 |
CN103066104B (zh) * | 2012-12-28 | 2015-11-18 | 上海贝岭股份有限公司 | 具有终端保护结构的半导体功率器件 |
US9218958B2 (en) | 2013-12-10 | 2015-12-22 | Infineon Technologies Ag | Method for forming a semiconductor device |
US9570576B2 (en) * | 2013-12-10 | 2017-02-14 | Infineon Technologies Ag | Method for forming a semiconductor device having insulating parts or layers formed via anodic oxidation |
CN103681881A (zh) * | 2013-12-18 | 2014-03-26 | 无锡中微晶园电子有限公司 | 高可靠可堆叠高速soi二极管 |
CN105895632A (zh) * | 2014-09-05 | 2016-08-24 | 上海硅通半导体技术有限公司 | 一种晶圆结构及其制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0338312A2 (de) * | 1988-04-01 | 1989-10-25 | Hitachi, Ltd. | Bipolarer Transistor mit isolierter Steuerelektrode |
US5378920A (en) * | 1987-02-26 | 1995-01-03 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
EP0721211A2 (de) * | 1988-02-08 | 1996-07-10 | Kabushiki Kaisha Toshiba | Halbleiteranordnung und Verfahren zu ihrer Herstellung |
US6191456B1 (en) * | 1998-06-26 | 2001-02-20 | Siemens Aktiengesellschaft | Lateral IGBT in an SOI configuration and method for its fabrication |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5851857A (en) * | 1996-09-04 | 1998-12-22 | Ixys Corporation | High voltage power MOS device |
JP2005057235A (ja) * | 2003-07-24 | 2005-03-03 | Mitsubishi Electric Corp | 絶縁ゲート型バイポーラトランジスタ及びその製造方法、並びに、インバータ回路 |
US7364962B1 (en) * | 2004-02-02 | 2008-04-29 | Advanced Micro Devices, Inc. | Shallow trench isolation process utilizing differential liners |
-
2004
- 2004-06-11 DE DE102004028474A patent/DE102004028474B4/de not_active Expired - Fee Related
-
2005
- 2005-06-10 US US11/629,022 patent/US7989921B2/en active Active
- 2005-06-10 CN CNA2005800268989A patent/CN101002329A/zh active Pending
- 2005-06-10 EP EP05759586A patent/EP1766687A1/de not_active Withdrawn
- 2005-06-10 WO PCT/DE2005/001036 patent/WO2005122271A1/de active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5378920A (en) * | 1987-02-26 | 1995-01-03 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
EP0721211A2 (de) * | 1988-02-08 | 1996-07-10 | Kabushiki Kaisha Toshiba | Halbleiteranordnung und Verfahren zu ihrer Herstellung |
EP0338312A2 (de) * | 1988-04-01 | 1989-10-25 | Hitachi, Ltd. | Bipolarer Transistor mit isolierter Steuerelektrode |
US6191456B1 (en) * | 1998-06-26 | 2001-02-20 | Siemens Aktiengesellschaft | Lateral IGBT in an SOI configuration and method for its fabrication |
Also Published As
Publication number | Publication date |
---|---|
DE102004028474A1 (de) | 2006-01-05 |
CN101002329A (zh) | 2007-07-18 |
US7989921B2 (en) | 2011-08-02 |
US20080290366A1 (en) | 2008-11-27 |
EP1766687A1 (de) | 2007-03-28 |
DE102004028474B4 (de) | 2009-04-09 |
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