WO2005106929A1 - 半導体ウェハ及びその製造方法 - Google Patents
半導体ウェハ及びその製造方法 Download PDFInfo
- Publication number
- WO2005106929A1 WO2005106929A1 PCT/JP2004/006059 JP2004006059W WO2005106929A1 WO 2005106929 A1 WO2005106929 A1 WO 2005106929A1 JP 2004006059 W JP2004006059 W JP 2004006059W WO 2005106929 A1 WO2005106929 A1 WO 2005106929A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- film
- alignment mark
- semiconductor wafer
- alignment
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 40
- 238000000034 method Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 6
- 239000010408 film Substances 0.000 description 68
- 239000000758 substrate Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000012546 transfer Methods 0.000 description 2
- 241000652704 Balta Species 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
Definitions
- the present invention relates to a semiconductor wafer having a plurality of layers and a method for manufacturing the same.
- the semiconductor wafer refers to not only the semiconductor substrate itself but also a layer formed thereon. Background technology ''
- the alignment mark is formed in a scribe area which is a cutting margin for cutting a plurality of chips from a wafer.
- 4A to 4C are schematic views showing a reticle used in a conventional method of manufacturing a ferroelectric memory. In this method, alignment is performed many times.
- FIGS. 4A to 4C show reticles used in three alignments, as shown in FIGS. 4A, 4B, and 4C. , Area of alignment mark used when forming bulk layer 101 a, area of alignment mark used when forming capacitor layer 101 b, and area of alignment mark used when forming wiring layer 101c is formed in the scribe area 102 of the reticles 105a, 105b, and 105c, respectively.
- the scribe area 102 is divided into a light-shielded area 103 and an alignment data area 104.
- the light-shielding region 103 is provided to prevent the alignment marks from overlapping between two adjacent chips. Therefore, each area of the light-shielding region 103 and the alignment data region 104 is about 1.2 times smaller than that of the scribe region 102.
- the alignment mark areas 101 a, 101 b and 10 are arranged so as not to overlap each other in plan view when transferred to the semiconductor substrate. This is because a step due to the alignment mark formed in the lower layer becomes a pseudo edge when forming the alignment mark in the upper layer, and there is a possibility that an alignment failure occurs.
- the length of the alignment data area required for alignment is 6 mm, and the reticle shot size is 15 nim square, the length of the alignment data area is 7.5 mm. It is possible to place all the alignment marks. However, if the shot size of the reticle is 1 lmm square, not all alignment marks can be placed. If all the alignment marks cannot be arranged, the alignment marks may be incorrectly aligned.
- the shot size is 15 mm square and the alignment mark is arranged over the entire alignment data area of 7.5 mm, even if an attempt is made to add a wiring layer or the like after that, Since the alignment data area has already been filled, a new alignment mark cannot be allocated.
- Patent Document 1 discloses a method of switching whether or not to transfer an alignment mark formed on a reticle according to the position of a transfer destination. However, in this method, sufficient alignment cannot be performed because some alignment marks are not transferred to the side of the chip.
- Patent Document 1
- An object of the present invention is to provide a semiconductor wafer capable of performing alignment with sufficient accuracy even when the alignment data area is narrow, and a method for manufacturing the same.
- a second film covering the first alignment mark is formed.
- the second film is flattened.
- a light-shielding film that covers the first alignment mark from above is formed on the second film.
- a third film is formed on the light-shielding film.
- a second alignment mark overlapping the first alignment mark in plan view is formed on the third film.
- FIGS. 1A to 1C are schematic views showing a reticle used in the method for manufacturing a ferroelectric memory according to the embodiment of the present invention.
- FIGS. 2A to 2F are plan views showing a method for forming a wiring layer according to the embodiment of the present invention in the order of steps.
- 3A to 3F are cross-sectional views illustrating a method of forming a wiring layer according to an embodiment of the present invention in the order of steps.
- 4A to 4C are schematic views showing a reticle used in a conventional method of manufacturing a ferroelectric memory.
- FIG. 1A to 1C show a method for manufacturing a ferroelectric memory (semiconductor device) according to an embodiment of the present invention.
- FIG. 2 is a schematic view showing a reticle used in the first embodiment. In this manufacturing method, alignment is performed a large number of times.
- FIGS. 1A to 1C show a reticle ′ used in the alignment three times. As shown in FIG. 1A, FIG. 1B and FIG.
- a region 1a where an alignment mark used when forming a Balta layer is present and a region 1b where an alignment mark used when forming a capacitor layer is present
- areas lc where alignment marks used when forming wiring layers are present are formed in scribe areas 2 of reticles 5a, 5b and 5c, respectively. 3 and an alignment data area 4.
- the light-shielding region 3 is provided so that the alignment marks do not overlap between two adjacent chips. Therefore, the area of each of the light-shielding region 3 and the alignment data region 4 is about ⁇ of that of the scribe region 2 with respect to the deviation and deviation.
- the region 1 a and the region 1 b where the alignment mark exists are mutually seen in a plan view when transferred to a semiconductor wafer. They are arranged so that they do not overlap.
- the region 1b and the region 1c are arranged so as not to overlap with each other in plan view when transferred to the semiconductor substrate.
- the area la and the area lc are arranged so as to overlap each other in plan view when transferred to a semiconductor wafer.
- the film for transferring the alignment mark existing in the region 1a, 1b or 1c is planarized in advance. Then, the alignment using the alignment mark transferred to the film is performed, and after the alignment using the alignment mark is not performed in the subsequent steps, a light-shielding film covering the alignment mark is formed.
- FIGS. 3A to 3F are diagrams of a wiring layer according to an embodiment of the present invention. It is sectional drawing which shows the formation method in order of a process. 3A to 3F show cross sections taken along line II in FIGS. 2A to 2F, respectively. FIGS. 2A to 2F and FIGS. 3A to 3F show scribe areas of the wafer.
- an insulating film 11 is formed on the entire surface, and is planarized.
- wiring plugs (not shown) and the like are formed on the insulating film 11 ⁇ .
- an insulating film 12 such as a silicon oxide film is formed on the insulating film 11, and the flattening is performed.
- a hole for a plug and a hole for an alignment mark are formed in the insulating film 12.
- the reticle for example, a reticle having the same alignment mark area as the reticle 5a shown in FIG. 1A is used.
- an insulating film 15 such as a silicon oxide film is formed on the insulating film 12, and the insulating film 15 is planarized.
- a hole for a plug and a hole for an alignment mark are formed in the insulating film 15 by performing pattern jungling using a reticle.
- the reticle for example, a reticle having an alignment mark area similar to the reticle 5b shown in FIG. 1B is used.
- a contact plug (not shown) is formed in the plug hole, and the conductive film 16 is formed as a third alignment mark in the alignment hole.
- the conductive film 16 is formed at a position separated from the conductive film 13.
- a wiring layer (not shown) is formed by forming a conductive film such as an A1 film on the entire surface and performing patterning thereof.
- the conductive film 17 is left near the conductive film 16. In this state, by observing the positional relationship between the conductive film 17 and the conductive film 16, it is possible to understand how much displacement has occurred, and what kind of correction should be performed in the subsequent steps. Can be grasped.
- the conductive film 18 that indirectly covers the conductive films 13 and 14 is left as a light shielding film.
- an insulating film 19 such as a silicon oxide film is formed on the insulating film 15 and is planarized.
- a hole for a plug and a hole for an alignment mark are formed in the insulating film 19 by performing pattern jungling using a reticle.
- a reticle for example, a reticle having an alignment mark area similar to the reticle 5c shown in FIG. 1C is used.
- a contact plug (not shown) is formed in the hole for the plug, and the conductive film 20 is formed as a second alignment mark in the hole for the alignment.
- the conductive film 20 is formed at a position overlapping with the conductive film 13 in plan view.
- a conductive film such as an AI film is formed on the entire surface, and the patterning is performed to form wiring (not shown) and to form a conductive film.
- the conductive film 21 is left near 20.
- the conductive films 13 and 14 exist below the conductive films 20 and 21, but the conductive film 18 intervenes as a light-shielding film between them.
- poor alignment will not occur because of the 14 and 14.
- a desired number of wiring layers are formed while overlapping the alignment marks in plan view while forming the light-shielding film.
- a cover film or the like is formed to complete the semiconductor device.
- the light-shielding film covering the used and unnecessary alignment marks is formed on the flattened film, two or more alignment marks are seen in a plan view. Even if they overlap, it is possible to avoid the occurrence of alignment failure. Therefore, even when the alignment data area is narrow, an alignment mark can be always formed, and high alignment accuracy can be obtained.
- the limit on the number of alignment marks is relaxed, even if the number of wiring layers is to be increased, the alignment data area and the scribe area do not need to be expanded, and the number of alignment marks can be reduced from one. A large number of chips that can be manufactured can be maintained.
- the material of the light-shielding film is not limited to a conductor, and an insulator or a semiconductor may be used as long as it can shield light.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/006059 WO2005106929A1 (ja) | 2004-04-27 | 2004-04-27 | 半導体ウェハ及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/006059 WO2005106929A1 (ja) | 2004-04-27 | 2004-04-27 | 半導体ウェハ及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005106929A1 true WO2005106929A1 (ja) | 2005-11-10 |
Family
ID=35241920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/006059 WO2005106929A1 (ja) | 2004-04-27 | 2004-04-27 | 半導体ウェハ及びその製造方法 |
Country Status (1)
Country | Link |
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WO (1) | WO2005106929A1 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09232207A (ja) * | 1996-02-23 | 1997-09-05 | Fujitsu Ltd | アライメント・マークの形成方法 |
JP2001358048A (ja) * | 2000-06-13 | 2001-12-26 | Nec Corp | 半導体装置及びその製造方法 |
JP2002107906A (ja) * | 2000-09-29 | 2002-04-10 | Fujitsu Ltd | スクライブ内パターンデータ作成装置、及びスクライブ内パターンデータ作成方法 |
-
2004
- 2004-04-27 WO PCT/JP2004/006059 patent/WO2005106929A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09232207A (ja) * | 1996-02-23 | 1997-09-05 | Fujitsu Ltd | アライメント・マークの形成方法 |
JP2001358048A (ja) * | 2000-06-13 | 2001-12-26 | Nec Corp | 半導体装置及びその製造方法 |
JP2002107906A (ja) * | 2000-09-29 | 2002-04-10 | Fujitsu Ltd | スクライブ内パターンデータ作成装置、及びスクライブ内パターンデータ作成方法 |
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