WO2005093956A1 - Pll回路 - Google Patents
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- WO2005093956A1 WO2005093956A1 PCT/JP2005/005746 JP2005005746W WO2005093956A1 WO 2005093956 A1 WO2005093956 A1 WO 2005093956A1 JP 2005005746 W JP2005005746 W JP 2005005746W WO 2005093956 A1 WO2005093956 A1 WO 2005093956A1
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- 230000008859 change Effects 0.000 claims description 114
- 238000000034 method Methods 0.000 claims description 61
- 230000010355 oscillation Effects 0.000 claims description 45
- 230000008569 process Effects 0.000 claims description 31
- 238000004891 communication Methods 0.000 claims description 14
- 238000010295 mobile communication Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 4
- 230000004075 alteration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 23
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 21
- 238000001514 detection method Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 8
- 230000007704 transition Effects 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 241000143252 Idaea infirmaria Species 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Definitions
- the present invention relates to a PLL (Phase Locked Loop) circuit.
- the mobile communication terminal device can execute transmission and reception of various types, that is, the mobile communication terminal device is a multi-mode communication terminal device. Have been required.
- a frequency synthesizer used in a mobile communication terminal device having a multi-band wireless function needs to be able to generate local signals in various frequency bands corresponding to multi-band radio.
- GSM Global System Mobile Communication
- DCS Digita: ellular System
- PCS Personal Communication Services
- 1900MHz band ⁇ Use 2GHz band ⁇
- MTS Universal Mobile Telecommunication System
- a small-scale circuit configuration in which an arithmetic circuit including a frequency divider and a mixer for multiplication is combined with two unit synthesizers generates signals in a plurality of frequency bands larger than the number of unit synthesizers.
- an arithmetic circuit including a frequency divider and a mixer for multiplication is combined with two unit synthesizers generates signals in a plurality of frequency bands larger than the number of unit synthesizers.
- the frequency variable range of each voltage controlled oscillator is narrow, but the total frequency range is wide. Furthermore, in this method, since the frequency variable range of each voltage-controlled oscillator is narrow, the modulation sensitivity of each voltage-controlled oscillator can be small, and the synthesizer can operate stably.
- FIG. 11 shows a quadruple circuit that is proposed in Patent Document 1 and has a PLL circuit power.
- 4 quadruples means that the frequency is converted to 4 times.
- one of a plurality of voltage controlled oscillators is automatically selected and a clock is generated.
- the quadrant circuit shown in FIG. 11 has a frequency-phase comparator 1, a charge pump 2, a loop filter 3, and a control voltage-oscillation frequency characteristic different from each other (frequency variable ranges differ from each other).
- a voltage controlled oscillator group 4 including four voltage controlled oscillators, a frequency divider 5, an N-channel MOS transistor NM5, a resistor R, and a selection circuit 6.
- the N-channel MOS transistor NM5 When the output signal S14 of the selection circuit 6 is at a high potential (H), the N-channel MOS transistor NM5 is turned on, and the control signal from the loop filter 3 is provided by the series connection circuit including the resistor R and this transistor NM5. The current of S4 is extracted. As a result, the line of the control signal S4 is The potential is set to a voltage within a range between threshold voltages Vrefl and Vref2 described later.
- Frequency phase comparator 1 generates output signals Sl and S2 based on the result of comparison between reference signal CK1 and internal signal CK2.
- the output signal S1 is a signal indicating the amount of advance of the phase of the reference signal CK1 with respect to the internal signal CK2
- the output signal S2 is the signal indicating the amount of advance of the phase of the internal signal CK2 with respect to the reference signal CK1.
- These output signals Sl and S2 are input to the charge pump 2.
- the output signal S3 of the charge pump 2 is input to the loop filter 3, from which high-frequency components are removed, and then input to the voltage-controlled oscillator group 4 as the control signal S4 of the voltage-controlled oscillator group 4.
- the selection signals S10 to S13 correspond to four voltage-controlled oscillators (VCO:
- This signal is used to select one voltage-controlled oscillator from the Voltage Controlled Oscillator, and is generated by the selection circuit 6.
- the output signal CK3 of the voltage-controlled oscillator group 4 is frequency-divided by the frequency divider 5 into an internal signal CK2.
- FIG. 12 shows a block diagram of the selection circuit 6.
- the output signal S14 becomes high potential (H) for a fixed time, and the potential of the control signal S4 is set between the threshold voltage Vrefl and Vref2 (Vrel2> Vrefl). Set the voltage within the range.
- the selection circuit 6 includes a voltage comparator 418 having a threshold voltage Vrefl and a voltage comparator 419 having a threshold voltage Vref2.
- the control signal S4 is input to these voltage comparators 418 and 419, and the voltage comparator 418 outputs an output signal S15, and the voltage comparator 419 outputs an output signal S16.
- the voltage comparator 418 sets the output signal S15 to a low potential (L) when the voltage of the input control signal S4 is lower than the threshold voltage Vrefl, and sets the output signal S15 to a high potential (H) when the voltage is high. Set.
- the voltage comparator 419 sets the output signal S16 to a low potential (L) when the voltage of the input control signal S4 is lower than the threshold voltage Vre! 2, and sets the high potential (H ).
- the selection circuit 6 includes a NOR gate 420 and an AND gate 421.
- the NOR gate 420 outputs an output signal S17 based on the output signals S15 and S16 input to the NOR gate 420. That is, when both the output signals S15 and S16 input to the NOR gate 420 are at the low potential (L), the NOR gate 420 outputs the high potential (H) output signal S17, and at other times, The low potential (L) output signal S17 is output.
- the AND gate 421 outputs an output signal S18 based on the output signals S15 and S16 input to the AND gate 421. That is, the AND gate 421 outputs the high potential (H) output signal S18 when both of the output signals S15 and S16 input to the AND gate 421 are at the high potential (H), and outputs the output signal S18 at other times. Outputs low potential (L) output signal S18.
- the selection circuit 6 includes a 2-bit up counter 422 that receives the output signal S17 and outputs the count value S19, and a 2-bit up counter 423 that receives the output signal S18 and outputs the count value S20.
- the count value S19 output from the bit-up counter 422 is also subtracted from the count value S20 output from the 2-bit-up counter 423, and the subtractor 424 outputs a subtraction result value S21, which is the result of the subtraction.
- a decoder 425 that receives the output of the subtraction result value S21 and outputs output signals S10, Sl1, S12, S13, and S14. The decoder 425 sets only one of the output signals S10 to S13 to a high potential (H) according to the subtraction result value S21 output from the subtractor 424.
- the selection circuit 6 operating in this manner automatically selects a desired one of the four voltage-controlled oscillators having different frequency variable ranges according to the frequency four times the frequency of the reference signal CK1. Will be selected.
- the output signal S14 temporarily goes to a high potential (H), and the potential of the control signal S4 is forcibly changed from the threshold voltage Vrefl shown in FIG. High and lower than Vref2, the output of NOR gate 420 and AND gate 421 Since the force once returns to the low potential (L), it is possible to prevent the wrong voltage-controlled oscillator from being selected from among the voltage-controlled oscillators 4 having different frequency variable ranges.
- FIG. 13 is a characteristic diagram showing oscillation frequency characteristics of the conventional voltage-controlled oscillator group 4 with respect to the voltage of the control signal S4.
- the frequencies fl to f8 have a relationship of fl ⁇ f2 ⁇ f3 ⁇ f4 ⁇ f5 ⁇ f6 ⁇ f7 ⁇ f8.
- the desired oscillation frequency that is, the frequency fosc, which is four times the frequency of the input reference signal CK1
- the frequency fosc which is four times the frequency of the input reference signal CK1
- the output signal S 14 temporarily becomes high potential (H), and the control signal S 4 temporarily returns to a voltage in the range between the threshold voltage Vrefl and the threshold voltage Vref 2.
- the output signal S 17 of the NOR gate 420 changes from the high potential (H) to the low potential (L).
- the voltage-controlled oscillator is in a state of outputting substantially the same frequency as the reference signal, but since the phase of the frequency divider 5 does not change in a short time, the frequency-phase comparator 1 is still It operates to set the frequency of the internal signal higher, and consequently the control voltage S4 is reset.
- the selection circuit 6 repeats the above-described operation, and transits to the characteristic A. This time, because the frequency of the voltage controlled oscillator is higher than the reference signal, the phase of the frequency divider 5 leads the reference signal, so that the control voltage S4 falls below the threshold voltage Vrefl, and the selection circuit 6 returns to the characteristic B again. Transition.
- Patent document 1 JP-A-9-214335
- phase is the integral of the frequency, even if the optimal voltage-controlled oscillator is selected and an internal signal having the same frequency as the reference signal is input to the phase comparator.
- the present invention has been made to solve the above-described problems, and a PLL circuit that can be set to any one of a plurality of mutually different frequency variable ranges. It is another object of the present invention to provide a PLL circuit capable of performing a setting operation to a frequency variable range corresponding to a target frequency in a short time.
- a PLL circuit of the present invention compares a phase of a reference signal with a phase of an internal signal and outputs a phase difference signal corresponding to the phase difference between the reference signal and the internal signal.
- a plurality of oscillators each having a variable wave number range and each of which has an oscillation frequency controlled based on the phase difference signal; and any one of the plurality of oscillators capable of outputting a signal having a desired oscillation frequency.
- a frequency divider for generating the internal signal by dividing the output of the oscillator selected by the selector. If the frequency of the variable frequency range of the currently selected oscillator is lower than the target frequency, the frequency of the variable frequency range of the oscillator matches the target frequency or the target frequency is changed.
- the frequency range of the oscillator to be selected is increased by several steps (however, if the frequency range can be increased by only one step, it is increased by one step). If the frequency of the selected oscillator's frequency variable range exceeds the target frequency by repeating the change of the oscillator, the oscillator's frequency variable range is reduced with a smaller change width than before the selected frequency is exceeded.
- the frequency in the variable frequency range of the oscillator matches the target frequency or Until the frequency falls below the frequency of the selected oscillator, the frequency range of the selected oscillator will be lowered by multiple steps (however, if the frequency range can be lowered by only one step, the frequency will be lowered by one step). If the frequency of the selected oscillator's frequency variable range falls below the target frequency, the oscillator's frequency variable range is changed with a smaller change width than before the fall. Kunar so on, Ru as a feature to change the oscillator to be selected.
- the PLL circuit of the present invention includes a phase comparator that compares the phase of a reference signal and an internal signal and outputs a phase difference signal according to the phase difference, and a plurality of resonance circuits having different resonance frequencies. And based on the phase difference signal! An oscillator whose oscillation frequency is controlled, and selecting one of the plurality of resonance circuits from the plurality of resonance circuits based on the phase difference signal. A selector for setting any one of the frequency variable ranges to one frequency variable range and enabling the oscillator to output a signal having a desired oscillation frequency; and dividing the output of the oscillator by dividing the internal signal.
- a frequency divider that generates a frequency of the oscillator, wherein the frequency of the current frequency variable range of the oscillator is lower than a target frequency.
- the frequency variable range of the oscillator is increased by a plurality of steps until the frequency of the frequency variable range matches the target frequency or exceeds the target frequency.
- the frequency variable range of the oscillator is changed with a smaller change width than before.
- the resonance circuit to be selected is changed so as to be lower, and when the frequency of the current frequency variable range of the oscillator is higher than the target frequency, the frequency of the current frequency variable range is set to the target frequency. Until the frequency coincides or falls below the target frequency, the frequency variable range of the oscillator is reduced by a plurality of steps (however,
- the frequency variable range can be lowered by only one step, the frequency is reduced by one step), and the change of the selected resonance circuit is repeated, and the frequency of the frequency variable range of the oscillator after the selection becomes the target frequency.
- the selected resonance circuit is changed so that the frequency variable range of the oscillator increases with a smaller variation width than before the drop.
- a PLL circuit of the present invention compares a phase of a reference signal with an internal signal and outputs a phase difference signal corresponding to the phase difference, and a phase comparator based on the phase difference signal.
- An oscillator configured by interconnecting a plurality of delay circuits, each having a controlled delay time, and the number of connected delay circuits of the oscillator are selected based on the phase difference signal.
- the frequency variable range of the oscillator is increased by a plurality of steps until the frequency of the frequency variable range matches the target frequency or exceeds the target frequency (however, the frequency variable range is increased).
- the frequency of the oscillator can be increased by only one step, the number of links to be selected is changed repeatedly. If the frequency in the frequency variable range of the oscillator after the selection exceeds the target frequency, The frequency variable range of the oscillator with a smaller variation width than before Is changed so that the frequency of the variable frequency range of the oscillator is higher than a target frequency, or the frequency of the variable frequency range matches the target frequency, or Until the frequency falls below the target frequency, the frequency range of the oscillator is reduced by a plurality of steps (however, if the frequency range can be reduced by only one step, the frequency range is reduced by one step). When the frequency of the frequency variable range of the oscillator after the selection is lower than the target frequency, the frequency variable range of the oscillator is increased with a smaller change width than before the frequency changes. Further, the number of links to be selected is changed.
- the frequency of the current frequency variable range is set to the target frequency. If the frequency is lower than N, the frequency variable range is increased by N steps (N is an integer of 2 or more). ) Change the selection state and if the current frequency variable range frequency is higher than the target frequency, the frequency variable range is reduced by N steps (N is an integer of 2 or more) (however, N steps If it cannot be lowered, it is preferable to change the selection so that only the stage closest to the N stage is lowered).
- the selector changes the selection state before the predetermined time has passed since the selection state was changed last time
- the frequency of the current frequency variable range is lower than the target frequency. Changes the selection state so that the frequency variable range is increased by the same number of steps as the previous time (however, if the number of steps cannot be increased by the same time as the previous time, it will be increased by the closest number of steps to the previous time). If the frequency exceeds the target frequency due to the previous change, the frequency variable range is half the number of steps from the previous time. (However, if half of the previously changed number of steps is not an integer, the decimal part is rounded down and rounded up.
- the frequency variable range will be half the number of previous steps (however, If half of the floor is not an integer, it is preferable to change the selection state so that the decimal point is higher by one of truncation, round-up, and round-off.
- the frequency of the current frequency variable range is set to the target frequency. If the number of steps in the frequency variable range that is higher than the current frequency variable range is N1, if N1 is lower than the frequency, then N1 is divided by an integer M that is 2 or more, and the frequency variable range is (N1ZM).
- N1ZM is an integer of 2 or more.
- N2 is divided by an integer M greater than or equal to 2 so that the frequency variable range becomes higher by (N2ZM) steps (however, if it does not become N2ZM, the fractional part is rounded down. , Rounding up or rounding down, and (N2ZM) step cannot be raised! / In the case, change the selection state so that it is the closest to (N2ZM) step!
- N2 is divided by an integer M of 2 or more, and the frequency variable range is lowered by (N2ZM) steps. (However, if it does not become N2ZM, the decimal point is rounded off. If it is not possible to lower the value by (N2ZM) step, it is possible to change the selection state so that it is the closest to (N2ZM) step! preferable.
- the frequency divider is reset.
- the selection state is forcibly held in a state in which the selection state is not changed for a certain time after the selection state is changed by the selector.
- a wireless device includes the PLL circuit according to the present invention.
- a wireless communication terminal device of the present invention includes the wireless device of the present invention.
- the wireless communication terminal device of the present invention is preferably a mobile phone or another mobile communication terminal device, for example.
- the method for setting the frequency variable range of the PLL circuit according to the present invention includes a phase comparator that compares the phases of a reference signal and an internal signal and outputs a phase difference signal according to the phase difference.
- a plurality of oscillators each having a different frequency variable range and having an oscillation frequency controlled based on the phase difference signal; and one of the plurality of oscillators capable of outputting a signal having a desired oscillation frequency.
- the frequency variable range of the selected oscillator should be increased by several steps (however, only one frequency variable range If it is not possible to increase the frequency, increase the selected oscillator by one step), repeat the process of changing the selected oscillator, and if the frequency of the frequency variable range of the selected oscillator exceeds the target frequency, The process of changing the selected oscillator is performed so that the oscillator's frequency variable range becomes smaller with a small change width, and if the frequency of the currently selected oscillator's frequency variable range is higher than the target frequency, Until the frequency of the variable frequency range of the oscillator matches the target frequency or falls below the target frequency, the frequency variable range of the selected (However, if the frequency variable range cannot be reduced by one step, it
- the method of setting the frequency variable range of the PLL circuit according to the present invention includes a phase comparator that compares the phase of a reference signal and an internal signal and outputs a phase difference signal according to the phase difference, and a resonance circuit having a different resonance frequency.
- the frequency variable range of the oscillator is set to one of a plurality of different frequency variable ranges, and a signal of a desired oscillation frequency is output from the oscillator.
- frequency In the method of setting the variable range, if the frequency of the current frequency variable range of the oscillator is lower than the target frequency, the frequency of the frequency variable range matches the target frequency or the target frequency. Until the frequency exceeds, the selected resonance frequency is increased so that the frequency variable range of the oscillator is increased by a plurality of steps (however, if the frequency variable range can be increased by only one step, it is increased by one step).
- the frequency variable range of the oscillator after the selection exceeds the target frequency
- the frequency variable range of the oscillator is reduced with a smaller change width than before the frequency is changed.
- the process of changing the selected resonance circuit is performed, and if the current frequency variable range of the oscillator is higher than the target frequency, the frequency of the current frequency variable range is changed. Until the frequency matches the target frequency or falls below the target frequency, the frequency variable range of the oscillator is reduced by a plurality of steps (however, if the frequency variable range can be reduced only one step, only one step In such a case, when the frequency of the selected oscillator falls below the target frequency, the change width is smaller than before the selected frequency is changed. Performing a process of changing the selected resonance circuit so that the frequency variable range of the oscillator is increased. It is characterized by.
- the method of setting the frequency variable range of the PLL circuit according to the present invention includes a phase comparator that compares the phases of a reference signal and an internal signal and outputs a phase difference signal according to the phase difference.
- An oscillator configured by interconnecting a plurality of delay circuits, each of which has a delay time controlled based on the phase difference signal, and the number of connected delay circuits of the oscillator based on the phase difference signal.
- a frequency divider that generates the internal signal by dividing the output of the oscillator, and changes the selection state of the number of the delay circuits connected by the selector of the PLL circuit. Setting If the frequency of the current variable frequency range of the oscillator is lower than the target frequency, the frequency of the variable frequency range is equal to or higher than the target frequency. In order to increase the frequency variable range of the oscillator by a plurality of stages (however, if the frequency variable range can be increased by only one step, the frequency variable range is increased by one step), the process of repeating the change of the number of couplings to be selected is repeated.
- the connection is selected so that the frequency variable range of the oscillator is smaller than before the frequency exceeds the target frequency and the variation width is lower. If the frequency of the oscillator is higher than the target frequency, the frequency of the variable frequency range matches the target frequency. Until the frequency falls below the target frequency, the frequency variable range of the oscillator is reduced by a plurality of steps (however, the frequency variable range can be reduced by only one step, in which case, the frequency variable range is reduced by one step.
- the method is characterized in that a process of changing the number of links to be selected is performed so as to increase the range.
- the selector when the selector changes the selection state after a predetermined time has passed since the last time the selection state was changed, the selector changes the current frequency variable range. If the frequency range is lower than the target frequency, Change the selection state so that the change range is increased by N steps (N is an integer of 2 or more) (however, if it cannot be increased by N steps, it is increased by the step closest to N steps), and the current state is changed. If the frequency in the variable frequency range is higher than the target frequency, the frequency variable range is reduced by N steps (N is an integer of 2 or more). It is preferable to change the selection state (most recently, lower by stages).
- the frequency variable range is higher than the target frequency, and the frequency variable range has the same number of steps as the previous time. (If the number of steps cannot be lowered the same as the previous time, change the selected state so that the number of steps is the same as the previous time and the nearest V, and lower by the number of steps.) If the frequency variable range is less than the previous half, the frequency variable range is half the number of previous steps. (However, if the half of the previously changed number of steps is not an integer, the fractional part is rounded down, rounded up or rounded off. It is preferable to change the selection state so that it only becomes higher.
- the selector when the selector changes the selected state after a predetermined time has passed since the last time the selected state was changed, If the frequency of the frequency variable range is lower than the target frequency, and the number of steps in the frequency variable range that is higher than the current frequency variable range is N1, divide N1 by an integer M that is 2 or more, and To make the variable range higher by (N1ZM) steps (However, if (N1ZM) is not an integer, round down, round up, or round off to 4 decimal places, and cannot raise (N1ZM) steps If the frequency of the current frequency variable range is higher than the target frequency, change the selection state (so that it is closest to the (N1ZM) Lower than Assuming that the number of steps in the frequency variable range is Nl, N1 is divided by an integer M of 2 or more, so that the frequency variable range becomes lower by (N1ZM) steps (however, if (N1ZM) is not an integer
- N2 is divided by an integer M equal to or greater than 2 so that the frequency variable range becomes higher by (N2ZM) steps (however, if N2ZM is not an integer, the decimal point The following can be rounded down, rounded up or rounded down, and cannot be raised by (N2 / M) steps! / In such a case, it is the closest to (N2ZM) steps!
- the number of steps changed last time is assumed to be N2, and N2 is divided by an integer M of 2 or more, and the frequency variable range is changed. Is reduced by (N2ZM) steps (however, if it does not become N2ZM, Either round down, round up, or round off and round (N2ZM) step cannot be lowered! / In some cases, change the selection state so that it is the closest to (N2ZM) step! I prefer to.
- the frequency divider be reset when the selection state is changed by the selector.
- the selection state is not changed for a certain period of time after the selection state is changed by the selector.
- U prefer to hold.
- the program of the present invention is characterized in that it is a program for causing a computer to execute the method for setting the frequency variable range of the PLL circuit of the present invention.
- the frequency variable range is set when the frequency variable range setting operation is performed.
- the frequency of the range matches the target frequency or the target frequency Until it exceeds, the step of the frequency variable range is changed with a relatively large change width, so that the time required for setting the frequency variable range can be reduced.
- the step of the frequency variable range is changed with a relatively small change width. Since the frequency variable range is brought closer to the target frequency by making the change, it is possible to converge the frequency variable range frequency to the target frequency in a short time by repeating those operations.
- FIG. 1 is a block diagram of a quadruple circuit using a PLL circuit according to the first embodiment of the present invention.
- FIG. 1 the same components as those in FIG. 11 described above are denoted by the same reference numerals, and redundant description will be omitted.
- the quadruple-multiplier circuit using the PLL circuit according to the first embodiment of the present invention compares the phase of the reference signal with the phase of the internal signal, and outputs a signal corresponding to the phase difference.
- a phase comparator 1 that outputs a phase difference signal, a charge pump 2 and a loop filter 3, a plurality of voltages having different frequency variable ranges, and each of which has an oscillation frequency controlled based on the phase difference signal.
- a group of voltage-controlled oscillators 4 consisting of controlled oscillators (multiple oscillators: for example, 15 voltage-controlled oscillators from VCO1 to VCO15) and a signal with a desired oscillation frequency among multiple voltage-controlled oscillators can be output
- a selection circuit (selector) 6 for selecting any one of the voltage-controlled oscillators (any one of VC01 to VC015) based on the phase difference signal, and a voltage-controlled oscillator (selector) selected by the selection circuit 6
- An internal signal is generated by dividing the output of any one of VC01 to VC015).
- a frequency divider 5 for, and a 2-input AND circuit 7, a two-input OR circuit 8, the.
- the selection state of the voltage controlled oscillator by the selection circuit 6 is changed, if the frequency of the currently selected voltage controlled oscillator is lower than the target frequency, The frequency of the frequency variable range of the voltage-controlled oscillator matches the target frequency. Until the frequency reaches or exceeds the target frequency, the selection of the selected VCO is repeated so that the frequency variable range of the selected VCO increases by several steps. However, if the frequency variable range can be increased by only one step, the voltage-controlled oscillator to be selected is changed so as to increase by one step.
- the voltage to be selected is set so that the frequency variable range of the voltage-controlled oscillator is reduced with a smaller change width than before the frequency exceeds the target frequency. Change the control oscillator.
- the frequency in the frequency variable range of the currently selected voltage controlled oscillator is higher than the target frequency, the frequency in the frequency variable range of the voltage controlled oscillator matches the target frequency or Until the frequency falls below the target frequency, the selection of the voltage-controlled oscillator to be selected is repeated so that the frequency variable range of the selected voltage-controlled oscillator decreases by several steps. However, if the frequency variable range can be lowered by only one step, the voltage-controlled oscillator to be selected is changed so that it is lowered by one step.
- the voltage to be selected is selected so that the frequency variable range of the voltage-controlled oscillator increases with a smaller change width than before the frequency falls below the target frequency. Change the control oscillator.
- the frequency of the current frequency variable range is changed to the target frequency.
- the frequency variable range is increased by N steps (N is an integer of 2 or more: for example, 4 steps (steps) as described later) (however, if N steps cannot be increased, N Change the selection state so that the frequency in the current frequency variable range is higher than the target frequency, so that the frequency variable range is N steps (N is an integer of 2 or more). Change the selection state so that it becomes lower (however, if it cannot be lowered by N steps, it will be V closest to N steps, lower by only the steps).
- the selection circuit 6 changes the frequency of the current frequency variable range to the target frequency. If it is lower, the frequency variable range will be increased by the same number of steps as the previous time (however, if the number of steps cannot be increased as the previous time, it will be increased by the closest number of steps to the previous time) If the selected state is changed and the target frequency is exceeded by the previous change, the frequency variable range is half the number of steps as before (however, if half of the previously changed number is not an integer, the decimal point Change the selection state so that it is lower by only one of the following: round down, round up, or round off. If the current frequency variable range frequency is higher than the target frequency, the frequency variable range is Change the selection state so that the number of steps is decreased by the same number of steps as the previous time (however, if the number of steps cannot be decreased by the same time as the previous time, the number of steps is decreased by the same number of steps and the nearest V
- the frequency variable range will be half the number of previous steps (however, if half of the previously changed number of steps is not an integer, the fractional part will be rounded down, rounded up and rounded off.
- the selection state is changed so as to increase the selection state.
- the output signal S 14 output from the two-input OR circuit 8 of the selection circuit 6 is input to the loop filter 3.
- control is performed such that the control signal S4 output from the loop filter 3 takes a value between the threshold voltages Vrefl and Vref2. Is done. As a result, for a certain period of time after the selection state is changed by the selection circuit 6, the state is not changed.
- the output signal S 14 is input to the two-input AND circuit 7 together with the reference signal fREF.
- the output of the two-input AND circuit 7 is input to the reset terminal R of the frequency divider 5.
- the signal input to the frequency divider 5 from the two-input AND circuit 7 allows the phase of the internal signal fIN, which is the output from the frequency divider 5 based on the output signal fOUT, and the phase of the reference signal fREF Are synchronized with each other.
- the selection circuit 6 includes a voltage comparator 418 having a threshold voltage Vrefl, and a voltage comparator 419 having a threshold voltage Vref2 (> Vrefl).
- the voltage comparators 418 and 419 receive the control signal S4, the voltage comparator 418 outputs an output signal S15, and the voltage comparator 419 outputs an output signal S16.
- Voltage comparator 418 operates when the voltage of input control signal S4 is lower than threshold voltage Vrefl. In this case, the output signal S15 is set to a low potential (L) for a certain period of time, while when it is high, the output signal S15 is set to a high potential (H) for a certain period of time.
- the voltage comparator 419 sets the output signal S16 to the high potential (H) for a certain period of time, When it is low, the output signal S16 is set to a low potential (L) for a certain period of time.
- the output signals S15 and S16 of the voltage comparators 418 and 419 are input to the counter set signal generation circuit 442 and the level detection signal history counter 441.
- the counter set signal generation circuit 442 is connected to the voltage comparators 418 and 419,
- the counter set signal generation circuit 442 counts up or down by predetermined steps (for example, 4 steps, 2 steps or 1 step) according to the instruction of the level detection signal history counter 441. Therefore, only the third bit (with the least significant bit as the first bit) of the up / down counter 426, or the second bit, or the least significant bit, is moved by "1".
- the selection switch 436 is switched according to the output of the up / down counter 426, and a voltage controlled oscillator (one of VCO 1 to VCO 15) corresponding to each output is selected.
- FIG. 2 is a flowchart showing the operation of the level detection signal history counter 441 used in the present embodiment.
- step S101 when one of the output signals S15 and S16 input to the level detection signal history counter 441 becomes “H” (step S101), the fact is detected.
- step S102 it is determined whether a predetermined time (for example, 60 microseconds) has elapsed after the “H” level of the output signals S15 and S16 was previously input (step S102). That is, it is determined whether or not the force has passed a predetermined time since the selection state of the voltage controlled oscillator (any one of VCO 1 to VCO 15) is changed by the selection circuit 6 last time.
- a predetermined time for example, 60 microseconds
- step S102 If the predetermined time has not elapsed (Y in step S102), the process proceeds to step S103, in which "H" is currently output, and the voltage comparator which outputs "H” last time outputs "H". It is determined whether it is the same as the voltage comparator.
- step S103 If they are the same (Y in step S103), the process shifts to step S105, and the same The number of steps is instructed to the signal generation circuit 442.
- step S103 when it is determined that the "H" level is output from the voltage comparator different from the previous time (N in step S103), the process proceeds to step S104, and the number of steps of 1Z2 of the previous number of steps is calculated. Instruct the signal generation circuit 442.
- step S102 when it is determined that the predetermined time has elapsed since the previous "H" level was input (N in step S102), the process proceeds to step S106, and the number of steps "4" is set. Instruct the signal generation circuit 442.
- the counter set signal generation circuit 442 which receives the instruction of the number of steps from the level detection signal history counter 441 responds to the received instruction and which of the output signals S15 and S16 has become the "H" level. Then, the count value of the up / down counter 426 is changed.
- the up / down counter 426 operates the selection switch 436 according to the new count value to select the voltage controlled oscillator (any one of VC01 to VC015).
- step S106 if there is no voltage-controlled oscillator corresponding to the count value of the fourth step (N-th step), the counter 426 sets the three-step, two-step,
- the voltage-controlled oscillator is selected such that the frequency variable range is increased only at the step closest to N steps.
- the output signal S14 temporarily becomes high potential (H), and the potential of the control signal S4 output from the loop filter is forcibly set to the threshold value shown in FIG. Since the voltage is set higher than the voltage Vrefl and lower than the voltage Vre! 2, the outputs of the voltage comparators 418 and 419 return to a low potential (L).
- the output signal S14 and the reference signal fREF are input, and the two-input AND circuit 7 resets the frequency divider 5 for a certain period of time when the selection state of the voltage controlled oscillator changes.
- the output phase of the device 5 is synchronized.
- the phase comparator 1 can detect a large change in frequency due to a change in the selected state of the voltage-controlled oscillator in a short time, and the frequency variable ranges different from each other can be detected. It is possible to prevent an erroneous voltage controlled oscillator from being selected from among the voltage controlled oscillators having any of (VC01 to VC015).
- the frequency variable range of the voltage-controlled oscillator (one of VC01 to VC015) after the selection exceeds the desired (target) frequency by a plurality of steps ( For example, since the voltage is changed by four steps at a time, the time required until a voltage-controlled oscillator having a desired frequency can be selected can be greatly reduced.
- FIG. 3 is a characteristic diagram showing an oscillation frequency characteristic with respect to the voltage of the control signal S4 of the voltage-controlled oscillator group 4 of the present embodiment.
- Each of A to H is a part of the control voltage-oscillation frequency characteristic of the voltage-controlled oscillator group 4, and the frequencies fl to fl5 are represented by fl ⁇ f2 ⁇ f3 ⁇ ... ⁇ Fl2 ⁇ f 13 ⁇ fl4 ⁇ fl5 It is in.
- the desired oscillation frequency that is, the frequency fosc, which is four times the frequency of the input reference signal fREF, is within the range of the control voltage-oscillation frequency characteristic of A (frequency variable range).
- step S101 the control voltage S4 exceeds the threshold voltage Vre! 2
- the output signal S16 of the voltage comparator 419 becomes low potential (H) for a fixed time
- the level detection signal history counter 441 proceeds to step S101.
- the counter set signal generation circuit 442 receiving this instruction generates a signal for incrementing the third bit from the least significant bit of the up / down counter 426 by “1”.
- the up / down counter 426 performs a 4-step up-count operation.
- the selection state of the voltage-controlled oscillator changes from the characteristic A to the characteristic B, and at the same time, the output signal S14 temporarily becomes high potential (H), and the control signal S4 becomes high. Since the voltage temporarily returns to a voltage in the range between the threshold voltage Vrefl and the threshold voltage Vref2, the output of S16 returns to the low potential (L) after the switching of the voltage controlled oscillator.
- the frequency divider 5 is reset for a certain period of time when the selection state of the voltage controlled oscillator changes by the two-input AND circuit 7 to which the output signal S14 and the reference signal fREF are input.
- the output phase of the frequency divider 5 is synchronized, and the phase comparator 1 detects and returns a large change in frequency caused by a change in the selected state of the voltage-controlled oscillator in a short time, thereby detecting a voltage-controlled oscillator that should not be selected. It is possible to prevent erroneous selection.
- step S101 when detecting the "H" level input in step S101, the level detection signal history counter 441 shifts to step S102 to determine whether or not the previous "H" level input force has passed a predetermined time. Since the predetermined time has elapsed before this time, the process proceeds to step S103, and it is determined whether or not the “H” level is output from the same voltage comparator as before.
- step S105 since the same voltage comparator outputs the signal, the process proceeds to step S105, and the signal generation circuit 442 is instructed to have the same number of steps as "4" as in the previous time.
- the up / down counter 426 counts up by four steps, and the selected state of the voltage-controlled oscillator changes from the characteristic B to the characteristic C. Then, even if the PLL control based on the characteristic B is performed, the frequency of the internal signal ⁇ ⁇ ⁇ ⁇ is still lower than the frequency of the reference signal fREF, so that the voltage of the control signal S4 exceeds the threshold voltage Vref2 again. With this operation, the selection of the voltage controlled oscillator changes from the characteristic C to the characteristic D.
- step S101 when detecting the "H" level input in step S101, the level detection signal history counter 441 shifts to step S102 to determine whether or not the previous "H" level input force has passed a predetermined time. Since the predetermined time has elapsed before this time, the process proceeds to step S103, and it is determined whether or not the “H” level is output from the same voltage comparator as before.
- the counter set signal generation circuit 442 receiving this instruction generates a signal for causing the up / down counter 426 to count down by two steps when the signal S15 goes to the "H" level.
- the characteristic D transitions to the characteristic E, and finally locks to the point b.
- the frequency division ratio of the frequency divider 5 is switched so that the desired oscillation frequency fosc is set to the point a within the frequency range of the characteristic A when the current characteristic E is locked at the point b. Then, as shown by the dotted line in Fig. 3, the characteristic E ⁇ characteristic F ⁇ characteristic G ⁇ characteristic H transitions and finally locks to point a of characteristic A.
- a voltage-controlled oscillator is selected in a wideband PLL circuit using a number of voltage-controlled oscillators having mutually different frequency variable ranges.
- the frequency variable range has a relatively large change width (for example, every four steps). Since the steps are changed, the time required for setting the frequency variable range can be reduced.
- the frequency of the frequency variable range exceeds the target frequency (when the step of the frequency variable range is changed so as to exceed the target frequency)
- a relatively small change width for example, By changing the step of the frequency variable range in half the step of the previous change width, the frequency variable range approaches the target frequency. Accordingly, the frequency in the frequency variable range can be converged to the target frequency in a short time.
- the frequency variable range is changed in N steps (N is an integer of 2 or more).
- N is an integer of 2 or more.
- the frequency variable range is changed by the same number of steps as before until the frequency variable range is changed over the target frequency, and the frequency variable range is changed over the target frequency. If the number of stages has been changed, the number of stages will be half of the previous number.
- the fractional part shall be rounded down, rounded up or rounded off Good, just change the frequency variable range Therefore, by repeating the operation, the frequency in the frequency variable range can be converged to the target frequency in a short time.
- FIG. 4 is a block diagram of a quadruple circuit using a PLL circuit according to the second embodiment of the present invention.
- the same components as those in FIG. 1 described above are denoted by the same reference numerals, and detailed description is omitted.
- the frequency of the current frequency variable range is changed to the target frequency. If the frequency is lower than the current frequency variable range, assuming that the number of steps in the frequency variable range that is higher than the current frequency variable range is N1, N1 is divided by an integer M greater than or equal to 2 and the frequency variable range is raised by (N1ZM) steps Thus, the selection state by the selection circuit 6 is changed.
- decimal point of (N1 ZM) shall be rounded down, rounded up or rounded off, and any of the (N1Z M) stage or (N1ZM) rounded down, rounded up or rounded down If the value cannot be increased by the step of the value, the selection state by the selection circuit 6 is changed so that the level is increased only by the step closest to that step.
- the number of steps in the frequency variable range whose steps are lower than the current frequency variable range is N1, and N1 Is divided by an integer M of 2 or more, and the selection state by the selection circuit 6 is changed so that the frequency variable range becomes lower by (NlZM) steps.
- N1ZM decimal part of (N1ZM) shall be rounded down, rounded up or rounded off
- the decimal point of (N1ZM) or (N1ZM) shall be rounded down, rounded up or rounded off. If the value cannot be lowered only by the level, the selection state by the selection circuit 6 is changed so that the level is lowered only by the level closest to that level.
- the frequency of the current frequency variable range is If the frequency is lower than the target frequency, assuming that the number of steps changed last time is N2, N2 is divided by an integer M that is 2 or more, and the selection state is changed so that the frequency variable range becomes higher by (N2ZM) steps. However, if N2ZM is not an integer, the fractional part shall be rounded down, rounded up or rounded off and rounded down to the (N2ZM) stage or (N2ZM). If it is not possible to raise the level of any of the five values, change the selection state so that the level closest to that level is raised.
- N2 is divided by an integer M of 2 or more, and the frequency variable range becomes (N2ZM) Change the selection state so that it is lower by a step.
- N2ZM is not an integer
- the decimal point shall be rounded down, rounded up or rounded off
- the decimal point of (N2ZM) stage or (N2ZM) shall be rounded down, rounded up and rounded down. If the value cannot be lowered by the value of the input force, it is the closest to the (N2ZM) level! Change the selection state so that it becomes lower only by the stage.
- the PLL circuit according to the present embodiment is used in the first embodiment, and instead of the level detection signal history counter 441, a counter circuit is used.
- a history holding circuit 443 is provided.
- the counter history holding circuit 443 stores the counter history of the up / down counter 426, and controls the counter set signal generation circuit 442 based on the history information.
- FIG. 5 is a flowchart showing the operation of the counter history holding circuit 443 used in the present embodiment.
- the counter history holding circuit 443 is provided with the voltage currently selected by the up / down counter 426.
- the control oscillator and the previously selected voltage controlled oscillator are stored.
- One of the output signals S15 and S16 input to the counter history holding circuit 443 is "H".
- step S202 it is determined whether or not a predetermined time has passed since the “H” level of the output signals S15 and S16 was previously input.
- the number N2 indicating how many steps the frequency variable range has changed due to the previous change of the voltage controlled oscillator is set to an integer of 2 or more.
- step S203 Divide it by M (step S203), output the quotient (round up, round down, or round off to the nearest decimal) to the counter set signal generation circuit 442 (step S204), and end the processing.
- step S202 If the predetermined time has elapsed (N in step S202), the flow shifts to step S205, and it is determined whether or not the output signal S15 of the output signals S15 and S16 has reached the "H" level. Is determined.
- the oscillation frequency is lower than that of the currently selected VCO! ⁇ Divide the number of voltage controlled oscillators (N1) by an integer M greater than or equal to 2 (step S206), and output the quotient (round up, round down or round down to 4 decimal places) to the counter set signal generation circuit 442 (step (S207), the process ends.
- step S205 If it is determined that the output signal S16 is at the "H" level among the output signals S15 and S16 (N in step S205), the oscillation is performed more than the currently selected voltage-controlled oscillator.
- the frequency is high, the number of voltage controlled oscillators (N1) is divided by an integer M of 2 or more (step S208), and the quotient (rounded up, rounded down, or rounded down to the decimal point) is sent to the counter set signal generation circuit 442.
- Output step S209) and end the process.
- the counter set signal generation circuit 442 receiving the calculation result from the counter history holding circuit 443 determines whether the received calculation result and which of the output signals S15 and S16 has become the "H" level. The count value of the up / down counter 426 is changed accordingly.
- FIG. 6 is a characteristic diagram showing an oscillation frequency characteristic of the voltage-controlled oscillator group 4 of the present embodiment with respect to the voltage of the control signal S4.
- a to D are part of the control voltage-oscillation frequency characteristics of the voltage controlled oscillator group.
- Frequencies fl to ⁇ 5 are in the relationship of fl ⁇ f2 ⁇ f3 ⁇ ... ⁇ fl2 ⁇ fl3 ⁇ fl4 ⁇ fl5 .
- the oscillation frequency is within the frequency range of the desired oscillation frequency, that is, four times the frequency of the input reference signal fREF, of the fosc force characteristic A.
- the output signals S15 of the voltage comparators 418 and 419 The counter 426 does not perform the count operation while S16 does not become the high potential (H).
- the state of the selection circuit 6 does not change in the initial state.
- the counter history holding circuit 443 proceeds to step S201. This is detected at step S202, and it is determined at step S202 whether or not a force has passed a predetermined time since the previous "H" level signal was input.
- the predetermined time is set to be about the time when the PLL control is performed by one voltage-controlled oscillator and the control signal S4 changes between the threshold voltages Vrefl and Vre! 2.
- step S208 Due to the change in the division ratio when the PLL circuit is in the locked state, when the "H" level signal is input, a predetermined time has elapsed since the previous "H” level signal was input. Therefore, the process proceeds to step S208 via step S205, and divides the number of voltage-controlled oscillators (N1) having an oscillation frequency higher than the currently selected voltage-controlled oscillator by M (here, for example, M is 2). .
- the quotient is “6”.
- the counter set signal generation circuit 442 receiving this “6” and the “H” level of the output signal S16 instructs the counter 426 to perform a 6-step up-count. This causes the selected state of the voltage controlled oscillator to transition to characteristic B. [0155] Then, the output signal S14 becomes high potential (H) due to the "H" level of the output signal S16, and the control signal S4 temporarily returns to a voltage in the range between the threshold voltage Vrefl and the threshold voltage Vref2. Therefore, the output signal S16 returns to the low potential (L) after the switching of the voltage controlled oscillator.
- the frequency divider 5 is reset for a certain period of time when the selection state of the voltage controlled oscillator changes by the two-input AND circuit 7 to which the output signal S14 and the reference signal are input.
- the output phase of the VCO is synchronized, and the phase comparator 1 detects and feedbacks a large change in the frequency caused by the change of the selected state of the VCO in a short time. VCO 1 to VCO 15) can be prevented from being selected incorrectly.
- the counter history holding circuit 443 detects that the output signal S16 of the voltage comparator 419 has become high potential (H) in step S201, and inputs the previous “H” level signal in step S202. Then, it is determined whether or not a predetermined time has elapsed.
- step S202 since the “H” level signal is input again within a short time after the previous “H” level input (Y in step S202), the process proceeds to step S203, and the number of the previously changed steps ( Steps: Divide N2) by M (for example, 2).
- the number of steps N2 changed last time that is, the number of steps N2 when changing the selection state from the voltage controlled oscillator of characteristic A to the voltage controlled oscillator of characteristic B is “6”. Therefore, the quotient divided by "2" is "3".
- the counter history holding circuit 443 detects that the output signal S16 of the voltage comparator 419 has become high potential (H) in step S201, and in step S202, outputs the previous "H" level signal. Is input and the force is determined as to whether or not a predetermined time has elapsed.
- Step S203 since the "H" level signal is input again within a short time after the previous "H” level input (Y in step S202), the process proceeds to step S203, and the number of previously changed steps is changed. (Steps: N2) divided by M (for example, 2).
- the number of steps N2 changed last time that is, the number of steps N2 when changing the selection state to the voltage-controlled oscillator of the characteristic B and the voltage-controlled oscillator of the characteristic C is " 3 ", the quotient divided by" 2 "becomes" 1 "by truncating the decimal part, for example.
- the counter set signal generation circuit 442 receiving this "1" and the "H” level of the output signal S16 instructs the up / down counter 426 to count up by one step.
- the selected state of the voltage controlled oscillator changes to the characteristic D.
- the same PLL control as described above is performed, and finally locked at point b.
- the frequency in the current frequency variable range is changed.
- N1 is divided by an integer M of 2 or more, and the frequency variable range becomes (N1ZM)
- the selection state by the selection circuit 6 is changed so as to be higher by a step. If the frequency of the current frequency variable range is higher than the target frequency, the frequency lower than the current frequency variable range Assuming that the number of steps in the variable range is N1, N1 is divided by an integer M equal to or greater than 2 and the selection state by the selection circuit 6 is changed so that the frequency variable range becomes lower by (N1ZM) steps.
- the first implementation described above can be performed by setting If the target frequency can be approached faster than in the case of the form, an effect can be obtained.
- the frequency of the current frequency variable range is If the frequency is lower than the target frequency, assuming that the previously changed number of steps is N2, N2 is divided by an integer M that is 2 or more, and the selection state is changed so that the frequency variable range becomes higher by (N2ZM) steps. If the frequency of the frequency variable range of is higher than the target frequency, and the number of steps changed previously is N2, N2 is divided by an integer M of 2 or more, and the frequency variable range becomes lower by (N2ZM) steps. Since the selection state is changed as described above, the step of the frequency variable range that crosses the target frequency is not changed, so that the change by the selection state by the selection circuit 6 can be prevented from being lost.
- FIG. 7 is a block diagram of a quadruple circuit using a PLL circuit according to the third embodiment of the present invention.
- the same components as those in FIG. 1 described above are denoted by the same reference numerals, and detailed description is omitted.
- the oscillator 400 is replaced with the voltage-controlled oscillator group 4 (having the voltage-controlled oscillators VC01 to VC15 having mutually different frequency variable ranges) in the PLL circuit according to the first embodiment.
- the voltage-controlled oscillator group 4 having the voltage-controlled oscillators VC01 to VC15 having mutually different frequency variable ranges
- This oscillator 400 includes a resonance circuit group 434 having resonance circuits (for example, LC resonance circuits 1 to 15) having resonance frequencies different from each other.
- Each of the LC resonance circuits 1 to 15 is composed of an inductor and a capacitor.
- the PLL circuit according to the third embodiment selects a selected one of the LC resonance circuits 1 to 15 of the resonance circuit group 434 (one of the LC resonance circuits 1 to 15). By switching at 436, it functions similarly to the PLL circuit according to the first embodiment.
- the selection circuit 6 selects one resonance circuit from the LC resonance circuits 1 to 15 so that the frequency variable range of the oscillator 400 can be changed to any one of a plurality of different frequency variable ranges. Force can be set to one frequency variable range, and a signal of a desired oscillation frequency can be output from the oscillator 400.
- the selection state of the LC resonance circuits 1 to 15 by the selection circuit 6 is changed.
- the frequency of the current variable range of the oscillator 400 is lower than the target frequency by V, if the frequency of the variable range matches the target frequency or exceeds the target frequency, The change of the selected resonance circuit is repeated so that the frequency variable range of the oscillator 400 becomes higher by a plurality of steps.
- the frequency variable range can be increased by only one step, change the selected resonance circuit so that it is increased by one step.
- the resonance circuit is selected so that the frequency variable range of the oscillator 400 is smaller than before the frequency exceeds the target frequency and the variation width becomes lower with the change width. To change.
- FIG. 8 is a block diagram of a quadruple circuit using a PLL circuit according to a fourth embodiment of the present invention.
- the same components as those in FIG. 4 described above are denoted by the same reference numerals, and detailed description is omitted.
- An oscillator 400 is provided in place of 4 (having voltage-controlled oscillators VC01 to VC15 having mutually different frequency variable ranges).
- the oscillator 400 includes a resonance circuit group 434 having resonance circuits (for example, LC resonance circuits 1 to 15) having resonance frequencies different from each other.
- Each of the LC resonance circuits 1 to 15 is composed of an inductor and a capacitor.
- the PLL circuit according to the fourth embodiment selects a selected one of the LC resonance circuits 1 to 15 of the resonance circuit group 434 (one of the LC resonance circuits 1 to 15) by a selection switch. By switching at 436, it functions similarly to the PLL circuit according to the second embodiment.
- the selection circuit 6 selects one of the LC resonance circuits 1 to 15 so that the frequency variable range of the oscillator 400 can be changed to any one of a plurality of different frequency variable ranges. Force can be set to one frequency variable range so that the oscillator 400 can output a signal of a desired oscillation frequency.
- FIG. 9 is a block diagram of a quadruple circuit using a PLL circuit according to the fifth embodiment of the present invention.
- the same components as those in FIG. 1 described above are denoted by the same reference numerals, and detailed description is omitted.
- a ring oscillator (oscillator) 435 is provided in place of 4 (having voltage controlled oscillators VC01 to VC15 having different frequency variable ranges).
- the ring oscillator 435 is configured by connecting (connecting) a plurality of inverters (delay circuits) with variable delay times in series with each other.
- the PLL circuit according to the fifth embodiment functions similarly to the PLL circuit according to the first embodiment by switching the number of connected inverters in the ring oscillator 435 by the selection switch 436.
- the selection circuit 6 can change the frequency in a wide range by selecting the number of connected inverters in the ring oscillator 435.
- the selection circuit 6 selects the number of connected inverters in the ring oscillator 435, so that the frequency variable range of the ring oscillator 435 can be any one of a plurality of different frequency variable ranges. By setting the range, a signal of a desired oscillation frequency can be output from the ring oscillator 435.
- the selection state of the number of connected inverters by the selection circuit 6 is changed.
- the frequency of the current variable frequency range of the ring oscillator 435 is lower than the target frequency
- the frequency of the variable frequency range is equal to or higher than the target frequency.
- the number of links to be selected is repeatedly changed so that the frequency variable range of the ring oscillator 435 becomes higher by several steps. However, if the frequency variable range can only be increased by one step, the number of connections is changed so that it is increased by one step.
- the selection is made so that the frequency variable range of the ring oscillator 435 decreases with a smaller change width than before the frequency exceeds the target frequency. Change the number of concatenations.
- the frequency force of the current frequency variable range of the ring oscillator 435 is higher than the target frequency, and in that case, until the frequency of the frequency variable range matches the target frequency or falls below the target frequency. Then, the change of the number of links to be selected is repeated so that the frequency variable range of the ring oscillator 435 becomes lower by a plurality of steps. However, if the frequency variable range cannot be lowered by only one step, the number of links to be selected is changed so that it is lowered by one step.
- the number of couplings to be selected is set so that the frequency variable range of the ring oscillator 435 becomes higher with a smaller change width than before the lower frequency. To change.
- FIG. 10 is a block diagram of a quadruple circuit using a PLL circuit according to the sixth embodiment of the present invention.
- the same components as those in FIG. 4 described above are denoted by the same reference numerals, and detailed description is omitted.
- a ring oscillator ( Oscillator) 435 instead of the voltage controlled oscillator group 4 (having voltage controlled oscillators VC01 to VC15 having mutually different frequency variable ranges) in the PLL circuit according to the second embodiment, a ring oscillator ( Oscillator) 435.
- the ring oscillator 435 is configured by connecting (connecting) a plurality of inverters (delay circuits) with variable delay times in series with each other.
- the PLL circuit according to the sixth embodiment includes the number of connected inverters in ring oscillator 435. Is switched by the selection switch 436, thereby functioning similarly to the PLL circuit according to the second embodiment.
- the selection circuit 6 can change the frequency in a wide range by selecting the number of connected inverters in the ring oscillator 435.
- the selection circuit 6 selects the number of connected inverters in the ring oscillator 435, thereby changing the frequency variable range of the ring oscillator 435 to one of a plurality of different frequency variable ranges. By setting the range, a signal of a desired oscillation frequency can be output from the ring oscillator 435.
- a voltage controlled oscillator having such characteristics that the oscillation frequency becomes higher as the potential of the voltage of the control signal S4 becomes higher is used. It is also possible to use a voltage controlled oscillator having characteristics such that the oscillation frequency decreases as the potential of the voltage of the control signal S4 increases. In this case, if the threshold voltages Vrefl and Vref2 are used as they are, if the voltage of the control signal S4 falls below the threshold voltage Vrefl, the PLL lock characteristic switches to a higher frequency characteristic than the current characteristic. , The characteristics will be switched.
- phase comparator 1 is used. Instead of this, a frequency phase comparator may be used.
- the oscillation frequency of the voltage controlled oscillator is controlled by the output signal of the loop filter 3, but may be controlled by a phase difference signal instead.
- the counter is incremented or decremented by 4 steps first! However, you can use other steps such as 2 steps or 8 steps!
- a wireless device may be configured by adding various components such as an antenna to the PLL circuit described in each of the above embodiments. it can.
- a wireless communication terminal device for example, a mobile communication device such as a mobile phone
- Terminal device for example, a mobile communication device such as a mobile phone
- FIG. 1 is a block diagram of a quadruple circuit that is a PLL circuit according to a first embodiment of the present invention.
- FIG. 2 is a flowchart illustrating an operation of a level detection signal history counter in the circuit of FIG. 1.
- FIG. 3 is a control characteristic diagram of a group of voltage-controlled oscillators in the circuit of FIG. 1, particularly an explanatory diagram of a switching operation.
- FIG. 4 is a block diagram of a quadruple circuit that is a PLL circuit according to a second embodiment of the present invention.
- FIG. 5 is a flowchart for explaining the operation of a counter history holding circuit in the circuit of FIG.
- FIG. 6 is a control characteristic diagram of a group of voltage-controlled oscillators in the circuit of FIG. 4, particularly an explanatory diagram of a switching operation.
- FIG. 7 is a block diagram of a quadruple circuit that is a PLL circuit according to a third embodiment of the present invention.
- FIG. 8 is a block diagram of a quadruple circuit that is a PLL circuit according to a fourth embodiment of the present invention.
- FIG. 9 is a block diagram of a quadruple circuit that is a PLL circuit according to a fifth embodiment of the present invention.
- FIG. 10 is a block diagram of a quadruple circuit that also has a PLL circuit power according to a sixth embodiment of the present invention.
- FIG. 11 is a block diagram of a conventional quadruple multiplication circuit which also has a PLL circuit power.
- FIG. 12 is a circuit diagram of a selection circuit in the circuit of FIG.
- FIG. 13 is a control characteristic diagram of a group of voltage-controlled oscillators in the circuit of FIG.
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2006511563A JP4288425B2 (ja) | 2004-03-29 | 2005-03-28 | Pll回路 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2004-094308 | 2004-03-29 | ||
JP2004094308 | 2004-03-29 |
Publications (1)
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WO2005093956A1 true WO2005093956A1 (ja) | 2005-10-06 |
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ID=35056530
Family Applications (1)
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PCT/JP2005/005746 WO2005093956A1 (ja) | 2004-03-29 | 2005-03-28 | Pll回路 |
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WO (1) | WO2005093956A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1865603A1 (en) * | 2005-03-31 | 2007-12-12 | Fujitsu Ltd. | Clock selecting circuit and synthesizer |
JP2009147916A (ja) * | 2007-11-21 | 2009-07-02 | Fujitsu Ten Ltd | 映像信号処理装置 |
JP2016218903A (ja) * | 2015-05-25 | 2016-12-22 | 富士通株式会社 | 位相ロックループ回路制御装置及び位相ロックループ回路の制御方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06104748A (ja) * | 1992-06-22 | 1994-04-15 | Matsushita Electric Ind Co Ltd | Pll回路 |
JPH09284681A (ja) * | 1996-04-19 | 1997-10-31 | Fujitsu General Ltd | Pll回路 |
-
2005
- 2005-03-28 WO PCT/JP2005/005746 patent/WO2005093956A1/ja active Application Filing
- 2005-03-28 JP JP2006511563A patent/JP4288425B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06104748A (ja) * | 1992-06-22 | 1994-04-15 | Matsushita Electric Ind Co Ltd | Pll回路 |
JPH09284681A (ja) * | 1996-04-19 | 1997-10-31 | Fujitsu General Ltd | Pll回路 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1865603A1 (en) * | 2005-03-31 | 2007-12-12 | Fujitsu Ltd. | Clock selecting circuit and synthesizer |
EP1865603A4 (en) * | 2005-03-31 | 2009-11-18 | Fujitsu Ltd | TAKTA SELECTION AND SYNTHESIZER |
US7750747B2 (en) | 2005-03-31 | 2010-07-06 | Fujitsu Limited | Clock selection circuit and synthesizer |
JP2009147916A (ja) * | 2007-11-21 | 2009-07-02 | Fujitsu Ten Ltd | 映像信号処理装置 |
JP2016218903A (ja) * | 2015-05-25 | 2016-12-22 | 富士通株式会社 | 位相ロックループ回路制御装置及び位相ロックループ回路の制御方法 |
Also Published As
Publication number | Publication date |
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JP4288425B2 (ja) | 2009-07-01 |
JPWO2005093956A1 (ja) | 2008-02-14 |
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