WO2005088693A1 - Line edge roughness control - Google Patents

Line edge roughness control Download PDF

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Publication number
WO2005088693A1
WO2005088693A1 PCT/US2005/007386 US2005007386W WO2005088693A1 WO 2005088693 A1 WO2005088693 A1 WO 2005088693A1 US 2005007386 W US2005007386 W US 2005007386W WO 2005088693 A1 WO2005088693 A1 WO 2005088693A1
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WO
WIPO (PCT)
Prior art keywords
arc
layer
etched
arc open
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/007386
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English (en)
French (fr)
Inventor
Youngjin Choi
Helen H. Zhu
Sangheon Lee
Sean S. Kang
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Lam Research Corp
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Lam Research Corp
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Filing date
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Priority to JP2007502898A priority Critical patent/JP2007528610A/ja
Publication of WO2005088693A1 publication Critical patent/WO2005088693A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • a method for etching a layer through a photoresist mask with an ARC layer between the layer to be etched and the photoresist mask over a substrate is provided.
  • the substrate is placed into a processing chamber.
  • An ARC open gas mixture is provided into the processing chamber.
  • the ARC open gas mixture comprises an etchant gas and a polymerization gas comprising CO and CH F.
  • An ARC open plasma is formed from the ARC open gas mixture.
  • the ARC layer is' etched with the ARC open plasma until the ARC layer is opened.
  • the ARC open gas mixture stopped before the layer to be etched is completely etched.
  • a method for forming a semiconductor device is provided.
  • a layer to be etched is placed over a substrate.
  • An organic ARC layer is formed over the layer to be etched.
  • a photoresist mask is formed over the ARC layer.
  • the substrate into is placed into a processing chamber.
  • An ARC open gas mixture is provided into the processing chamber.
  • the ARC open gas mixture comprises an etchant gas and a polymerization gas comprising CO and CH 3 F.
  • An ARC open plasma is formed from the ARC open gas mixture.
  • the ARC layer is etched with the ARC open plasma until the ARC layer is opened.
  • FIG. 1 is a high level flow chart for forming a feature in a dielectric layer, which uses an inventive antireflective coating (ARC) open process.
  • ARC antireflective coating
  • FIG.'s 2A-C are cross-sectional views of an etch layer over a substrate during the formation of features using the inventive ARC open process.
  • FIG. 3 is a more detailed flow chart of a step of the opening of the ARC layer.
  • FIG. 4 is a schematic view of a process chamber that may be used in a preferred embodiment of the invention.
  • FIG.'s 5 A and 5B illustrate a computer system, which is suitable for implementing a controller.
  • FIG.'s 6A-B are cross-sectional views of an etch layer over a substrate after an ARC opening is performed.
  • FIG.'s 7A-B are cross-sectional views of an etch layer over a substrate after features have been etched into the etch layer.
  • FIG.'s 8A-B are cross-sectional views of an etch layer over a substrate after an etch layer after an ARC opening
  • FIG.'s 9A-B are cross-sectional views of an etch layer over a substrate after features have been etched into the etch layer after a prior art ARC open process has been used.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details.
  • FIG. 1 is a high level flow chart for forming a feature in a dielectric layer, which uses the inventive antireflective coating (ARC) open process.
  • An ARC layer is formed over an etch layer, which is a layer to be etched (step 104).
  • FIG. 2A is a cross-sectional view of an etch layer 204 over a substrate 208.
  • An ARC layer 216 has been formed over the etch layer 204.
  • a photoresist mask 220 is formed over the ARC layer 216 (step 108).
  • the ARC layer is opened (step 112).
  • FIG. 1 is a high level flow chart for forming a feature in a dielectric layer, which uses the inventive antireflective coating (ARC) open process.
  • An ARC layer is formed over an etch layer, which is a layer to be etched (step 104).
  • FIG. 2A is a cross-sectional view of an etch layer 204 over a substrate 208.
  • An ARC layer 216 has
  • FIG. 2B is a cross-sectional view of the ARC layer 216 after it is opened.
  • Features 228 are then etched into the etch layer 212 through the photoresist mask 220 and the ARC layer 216, as shown in FIG. 2C.
  • the photoresist mask 220 and ARC layer 216 may be completely removed during a subsequent photoresist stripping process.
  • the etch layer 204 is show as being on top of the substrate 208, one or more layers may be between the etch layer 204 and the substrate 208. Alternatively, the substrate may be the etch layer.
  • FIG. 3 is a more detailed flow chart of the step of opening the ARC layer (step
  • the substrate is placed in a processing chamber (step 304). This step may occur before the step of opening the ARC layer (step 112).
  • An ARC open gas mixture is provided into the processing chamber (step 308).
  • This step comprises providing an etchant gas to the processing chamber (step 312), providing a polymerization gas to the processing chamber (step 316), and providing an etch rate booster to the processing chamber (step 320).
  • the polymerization gas is CO and CH 3 F.
  • the etch rate booster is O 2 .
  • the etch layer 204 is a is a silicon oxide dielectric layer over a silicon wafer substrate 208.
  • the ARC layer is a bottom antireflective coating (BARC), which is an organic ARC material.
  • FIG. 4 is a schematic view of a plasma processing chamber 400 that may be used for opening the ARC layer and etching the features in this example.
  • the plasma processing chamber 400 comprises confinement rings 402, an upper electrode 404, a lower electrode 408, a gas source 410, and an exhaust pump 420.
  • the gas source 410 comprises an ARC open etchant gas source 412, an ARC open etch booster gas source 418, an ARC open polymerization gas source 418, and an gas source for etching features in the etch layer 419, if the features are etched in the same process chamber.
  • the gas source 410 may comprise additional gas sources.
  • the substrate 208 is positioned upon the lower electrode 408.
  • the lower electrode 408 incorporates a suitable substrate chucking mechanism (e.g., electrostatic, mechanical clamping, or the like) for holding the substrate 208.
  • the reactor top 428 incorporates the upper electrode 404 disposed immediately opposite the lower electrode 408.
  • the upper electrode 404, lower electrode 408, and confinement rings 402 define the confined plasma volume. Gas is supplied to the confined plasma volume by the gas source 410 and is exhausted from the confined plasma volume through the confinement rings 402 and an exhaust port by the exhaust pump 420.
  • An RF source 448 is electrically connected to the lower electrode 408.
  • the upper electrode 404 is grounded. Chamber walls 452 surround the confinement rings 402, the upper electrode 404, and the lower electrode 408.
  • the RF source 448 may comprise a 27 MHz power source and a 2 MHz power source.
  • An Exelan 2300TM which is made by LAM Research CorporationTM of Fremont, California, was used in this example of the invention.
  • FIG.'s 5 A and 5B illustrate a computer system 500, which is suitable for implementing a controller 435 used in embodiments of the present invention.
  • FIG. 5 A shows one possible physical form of the computer system.
  • the computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge super computer.
  • Computer system 500 includes a monitor 502, a display 504, a housing 506, a disk drive 508, a keyboard 510, and a mouse 512.
  • Disk 514 is a computer-readable medium used to transfer data to and from computer system 500.
  • FIG. 5B is an example of a block diagram for computer system 500. Attached to system bus 520 is a wide variety of subsystems.
  • Processor(s) 522 also referred to as central processing units or CPUs
  • Memory 524 includes random access memory (RAM) and read-only memory (ROM).
  • RAM random access memory
  • ROM read-only memory
  • RAM random access memory
  • ROM read-only memory
  • RAM random access memory
  • ROM read-only memory
  • a fixed disk 526 is also coupled bi- directionally to CPU 522; it provides additional data storage capacity and may also include any of the computer-readable media described below.
  • Fixed disk 526 may be used to store programs, data, and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixed disk 526 may, in appropriate cases, be incorporated in standard fashion as virtual memory in memory 524.
  • Removable disk 514 may take the form of any of the computer-readable media described below.
  • CPU 522 is also coupled to a variety of input/output devices, such as display
  • an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch- sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers.
  • CPU 522 optionally may be coupled to another computer or telecommunications network using network interface 540. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps.
  • method embodiments of the present invention may execute solely upon CPU 522 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
  • embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations.
  • the media and computer code maybe those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts.
  • Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices.
  • ASICs application-specific integrated circuits
  • PLDs programmable logic devices
  • Computer code examples include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter.
  • Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
  • the etchant gas comprises 75 seem N 2 and
  • the ARC open polymerization gas comprises 200 seem CO and 6 seem CH F.
  • the ARC open etch booster gas comprises 3 seem O 2 .
  • the chamber pressure is set to 260 mTorr.
  • the power provided by the lower electrode is 0 Watts at 27 MHz and 600 Watts at 2 MHz.
  • the power provided during this step is kept low to reduce the removal of any of the photoresist mask 220.
  • This ARC open gas mixture which uses H 2 and N 2 as the ARC open etchant gases is highly selective for etching BARC with respect to silicon oxide. This high selectivity is defined as being greater than 20:1. More preferably, the ARC open etch to silicon oxide selectivity is greater than 50:1.
  • the ARC open selectivity is greater than infinity, so that there is no etching of the silicon oxide during the ARC open.
  • the lower electrode is kept at a temperature between -20° and 40° C .
  • FIG. 6A is a schematic cross-sectional view of a part of an etch layer near the center of a wafer after ARC opening is performed using this example.
  • FIG. 6B is a schematic cross-sectional view of a part of an etch layer near the edge of a wafer after ARC opening is performed using this example.
  • the photoresist mask 620 is protected to minimize damage to the photoresist mask 620 near both the center and edge of the wafer, to increase uniformity. Using the structures shown in FIG. 6A and FIG.
  • FIG. 7A is a schematic cross-sectional view of a part of an etch layer near the center of a wafer after a features are etched in the layer
  • FIG. 7B is a schematic cross-sectional view of a part of an etch layer near the edge of a wafer.
  • the inventive ARC open allows the formation of more uniform features and reduces line edge roughness.
  • FIG. 8A is a schematic cross-sectional view of a part of an etch layer 804 over a substrate 808 near the center of a wafer after ARC opening is performed using a prior art process.
  • FIG. 8A is a schematic cross-sectional view of a part of an etch layer 804 over a substrate 808 near the center of a wafer after ARC opening is performed using a prior art process.
  • FIG. 8A is a schematic cross-sectional view of a part of an etch layer 804 over a substrate 808 near the center of a wafer after ARC opening is performed using a prior art process.
  • FIG. 8B is a schematic cross-sectional view of a part of an etch layer near the edge of a wafer after ARC opening is performed using a prior art process.
  • Part of the photoresist mask 820 over an ARC layer 816 has been removed during the ARC open process. This is illustrated by the non-rectangular cross-sectional view of the parts of the photoresist mask 820 for both the center and the edge of the wafer, as shown in FIG. 8 A and FIG. 8B.
  • the erosion of the photoresist during the ARC open process of this example of the prior art is not uniform between the center of the wafer and the edge of the wafer.
  • FIG. 8A is a schematic cross-sectional view of a part of an etch layer near the center of a wafer after a features are etched in the etch layer and FIG.
  • FIG. 9B is a schematic cross-sectional view of a part of an etch layer near the edge of a wafer.
  • the erosion of the photoresist near the center of the wafer causes some line edge roughening 908 on the sides of the features 904, as shown in FIG. 9 A.
  • the increased erosion of the photoresist near the edge of the wafer causes increased line edge roughening 912 on the sides of the features 904, causing less uniform etch results over the surface of the wafer.
  • the ARC layer is an organic material, since the preferred ARC open recipe is known to open layers of organic material. Therefore, BARC, which is an organic ARC, is used in the preferred embodiment of the invention.
  • the inventive ARC open is able to slowly etch an organic ARC such as BARC, but since the ARC is thin, the slow etch is sufficient.
  • the inventive ARC open recipe is not able etch inorganic layers or etches inorganic silicon based layers so much slower than organic layers that attempting to etch a thin ARC inorganic layer may be too time consuming. Having an etch that is able to etch an organic layer but unable to etch an inorganic layer at a desirable speed allows for the high etch selectivity for etching an organic ARC over an inorganic dielectric layer. Table 1 provides preferred, more preferred, and most preferred ranges for the break through etch. Table 1

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
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PCT/US2005/007386 2004-03-10 2005-03-02 Line edge roughness control Ceased WO2005088693A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007502898A JP2007528610A (ja) 2004-03-10 2005-03-02 ラインエッジラフネス制御

Applications Claiming Priority (2)

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US10/798,456 US20040171260A1 (en) 2002-06-14 2004-03-10 Line edge roughness control
US10/798,456 2004-03-10

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US (1) US20040171260A1 (enExample)
JP (1) JP2007528610A (enExample)
KR (1) KR20070011306A (enExample)
CN (1) CN101027759A (enExample)
TW (1) TW200537580A (enExample)
WO (1) WO2005088693A1 (enExample)

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US20040171260A1 (en) * 2002-06-14 2004-09-02 Lam Research Corporation Line edge roughness control
US7547635B2 (en) * 2002-06-14 2009-06-16 Lam Research Corporation Process for etching dielectric films with improved resist and/or etch profile characteristics
US20090311871A1 (en) * 2008-06-13 2009-12-17 Lam Research Corporation Organic arc etch selective for immersion photoresist
TWI627667B (zh) 2012-11-26 2018-06-21 應用材料股份有限公司 用於高深寬比半導體元件結構具有污染物去除之無黏附乾燥處理
GB201315424D0 (en) * 2013-08-29 2013-10-16 Occles Ltd An eye cover device
KR102202517B1 (ko) * 2014-07-13 2021-01-13 케이엘에이 코포레이션 오버레이 및 수율 임계 패턴을 이용한 계측
US9899219B2 (en) * 2016-02-19 2018-02-20 Tokyo Electron Limited Trimming inorganic resists with selected etchant gas mixture and modulation of operating variables
KR102413039B1 (ko) * 2016-02-29 2022-06-23 도쿄엘렉트론가부시키가이샤 선택적 SiARC 제거

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US20040171260A1 (en) 2004-09-02

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