WO2005062156A1 - 周波数制御方法および情報処理装置 - Google Patents
周波数制御方法および情報処理装置 Download PDFInfo
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- WO2005062156A1 WO2005062156A1 PCT/JP2004/018841 JP2004018841W WO2005062156A1 WO 2005062156 A1 WO2005062156 A1 WO 2005062156A1 JP 2004018841 W JP2004018841 W JP 2004018841W WO 2005062156 A1 WO2005062156 A1 WO 2005062156A1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to a frequency control method for controlling a clock frequency of an information processing device such as a personal computer, and an information processing device.
- the clock frequency of the notebook PC CPU is set to the type of the processing operation of the OS. Some control is performed to switch to a user-specified clock frequency that is not relevant. This technical content is disclosed in, for example, JP-A-11-73237.
- the method disclosed in Japanese Patent Application Laid-Open No. 2001-5661 described above is excellent in efficiency in that the required clock frequency can be set according to the required processing operation of the notebook PC.
- an object of the present invention is to solve a powerful problem, to reduce the processing speed unnecessarily, and to suppress wasteful consumption of driving power more efficiently. It is to provide a number control method and an information processing device.
- a frequency control method for controlling an operation frequency of the control unit of an information processing apparatus including a control unit for controlling a processing operation, wherein the upper limit value of the operation frequency is specified.
- FIG. 1 is a block diagram showing an example of an internal configuration of a notebook PC according to an embodiment of the present invention.
- FIG. 2 is a diagram showing an example of an outline of a procedure in which the notebook PC having the configuration shown in FIG.
- FIG. 3 is a flowchart showing an example of processing contents regarding designation of a power saving level by the notebook PC having the configuration shown in FIG.
- FIG. 4 is a flowchart showing an example of processing contents via a ⁇ S interface unit of the BIOS shown in FIG.
- FIG. 5 is a flowchart showing an example of processing contents via a core part of the BIOS shown in FIG.
- FIG. 6 is a flowchart showing an example of the content of a switching process of the clock frequency of the CPU shown in FIG.
- FIG. 7 is a flowchart showing an example of a content of a CPU clock frequency reading process shown in FIG. 1.
- FIG. 8 is a flowchart showing a modification of the control process of the clock frequency by the CPU shown in FIG. 1.
- FIG. 1 is a block diagram showing an example of an internal configuration of a notebook PC according to an embodiment of the present invention.
- FIG. 1 illustrates only the configuration of a portion related to the present invention in the internal circuit of the notebook PC.
- a notebook PC according to one embodiment of the present invention includes a CPU 1 that controls the entire notebook PC.
- the CPU 1 is connected to a north bridge (hereinafter referred to as NB) 2.
- NB2 is connected to a south bridge (hereinafter referred to as SB) 3.
- NB2 is, for example, a bridge circuit that executes processing such as data and address conversion between the NB2 and the CPU 1, which is a device connected to the NB2.
- the SB3 is a bridge circuit that executes data input / output processing between devices connected via the SB3.
- the NB 2 is connected to the main memory 4 which is a work area when the CPU 1 operates. Ma
- the NB 2 is connected to an LCD (Liquid Crystal Display) 5, which is a display device.
- the SB3 is connected to the BIOS-ROM 6 and the HDD (hard disk drive) 7.
- the BIOS-ROM 6 stores a program for controlling the basic input / output of the notebook PC and controlling the clock frequency of the CPU 1.
- the BIOS-ROM 6 performs processing to change the clock frequency of the CPU 1 according to the type of processing performed by the notebook PC, and control of the clock frequency of the CPU 1 according to control by a power saving utility described later.
- the control processing program relating to the processing for changing the upper limit value is stored.
- the BIOS-ROM 6 stores parameters related to control of the notebook PC.
- the parameter relating to the control is, for example, the value of the clock frequency of the CPU 1.
- the BIOS-ROM 6 is a memory from which various programs and parameters can be read under the control of the CPU 1.
- the CPU 1 has a CPU register la for managing the clock frequency of the CPU 1.
- the CPU 1 operates at the clock frequency managed by the CPU register la.
- the value of the clock frequency managed by the CPU register la can be read / written by control via the BIOS-ROM6.
- the HDD 7 is a non-volatile storage medium, and is a device that can store data even when the power of the notebook PC is not turned on.
- the HDD 7 stores an OS (operating system), application programs, and the like. When these programs are executed, the programs are appropriately expanded in the memory 4.
- the OS includes a power saving utility program.
- the power saving utility is a program having a function of designating a power saving level corresponding to a plurality of upper limit values of the clock frequency of the CPU 1 according to a key input by a user.
- the power saving level is indicated by, for example, three levels of “high”, “medium”, and “low”. Each power saving level is associated with an upper limit of a different clock frequency.
- the CPU 1 operates at a clock frequency equal to or lower than the upper limit corresponding to each of the power saving levels according to the designation of the power saving level.
- the bus extended from the SB3 is connected to an embedded controller (hereinafter, referred to as EC) 8.
- EC embedded controller
- the EC 8 is connected to the keyboard 9.
- EC8 keyboard When mode 9 is pressed, this key is detected and a control signal corresponding to the pressed key is output to CPU1.
- a predetermined operation is performed using the keyboard 9 to cause the CPU 1 to read out the power saving utility from the HDD 7.
- the screen for setting the power saving level is displayed on the LCD5.
- the user specifies the power saving level by operating the keyboard 9 with the force S indicated on the setting screen.
- EC 8 is connected to power supply circuit 10.
- the power circuit 10 is connected to a power plug 12 via a power cord 11.
- the power supply circuit 10 supplies necessary drive power to each device such as the CPU 1.
- the power supply circuit 10 is connected to the battery 13. When external power cannot be obtained via the power plug 12, the power supply circuit 10 obtains driving power from the battery 13 and supplies this driving power to each device.
- FIG. 2 is a diagram illustrating an example of an outline of a procedure in which the notebook PC having the configuration illustrated in FIG. 1 specifies an upper limit value of the clock frequency of the CPU 1.
- the BIOS in FIG. 2 is a program stored in the BIOS-ROM 6.
- the BIOS includes an OS interface unit, which is a program for accessing the ⁇ S, and a core unit, which is a program for performing various arithmetic processing.
- the processing related to the power saving level by the notebook PC is executed by the BIOS ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ S interface.
- the process shifts from processing by the function of the core to processing by the function of the core of the BIOS.
- the clock frequency associated with the power saving level is derived.
- CPU1 controls so that it corresponds to the value of the clock frequency managed by CPU register la of PU1.
- the user specifies the power saving level by executing the power saving utility function, and then calculates the upper limit of the clock frequency corresponding to the specified power saving level through execution of the BIOS. The processing will be described.
- FIG. 3 is a flowchart showing an example of processing contents regarding designation of a power saving level by the notebook PC having the configuration shown in FIG.
- FIG. 4 is a flowchart showing an example of processing contents via the OS interface unit of the BIOS shown in FIG.
- FIG. 5 is a flowchart showing an example of processing contents via the core part of the BIOS shown in FIG.
- the CPU 1 activates a power saving utility of ⁇ S according to a key input by a user. Then, when the user specifies the power saving level in accordance with the instruction on the power saving level setting screen displayed on the LCD 5, the CPU 1 stores data indicating the specified power saving level in the memory 4 (step 4). Al). Then, the CPU 1 reads out and executes the program related to the OS interface section of the BIOS from the BIOS-ROM 6, and reads out the data of the power saving level stored in the memory 4 by the processing of step A1 (step A2). In other words, processing power related to the power saving level The processing shifts from the processing by the function of the power saving utility of the OS to the processing by the function of the OS interface part of the BIOS.
- the CPU 1 has a hyper threading function, which is a function of apparently executing a plurality of processes at once.
- the OS in the HDD 7 needs to be a system optimized for the hyper threading function.
- Whether the hyper threading function is enabled or disabled can be switched by the user through execution of the BIOS as needed.
- the procedure is as follows: First, the notebook PC is started, and a predetermined key operation is performed, so that the CPU 1 reads the BIOS setup program from the BIOS-ROM 6 and displays the BIOS setup screen on the LCD 5.
- the user operates the keyboard 9 according to the instruction displayed on the BIOS setup screen to enable or disable the hyper-threading function. Is set. Information on whether the hyper threading function is disabled or enabled is
- CMOS memory are stored in a non-illustrated non-volatile memory such as a CMOS memory.
- CPU 1 accesses BIOS-ROM 6 to determine whether the hypers of CPU 1 is set or disabled (step S2).
- step B1 If it is determined in step B1 that the hyper-threading function is enabled (YES in step B1), the CPU 1 reads the program related to the OS interface section of the BIOS from BIOS-ROM6. The OS reads and executes the command to determine whether the OS is running on CPU1. It is determined whether or not the system realizes the specification of the upper limit value of the clock frequency according to the power saving level (step B2).
- step B2 If it is determined in the process of step B2 that the OS does not support the power saving function of the hyper threading function of the CPU 1 (YES in step B2), the CPU 1 determines the clock frequency by the BIOS.
- a program related to the BIOS core is read from BIOS-ROM6 and executed so that the upper limit can be specified (step B3). In other words, the processing related to the power saving level shifts from processing by the function of the OS interface part of the BIOS to processing by the function of the core part of the BIOS.
- Step B4 the processing related to the power saving level shifts from the processing by the function of the OS interface unit of the BIOS to the processing by the function of the OS.
- step B4 When the result of the processing in step B2 is determined to be “N CPU”, the CPU 1 performs the processing in step B4 because an OS that supports the power saving function of the hyper threading function will be replaced by a notebook PC in the future.
- controlling the clock frequency via the ⁇ S instead of via the BIOS is more efficient than controlling the clock frequency via the BIOS. It is because the improvement of is expected.
- the CPU 1 reads the data of the power saving level stored in the memory 4 by the process of step A1 according to the program related to the core part of the BIOS (step S1).
- the CPU 1 calculates a parameter corresponding to the power saving level read in the process of step CI, that is, an upper limit value of the clock frequency of the CPU 1.
- the BIOS-ROM 6 stores the data of the highest performance value, which is the clock frequency for operating the CPU 1 at the highest performance, and the coefficient corresponding to the power saving level.
- CPU 1 derives a coefficient corresponding to the power saving level stored in memory 4 by the processing of step A1, calculates an upper limit by multiplying the coefficient by the highest performance value, and stores the upper limit in memory 4.
- the BIOS-ROM 6 stores data of the current clock frequency of the CPU 1 separately from the upper limit value of the clock frequency.
- the CPU 1 reads the upper limit value of the clock frequency calculated by the process of step C2 and the current clock frequency from the BIOS-ROM 6, and determines whether or not the current clock frequency is greater than the upper limit value calculated by the process of step C2. (Step C3).
- the CPU 1 will be described as a power S capable of performing a process of changing the clock frequency of the CPU 1 in accordance with the type of the process performed via ⁇ S.
- the CPU 1 calculates the clock frequency data of the CPU 1, which is the data stored in the CPU register la, by the process of Step C2. Rewrite the data with the clock frequency upper limit value data (step C4). As a result, the CPU 1 operates at the clock frequency of the upper limit calculated in the process of step C2. Note that, after the above-described processing in step B4, the CPU 1 performs the same processing as in steps C1 to C4. However, these processes are executed via the OS.
- FIG. 6 is a flowchart showing an example of the content of the clock frequency switching process of CPU 1 shown in FIG.
- the CPU 1 calculates a clock frequency corresponding to the type of the process, that is, a clock frequency as low as possible without lowering the processing speed (step Dl).
- the CPU 1 guides a clock frequency higher than a clock frequency required for performing other processes that do not require a waiting time.
- the CPU 1 accesses the CPU register la through the address conversion by the NB2, and uses the clock frequency data stored in the CPU register la by the processing of step D1, that is, the processing of the OS. Rewrite the data with the clock frequency calculated according to the type (step D2).
- CPU 1 performs the processing of steps Al, A2, B1 B4, CI, and C2 according to the above-described designation of the power saving level.
- the CPU 1 does not write the calculated value to the CPU register la but follows the program relating to the core part of the BIOS according to the program.
- the following processing is executed as interrupt processing instead of the processing of steps C3 and C4.
- the CPU 1 accesses the BIOS-ROM 6 and calculates whether the processing in step C2 has been performed in advance, that is, the upper limit value of the clock frequency according to the specification of the power saving level by the function of the power saving utility. Is determined (step El). As a result of this determination, if the CPU 1 determines that the upper limit value of the clock frequency has not been calculated (NO in step E1), the CPU 1 performs the processing of step E5. The processing of step E5 will be described later. On the other hand, if the CPU 1 determines that the upper limit of the clock frequency has been calculated (YES in step El), the CPU 1 skips the processing of step D2 and stores the data of the upper limit of the clock frequency in the BIOS ROM 6. And writes it to memory 4 (step E2).
- the CPU 1 writes the data of the clock frequency calculated by the process of step D1 into the memory 4 (step E3).
- the CPU 1 executes a program related to the core portion of the BIOS, calculates the clock frequency value S calculated in the process of step D1 and written in the memory 4, and is calculated in the process of step C2 and written in the memory 4. It is determined whether the clock frequency is lower than the upper limit value (step E4). That is, in the process of step E4, the CPU 1 determines whether or not the clock frequency is lower than the clock frequency specified by the power saving utility requested from the ⁇ S.
- the CPU 1 accesses the memory 4 Then, the data of the clock frequency calculated according to the type of the OS process, which is the data written to the memory 4 by the process of step E3, is read. Then, the CPU 1 accesses the CPU register la, and rewrites the clock frequency data managed by the CPU register la to the clock frequency data written in the memory 4 by the processing of step E3 (step E5). . Thus, the CPU 1 operates at the clock frequency calculated according to the processing content of the OS.
- step E4 when “NO” is determined in the process of step E4, the CPU 1 reads the data of the upper limit value of the clock frequency written in the memory 4 in the process of step E2. Then, the CPU 1 accesses the CPU register la, and rewrites the clock frequency data managed by the CPU register la to the clock frequency upper limit data read from the memory 4 (step E6). As a result, the CPU 1 operates at the clock frequency calculated according to the power saving level specified by the user by the power saving utility. Further, the CPU 1 writes the value of the clock frequency calculated by the processing in step E3 into the memory 4.
- step E1 to step E6 is an interrupt processing for the processing in steps Dl and D2, and depends on the clock frequency calculated according to the OS processing and the power saving level specified by the user.
- the lower one of the calculated clock frequencies is reflected as a new clock frequency of the CPU 1.
- the clock frequency of the CPU 1 changes according to the type of processing of the OS, and the value becomes a value equal to or less than the upper limit calculated according to the power saving level. It is possible to efficiently reduce unnecessary consumption of driving power without lowering the processing speed. For example, when the notebook PC is operated by the drive power supplied from the battery 13 instead of the external power supply, it is possible to suppress unnecessary consumption of the drive power even when performing a process of performing a light load process.
- FIG. 7 is a flowchart showing an example of the content of the clock frequency reading process of CPU 1 shown in FIG.
- CPU1 reads the current clock frequency of CPU1, which is the data stored in BIOS-ROM6 after rewriting the clock frequency managed by the CPU register la, and reads the read clock value.
- the clock calculated by the processing in step D1 Whether it matches the frequency value Confirmation (Step Fl). This reading process is performed by the OS.
- the clock frequency value is changed through the execution of the BIOS by the process of step E6, the current clock frequency stored in the BIOS The frequency does not match the clock frequency calculated according to the type of processing, and in this case, the CPU 1 determines that an error has occurred.
- the CPU 1 performs an interrupt process according to a program of the BIOS core unit when performing the process of reading the clock frequency through the execution of ⁇ S.
- the area for reading the current clock frequency by the CPU 1 is the access area 6a of the BIOS-ROM 6, in which the clock frequency data written to the CPU register la by the processing of step E3 is stored. ing.
- step D1 the CPU 1 executes the processing in step F1, that is, before performing the read processing of the current clock frequency by accessing the access area 6a through the address conversion, the clock stored in the area 6a.
- step F1 the processing in step F1
- the clock frequency data is rewritten to the clock frequency data stored in the memory 4 by the processing in step E3 (step G1).
- the value of the clock frequency read from the area 6a by the CPU 1 is the value of the clock frequency calculated according to the type of the OS process in the process of step D1. Therefore, even when the value of the clock frequency is changed through the execution of the BIOS by the processing of step E6, the above-described error can be prevented.
- the user specifies the power saving level by using the power saving utility and calculates the parameter corresponding to the power saving level, that is, the upper limit value of the clock frequency.
- the power saving utility allows the user to directly specify the upper limit of the clock frequency within the range of the above-mentioned maximum performance value through the input operation with the keyboard 9.
- FIG. 8 is a flowchart showing a modification of the control process of the clock frequency by the CPU 1 shown in FIG.
- the notebook PC automatically calculates the clock frequency according to the presence / absence of external power supply instead of the user's specification of the power saving level, and calculates this clock frequency. Specify as the new clock frequency of CPU1.
- the EC8 detects the value of the power supply voltage supplied to the power supply circuit 10 and determines whether or not external power is supplied. (Step Hl). As a result of this determination, when the external power is supplied (YES in step HI), the processing of steps Dl and D2 is performed without calculating the upper limit value of the clock frequency.
- CPU 1 stores the data of the power saving level corresponding to the clock frequency preset for battery operation. Is written to memory 4 (step H2). Thereafter, the CPU 1 performs the same processing as in step B1 and thereafter. In the process of step C2, the upper limit of the clock frequency for battery operation is calculated.
- the CPU 1 specifies a value of the clock frequency lower than the clock frequency when the external power is supplied as the upper limit value of the clock frequency.
- step E4 the process of step E4 is performed by the CPU1, and the lower value of the clock frequency value calculated according to the type of the OS process and the clock frequency calculated for battery operation is used.
- the clock frequency calculated according to the type of OS processing is written to the CPU register la by the processing of step E5, or the clock frequency calculated for driving the battery Is written to the CPU register la by the processing of step E6.
- the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying its constituent elements without departing from the gist thereof at an implementation stage.
- various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some components may be omitted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US11/449,595 US20060230304A1 (en) | 2003-12-19 | 2006-06-09 | Frequency control method and information processing apparatus |
Applications Claiming Priority (2)
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JP2003-422549 | 2003-12-19 | ||
JP2003422549A JP2005182473A (ja) | 2003-12-19 | 2003-12-19 | 周波数制御方法および情報処理装置 |
Related Child Applications (1)
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US11/449,595 Continuation US20060230304A1 (en) | 2003-12-19 | 2006-06-09 | Frequency control method and information processing apparatus |
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WO2005062156A1 true WO2005062156A1 (ja) | 2005-07-07 |
WO2005062156A8 WO2005062156A8 (ja) | 2005-08-25 |
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PCT/JP2004/018841 WO2005062156A1 (ja) | 2003-12-19 | 2004-12-16 | 周波数制御方法および情報処理装置 |
Country Status (4)
Country | Link |
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US (1) | US20060230304A1 (ja) |
JP (1) | JP2005182473A (ja) |
CN (1) | CN1894648A (ja) |
WO (1) | WO2005062156A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014063398A (ja) * | 2012-09-21 | 2014-04-10 | Fujitsu Ltd | 携帯端末装置の制御方法、制御プログラム、携帯端末装置 |
JP2014529146A (ja) * | 2012-08-30 | 2014-10-30 | ▲華▼▲為▼▲終▼端有限公司 | 中央演算装置を制御するための方法および装置 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4817760B2 (ja) * | 2005-08-26 | 2011-11-16 | キヤノン株式会社 | 情報処理装置及びそのシステムクロック周波数の設定方法 |
US8552849B2 (en) * | 2009-01-15 | 2013-10-08 | Infineon Technologies Ag | System and method for power supply testing |
JP5428695B2 (ja) * | 2009-09-16 | 2014-02-26 | 富士通株式会社 | バッテリー動作可能無線基地局装置 |
FR2960314B1 (fr) * | 2010-05-19 | 2012-07-27 | Bull Sas | Procede d'optimisation de gestion de veille d'un microprocesseur permettant la mise en oeuvre de plusieurs coeurs logiques et programme d'ordinateur mettant en oeuvre un tel procede |
TWI557546B (zh) * | 2012-01-11 | 2016-11-11 | 技嘉科技股份有限公司 | 一體式電腦及其電源管理方法 |
TWI526847B (zh) * | 2012-09-28 | 2016-03-21 | 微盟電子(昆山)有限公司 | 計算機及其硬體參數設定方法 |
JP6247480B2 (ja) * | 2013-09-12 | 2017-12-13 | 株式会社東芝 | 制御装置、制御システムおよび制御方法 |
US9689928B2 (en) | 2014-09-19 | 2017-06-27 | Infineon Technologies Ag | System and method for a built-in self-test of a battery |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06301647A (ja) * | 1993-04-13 | 1994-10-28 | Toshiba Corp | ポータブルコンピュータ |
JPH0844465A (ja) * | 1994-05-26 | 1996-02-16 | Seiko Epson Corp | 消費電力を効率化した情報処理装置 |
JPH10501911A (ja) * | 1994-06-17 | 1998-02-17 | インテル・コーポレーション | コンピュータ・システム内のプロセッサ性能と電力との動的管理 |
JP2001117663A (ja) * | 1999-10-21 | 2001-04-27 | Toshiba Corp | コンピュータシステムおよびその処理速度制御方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6385735B1 (en) * | 1997-12-15 | 2002-05-07 | Intel Corporation | Method and apparatus for limiting processor clock frequency |
US7058826B2 (en) * | 2000-09-27 | 2006-06-06 | Amphus, Inc. | System, architecture, and method for logical server and other network devices in a dynamically configurable multi-server network environment |
TW575803B (en) * | 2002-10-17 | 2004-02-11 | Uniwill Comp Corp | The method of managing portable computer power cord |
-
2003
- 2003-12-19 JP JP2003422549A patent/JP2005182473A/ja active Pending
-
2004
- 2004-12-16 WO PCT/JP2004/018841 patent/WO2005062156A1/ja active Application Filing
- 2004-12-16 CN CNA2004800378749A patent/CN1894648A/zh active Pending
-
2006
- 2006-06-09 US US11/449,595 patent/US20060230304A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06301647A (ja) * | 1993-04-13 | 1994-10-28 | Toshiba Corp | ポータブルコンピュータ |
JPH0844465A (ja) * | 1994-05-26 | 1996-02-16 | Seiko Epson Corp | 消費電力を効率化した情報処理装置 |
JPH10501911A (ja) * | 1994-06-17 | 1998-02-17 | インテル・コーポレーション | コンピュータ・システム内のプロセッサ性能と電力との動的管理 |
JP2001117663A (ja) * | 1999-10-21 | 2001-04-27 | Toshiba Corp | コンピュータシステムおよびその処理速度制御方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014529146A (ja) * | 2012-08-30 | 2014-10-30 | ▲華▼▲為▼▲終▼端有限公司 | 中央演算装置を制御するための方法および装置 |
US9405353B2 (en) | 2012-08-30 | 2016-08-02 | Huawei Device Co., Ltd. | Method and apparatus for controlling central processing unit |
JP2014063398A (ja) * | 2012-09-21 | 2014-04-10 | Fujitsu Ltd | 携帯端末装置の制御方法、制御プログラム、携帯端末装置 |
US9526026B2 (en) | 2012-09-21 | 2016-12-20 | Fujitsu Limited | Method for controlling information processing apparatus and information processing apparatus |
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Publication number | Publication date |
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CN1894648A (zh) | 2007-01-10 |
JP2005182473A (ja) | 2005-07-07 |
US20060230304A1 (en) | 2006-10-12 |
WO2005062156A8 (ja) | 2005-08-25 |
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