WO2005044695A1 - Boite de plaquettes amelioree bon marche - Google Patents

Boite de plaquettes amelioree bon marche Download PDF

Info

Publication number
WO2005044695A1
WO2005044695A1 PCT/US2004/015480 US2004015480W WO2005044695A1 WO 2005044695 A1 WO2005044695 A1 WO 2005044695A1 US 2004015480 W US2004015480 W US 2004015480W WO 2005044695 A1 WO2005044695 A1 WO 2005044695A1
Authority
WO
WIPO (PCT)
Prior art keywords
container
side walls
semiconductor wafers
cover
tray
Prior art date
Application number
PCT/US2004/015480
Other languages
English (en)
Other versions
WO2005044695A8 (fr
Inventor
Valoris L. Forsyth
Original Assignee
Illinois Tool Works, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Illinois Tool Works, Inc. filed Critical Illinois Tool Works, Inc.
Priority to KR1020067005008A priority Critical patent/KR101125775B1/ko
Priority to US11/920,028 priority patent/US20090090653A1/en
Priority to CN2004800252401A priority patent/CN1845860B/zh
Priority to EP04752489A priority patent/EP1685038A4/fr
Priority to JP2006537959A priority patent/JP4335921B2/ja
Publication of WO2005044695A1 publication Critical patent/WO2005044695A1/fr
Publication of WO2005044695A8 publication Critical patent/WO2005044695A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67369—Closed carriers characterised by shock absorbing elements, e.g. retainers or cushions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D21/00—Nestable, stackable or joinable containers; Containers of variable capacity
    • B65D21/02—Containers specially shaped, or provided with fittings or attachments, to facilitate nesting, stacking, or joining together
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67386—Closed carriers characterised by the construction of the closed carrier

Definitions

  • the present invention relates to a containment device or wafer box for transporting semiconductor wafers, particularly utilizing thermoformed material in place of other transport wafer packaging systems utilized in shipping wafers from a front-end wafer fabrication facility to a back-end product manufacturing facility.
  • the wafer box of the present invention includes a bottom floor attachment design which mechanically isolates wafers from side walls thereby acting as a shock absorber against vertical impact and vibration; a side wall configuration which isolates interior walls and the cavity from horizontal shock impact; a pedestal configuration at the corners and mid-span which provides standoff clearance when full boxes are inter-stacked, so that shock and vibration are not transmitted through the inter- stack configuration; a side wall configuration comprised of mating surfaces from the lid and bottom to create a double thickness wall thereby allowing substantially increased stacking capabilities; interlocking engagement elements on four sides to provide full engagement and survival of multiple drops of fully loaded wafer boxes (typically including 16 semiconductor wafers); interlocked offset flanges to provide for simple separation of the base from the lid; a large side wall flat surface to provide for the attachment of a large label along the side of the wafer box; and translucent material along the top of the wafer box so that large print paperwork is visible through the
  • the wafer box can include a side wall collapsible configuration through engagement of the lid to the base interface. This could be accomplished either by the vertical insertion of the lid over the base or through a living hinge folding action of the lid around the base. This provides for the reduction of excess movement of the semiconductor wafers in the cavity of the wafer box.
  • Figure 1 is a top plan view of the tray of the wafer box of the present invention.
  • Figure 2 is a side plan view of the tray of the wafer box of the present invention.
  • Figure 3 is a front plan view of the tray of the wafer box of the present invention.
  • Figure 4 is a perspective view of the tray of the wafer box of the present invention.
  • Figure 5 is a top plan view of the cover of the wafer box of the present invention.
  • Figure 6 is a side plan view of the cover of the wafer box of the present invention.
  • Figure 7 is a front plan view of the cover of the wafer box of the present invention.
  • Figure 8 is a perspective view of the cover of the wafer box of the present invention.
  • the tray 10 of the wafer box of the present invention includes a planar base 12 which is square or rectangular in shape, as bounded by sides 14, 16, 18, 20.
  • Side 20 includes an indented area 22.
  • Indented area 22 in combination with a similar indented area on the cover as will be described hereinafter in more detail, provides the opportunity for the user, or even automated machinery, to separate easily the tray 10 from the cover.
  • Outer walls 24, 26, 28, 30 rise inwardly adjacent from sides 14, 16, 18, 20, respectively, and terminate in elevated planar ledge area 32.
  • Inner walls 34, 36, 38, 40 extend from the interior of elevated planar ledge area 32 to planar base 12 thereby forming wafer cavity 42 therewithin.
  • Outer walls 24, 26, 28, 30 include semi-circular downwardly tapered concave portions 44 which add to the rigidity of the outer walls.
  • the portion of planar base 12 within wafer cavity 42 includes lattice 46 of ridges thereby mechanically isolating any wafers (not shown) within wafer cavity 42 from inner walls 34, 36, 38, 40 and acting as a shock absorber against vertical impact and vibration.
  • horizontal semi-circular channels 48, 50, 52, 54 are formed between respective outer walls 24, 26, 28, 30 and inner walls 34, 36, 38, 40.
  • Channels 48, 50, 52, 54 perform spacing, strengthening and horizontal shock-absorbing functions.
  • a pair of detent dimples 60 is formed on each of outer walls 24, 26, 28, 30 at about the one quarter and three quarters position along the span of each of the outer walls.
  • cover 62 of the wafer box includes lower rim 64 bounded by sides 66, 68, 70, 72 which generally correspond to the footprint of base 12 of tray 10.
  • side 72 includes indented area 74 which is intended to be laterally offset from indented area 22 when side 72 of cover 62 is aligned with side 20 of tray 10.
  • indented area 22 is on the left portion of side 20 while indented area 74 is on the right portion of side 72.
  • Cover side walls 76, 78, 80, 82 rise from lower rim 64 and terminate in cover upper planar surface 83.
  • Cover upper planar surface 83 may be formed of translucent material so that (large print) printed material inside may reduce the need for labeling of the wafer box.
  • Cover side walls 76, 78, 80, 82 are shaped so as to be able to outwardly engage outer walls 24, 26, 28, 30 when cover 62 is placed over tray 10 thereby forming a double thickness outer wall configuration.
  • Cover side walls 76, 78, 80, 82 include semi-circular downwardly tapered concave portions 84 which outwardly engage and mate to semi-circular downwardly tapered concave portions 44 of tray 10 in the installed position.
  • Central planar label areas 86 are formed at a central portion of each of cover side walls 76, 78, 80, 82, between the two interior semi-circular concave portions 84.
  • a pair of detent dimples 88 is formed on each of cover side walls 76, 78, 80, 82 at about the one quarter and three quarters position along the span of each of the cover side walls.
  • detent dimples 88 of cover 62 extend into detent dimples 60 of tray 10 thereby forming a detent relationship.
  • Corner pedestals 90 rise from the intersections of the cover side walls 76, 78, 80, 82 while mid-span pedestals 92 rise from the mid-point of cover side walls 76, 78, 80, 82.
  • Pedestals 90, 92 provide standoff clearance when full wafer boxes are inter-stacked so that transmission of shock and vibration through the inter-stack configuration is minimized or eliminated.
  • Tray 10 and cover 62 are typically formed of thermoformed material, although those skilled in the art will recognize a range of equivalents after review of this disclosure.
  • semiconductor wafers (not shown) are loaded into wafer cavity 42 of tray 10.
  • Cover 62 is then placed vertically over tray 10 so that detent dimples 88 of cover 62 extend into detent dimples 60 of tray 10 thereby forming a detent relationship, semi-circular downwardly tapered concave portions 84 of cover 62 outwardly engage and mate to semi-circular downwardly tapered concave portions 44 of tray 10, and indented areas 22 and 74 are laterally offset from each other thereby forming an interlocked offset flange configuration.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

L'invention concerne une boîte de plaquettes comprenant un plateau (10) et un couvercle (62). Ledit plateau (10) comprend une configuration de parois intérieures (34, 36, 38, 40) et extérieures (24, 26, 28, 30), des canaux horizontaux (48, 50, 52, 54) semi-circulaires étant disposés entre lesdites parois afin de fournie un espacement, un renforcement et des fonctions d'absorption de choc horizontal. Le plateau comprend (10) également une cavité de plaquette (42) formée dans la paroi intérieure (34, 36, 38, 40). Cette cavité de plaquette (42) comprend un treillis (46) de nervures disposées sur le fond de ladite cavité afin de fournir une fonction d'absorption de choc vertical. La paroi (76, 78, 80, 82) du couvercle (62) coopère et correspond avec la paroi extérieure (24, 26, 28, 30) du plateau (10) formant ainsi une configuration à paroi double. Une configuration de piédestal (90, 92) est formée sur les coins et les éléments médians de la partie supérieure du couvercle (62) afin de fournir un espace d'écartement entre les boîtes empilées et de limiter ou de supprimer la transmission d'un choc ou d'une vibration à travers une configuration d'empilement.
PCT/US2004/015480 2003-09-23 2004-05-18 Boite de plaquettes amelioree bon marche WO2005044695A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020067005008A KR101125775B1 (ko) 2003-09-23 2004-05-18 저 비용 웨이퍼 박스 개선
US11/920,028 US20090090653A1 (en) 2003-10-29 2004-05-18 Low cost wafer box improvements
CN2004800252401A CN1845860B (zh) 2003-09-23 2004-05-18 低成本晶片盒的改进
EP04752489A EP1685038A4 (fr) 2003-09-23 2004-05-18 Boite de plaquettes amelioree bon marche
JP2006537959A JP4335921B2 (ja) 2003-09-23 2004-05-18 低コストウェファボックスの改良

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US50517503P 2003-09-23 2003-09-23
US60/505,175 2003-09-23
US51586903P 2003-10-29 2003-10-29
US60/515,869 2003-10-29

Publications (2)

Publication Number Publication Date
WO2005044695A1 true WO2005044695A1 (fr) 2005-05-19
WO2005044695A8 WO2005044695A8 (fr) 2006-06-01

Family

ID=34572862

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/015480 WO2005044695A1 (fr) 2003-09-23 2004-05-18 Boite de plaquettes amelioree bon marche

Country Status (5)

Country Link
EP (1) EP1685038A4 (fr)
JP (1) JP4335921B2 (fr)
KR (1) KR101125775B1 (fr)
CN (1) CN1845860B (fr)
WO (1) WO2005044695A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005050156A1 (de) * 2005-10-19 2007-04-26 Manfred Jacob Kunststofftechnik Gmbh Verpackung für elektronische Bauteile, insbesondere für Tape-N-Reel-Spulen
US7918341B2 (en) 2007-10-12 2011-04-05 Peak Plastic & Metal Products (International) Limited Wafer container with staggered wall structure
US8109390B2 (en) 2009-08-26 2012-02-07 Texchem Advanced Products Incorporated Sdn Bhd Wafer container with overlapping wall structure
WO2012058678A2 (fr) * 2010-10-29 2012-05-03 Entegris, Inc. Conteneur de transport de substrat
US8556079B2 (en) 2009-08-26 2013-10-15 Texchem Advanced Products Incorporated Sdn Bhd Wafer container with adjustable inside diameter
US8813964B2 (en) 2009-08-26 2014-08-26 Texchem Advanced Products Incorporated Sdn. Bhd. Wafer container with recessed latch

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459099B (zh) * 2007-12-13 2010-11-10 中芯国际集成电路制造(上海)有限公司 晶圆盒、半导体生产过程的监测系统和方法
CN101752281B (zh) * 2008-12-02 2013-02-13 家登精密工业股份有限公司 晶片承载装置的承载盒
DE102010018668B4 (de) * 2010-04-07 2012-11-15 Curamik Electronics Gmbh Verpackungseinheit für Metall-Keramik-Substrate
HU230424B1 (hu) * 2011-07-29 2016-05-30 Curamik Electronics Gmbh Csomagolási egység szubsztrátok számára
CN102717982A (zh) * 2012-07-02 2012-10-10 深圳市华星光电技术有限公司 一种液晶玻璃的包装装置
KR102425700B1 (ko) * 2019-06-10 2022-07-28 삼성에스디아이 주식회사 이차전지 포장용 트레이

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3256975A (en) * 1963-11-29 1966-06-21 Leaming Ind Inc Container
US3482682A (en) * 1968-10-02 1969-12-09 Monsanto Co Retaining trays for semiconductor wafers and the like
US3710975A (en) * 1971-09-20 1973-01-16 Pantasote Co Of New York Inc Trays for photographic slides
US4697701A (en) * 1986-05-30 1987-10-06 Inko Industrial Corporation Dust free storage container for a membrane assembly such as a pellicle and its method of use
US5305878A (en) * 1993-04-01 1994-04-26 Yen Yung Tsai Packaged optical pellicle
US5441150A (en) * 1992-09-03 1995-08-15 Ma Laboratories, Inc. Memory module container
US6321911B1 (en) * 2000-01-31 2001-11-27 Display Pack, Inc. Fragility package
US6405873B2 (en) * 1998-09-18 2002-06-18 Seiko Epson Corporation Packing method and package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7059475B2 (en) * 2001-10-04 2006-06-13 Entegris, Inc. System for cushioning wafer in wafer carrier

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3256975A (en) * 1963-11-29 1966-06-21 Leaming Ind Inc Container
US3482682A (en) * 1968-10-02 1969-12-09 Monsanto Co Retaining trays for semiconductor wafers and the like
US3710975A (en) * 1971-09-20 1973-01-16 Pantasote Co Of New York Inc Trays for photographic slides
US4697701A (en) * 1986-05-30 1987-10-06 Inko Industrial Corporation Dust free storage container for a membrane assembly such as a pellicle and its method of use
US5441150A (en) * 1992-09-03 1995-08-15 Ma Laboratories, Inc. Memory module container
US5305878A (en) * 1993-04-01 1994-04-26 Yen Yung Tsai Packaged optical pellicle
US6405873B2 (en) * 1998-09-18 2002-06-18 Seiko Epson Corporation Packing method and package
US6321911B1 (en) * 2000-01-31 2001-11-27 Display Pack, Inc. Fragility package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1685038A4 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005050156A1 (de) * 2005-10-19 2007-04-26 Manfred Jacob Kunststofftechnik Gmbh Verpackung für elektronische Bauteile, insbesondere für Tape-N-Reel-Spulen
US7918341B2 (en) 2007-10-12 2011-04-05 Peak Plastic & Metal Products (International) Limited Wafer container with staggered wall structure
US8104619B2 (en) 2007-10-12 2012-01-31 Daewon Semiconductor Packaging Industrial Co., Ltd. Wafer container with staggered wall structure
US8109390B2 (en) 2009-08-26 2012-02-07 Texchem Advanced Products Incorporated Sdn Bhd Wafer container with overlapping wall structure
US8286797B2 (en) 2009-08-26 2012-10-16 Texchem Advanced Products Incorporated Sdn. Bhd. Wafer container
US8556079B2 (en) 2009-08-26 2013-10-15 Texchem Advanced Products Incorporated Sdn Bhd Wafer container with adjustable inside diameter
US8813964B2 (en) 2009-08-26 2014-08-26 Texchem Advanced Products Incorporated Sdn. Bhd. Wafer container with recessed latch
WO2012058678A2 (fr) * 2010-10-29 2012-05-03 Entegris, Inc. Conteneur de transport de substrat
WO2012058678A3 (fr) * 2010-10-29 2012-06-21 Entegris, Inc. Conteneur de transport de substrat

Also Published As

Publication number Publication date
EP1685038A4 (fr) 2008-11-26
WO2005044695A8 (fr) 2006-06-01
EP1685038A1 (fr) 2006-08-02
CN1845860A (zh) 2006-10-11
KR20070006665A (ko) 2007-01-11
CN1845860B (zh) 2011-01-19
JP2007505798A (ja) 2007-03-15
JP4335921B2 (ja) 2009-09-30
KR101125775B1 (ko) 2012-03-28

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