Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
  • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
  • H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

• the present invention relates to a phase locked loop filter.
• Radiotelephone systems typically require low phase noise, fast switching times, and precise accuracy of the channel frequencies.
• the associated PLL filter typically requires more than 10nF of capacitance, where the largest PLL capacitor will be the 'zero' capacitor (i.e. the PLL filter capacitor that is used to create a zero in the filters transfer function, which is necessary for the PLL's stability).
• PLL loop dynamics One technique that has been developed to reduce the required capacitance for a PLL, thereby allowing single-chip integration, while also retaining the same overall PLL transfer function (i.e. PLL loop dynamics), involves the use of a dual path PLL filter, in which each PLL filter path is driven by a separate charge pump path, for example from a charge pump having two output paths or two separate charge pumps having a single output path.
• dual path PLL filter was proposed by Craninckx and Steyaert, IEEE Journal of Solid-State Circuit, Vol. 33, No. 12, December 1998 in which a dual path PLL filter incorporated two active devices, an amplifier and a voltage adder.
• Another example of a dual path PLL filter was proposed by Koo, IEEE Journal of Solid-State Circuit, Vol. 37, No. 5, May 2002 in which a dual path PLL filter incorporated a single active device, an amplifier.
• US 5,774,023 discloses a loop filter that includes a high current first pole filter capacitor, a high current first pole damping resistor, a low current first pole filter capacitor, a low current first pole damping resistor and a first pole filter capacitor in which the loop filter is driven by a first charge pump output when current pulses from the charge pump are commensurate with a final narrow loop bandwidth otherwise the loop filter is driven by a second charge pump output.
• US 5,774,023 discloses the switching of current source between the first charge pump output and the second charge pump output rather than simultaneous output.
• phase locked loop filter according to claim 1.
• This provides the advantage of allowing a loop filter capacitance to be integrated onto a single chip without requiring the use of an active component, for example a voltage adder or an integrator.
• Figure 1 illustrates a phase locked loop incorporating a filter according to an embodiment of the present invention
• Figure 2 illustrates a phase locked loop filter according to an embodiment of the present invention
• Figure 3 shows graphs illustrate dual path characteristics of a phase locked loop filter according to an embodiment of the present invention
• Figure 4 illustrates a graph showing the phase noise characteristics of a phase locked loop filter according to an embodiment of the present invention.
• FIG. 1 illustrates a phase locked loop 10 for use in a radiotelephone (not shown).
• the phase locked loop 10 incorporates a phase detector 11 having a first input for receiving a reference frequency, a second input for receiving a PLL loop frequency and an output for coupling to a charge pump 12.
• the charge pump 12 has two output paths that are coupled to respective input paths of a loop filter 13.
• the loop filter 13 is coupled to a voltage controlled oscillator VCO 14.
• the VCO 14 is coupled to a first x2 divider 15, which provides an input to both a DCS portion of the radiotelephone and to a second x2 divider 16.
• the second x2 divider 16 provides an input to both a GSM portion of the radiotelephone and to an N divider 17.
• the N divider 17 is coupled to the second input of the phase detector 11 for providing the PLL loop frequency to the phase detector 11.
• FIG. 1 Although the embodiment shown in figure 1 is arranged for use in a multiband radiotelephone that supports both GSM and DCS, a person skilled in the art would appreciate that a more general PLL structure can be used, where, for example, the VCO 14 could be configured to provide an output frequency at the desired frequency without the need for a divider.
• the phase locked loop 10 operates in the following manner, a reference signal, for example a 26 MHz signal, is feed to the phase detector 11.
• the phase detector 11 compares the phase difference between the reference signal and an output signal from the N divider 17 to generate output pulses proportional to the error between the two phases of the signals.
• the output pulses from the phase detector 11 are used to either charge or discharge the charge pump 12, where the charge pump 12 has a first current output path and a second current output path, as described below.
• the signals between the phase detector 11 and the charge pump 12 are voltage signals.
• the charge pump 12 charges or discharges the loop filter 13.
• the loop filter 13 receives the current output from the first path and the second path and converts the current outputs, which reflect the phase difference between the two frequencies, into a voltage level, as described below.
• the voltage generated by the loop filter 13 is used to drive the VCO 14, where the VCO 14 is used to reduce the phase difference between the reference frequency and the output frequency of the N divider 17.
• the purpose of the first x2 divider 15, the second x2 divider 16 and the N divider 17 is to allow the generation of frequencies other than the reference frequency. As would be appreciated by a person skilled in the art by changing the N value it is possible to generate different frequencies, i.e. to act as a synthesizer.
• the VCO 14 can be arranged, when the PLL 10 has locked to the 26 MHz reference frequency, to generate a 3.6 GHz signal, where the first x2 divider 15 converts the 3.6 GHz signal to a 1.8 GHz signal, suitable for DCS application.
• the second x2 divider 16 converts the 1.8 GHz signal to a 0.9 GHz signal, suitable for GSM applications.
• the N divider 17 is arranged to convert the 0.9 GHz into a 26 MHz signal to maintain phase lock with the 26 MHz reference signal.
• Figure 2 illustrates the loop filter 13 coupled to the first charge pump path 21 and the second charge pump path 22.
• the first charge pump path 21 and the second charge pump path 22 can either be formed from a single charge pump or two separate charge pumps.
• the first charge pump path 21 is arranged to have a gain that corresponds to a charge pump gain l cp divided by a factor B.
• the second charge pump path 22 is arranged to generate a second current that corresponds to the charge pump current l cp minus the charge pump current l cp divided by the factor B (i.e. I cp - l cp /B).
• the loop filter 13 comprises a parallel resistor/capacitor circuit 23 having a first resistive element R1 (for example, a resistor or an element having the same functionality such as a switched capacitor circuit or a MOS transistor operating in its linear region) in parallel with a first capacitor C1.
• the parallel resistor/capacitor circuit 23 is coupled at one end to a reference voltage, for example ground or other stable voltage, and at the other end to the second charge pump path 22 and, in series, to a second capacitor C2.
• the other end of the second capacitor C2 is coupled to the first charge pump path 21 , thereby both the first charge pump path 21 and the second charge pump path 22 of the charge pump 12 provide a current simultaneously to the loop filter 13 for both frequency acquisition and locked mode.
• the loop filter 13 includes an additional pole created by a second resistive element R2 (for example, a resistor or an element having the same functionality such as a switched capacitor circuit or a MOS transistor operating in its linear region) coupled in series between the first charge pump path 21 and the VCO 14 and a third capacitor C3 that is coupled, at one end, between the second resistive element R2 and the VCO 14 and at the other end to a reference voltage, for example ground or other stable voltage.
• the purpose of the additional pole, created by the second resistive element R2 and third capacitor C3, is to further suppress phase noise and, though not essential, is a desirable feature.
• the voltage formed across the second capacitor C2 corresponds to the integrated input current and is governed by the equation in the s-domain, as shown in figure 3:
• the voltage formed across the parallel resistor/capacitor circuit 23 corresponds to a low pass transfer with a pole ⁇ p and is governed by the equation, as shown in figure 3:
• the second capacitor C2 is used to integrate the input voltage, and correspondingly is used to form the required zero for the loop filter 13, using a factor B to divide the charge pump current l cp provides the advantage of allowing the zero to be placed low enough, as illustrated in the filter impedance and loop gain graphs in figure 3, without requiring large capacitance values.
• the choice of the value of B depends of several factors. If the value of B increases the overall capacitance decreases, as such if capacitance is an issue you may want to put B as high as possible. However, there are several upper limits to the value of B. First, when B increases the in-band phase noise increases at the same rate. Second, it has been found that for a passive dual path filter with an additional pole (i.e.
• the low frequency path of the loop filter 13 formed between the first charge pump path 21 and the VCO 14 will, as a result of the charge pump current being divided by the factor B, be noisier than the high frequency path formed between the second charge pump path 22 and the VCO 14.
• the bandwidth of the low frequency path is smaller than the loop filter bandwidth, as determined by the high frequency path, the additional noise generated on the low frequency path will have no impact on the out-of-band phase noise.
• the noise generated by the low frequency path will be less than that of the high frequency path at offset frequencies higher than the loop filter bandwidth.
• values for the first capacitor C1 , the second capacitor C2, the third capacitor C3, the first resistive element R1 and the second resistive element R2 will know be calculated based on the following loop filter parameters:
• KVCO 400 MHz/V Ref frequency 26 MHz
• Dual Path ratio factor B 30
• the total loop filter capacitance for a loop filter based upon the loop filter described above is 615 pF.
• the total loop filter capacitance for a single path loop filter is of the order of 11 nF.

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• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
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• 2003
  • 2003-06-17 AT AT03291465T patent/ATE364930T1/de not_active IP Right Cessation
  • 2003-06-17 DE DE60314384T patent/DE60314384T2/de not_active Expired - Lifetime
  • 2003-06-17 EP EP03291465A patent/EP1492235B1/en not_active Expired - Lifetime
• 2004
  • 2004-06-16 KR KR1020057024275A patent/KR101073822B1/ko not_active Expired - Fee Related
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