GB2336482A - Phase lock loop with differential charge pump - Google Patents

Phase lock loop with differential charge pump Download PDF

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Publication number
GB2336482A
GB2336482A GB9807679A GB9807679A GB2336482A GB 2336482 A GB2336482 A GB 2336482A GB 9807679 A GB9807679 A GB 9807679A GB 9807679 A GB9807679 A GB 9807679A GB 2336482 A GB2336482 A GB 2336482A
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United Kingdom
Prior art keywords
charge pump
voltage
pll
voltage controlled
node
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GB9807679A
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GB2336482A8 (en
GB9807679D0 (en
GB2336482B (en
Inventor
Tal Mor
Shirazi Gadi
Fayneh Eyal
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Motorola Solutions Israel Ltd
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Motorola Israel Ltd
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Priority to GB9807679A priority Critical patent/GB2336482B/en
Publication of GB9807679D0 publication Critical patent/GB9807679D0/en
Publication of GB2336482A publication Critical patent/GB2336482A/en
Publication of GB2336482A8 publication Critical patent/GB2336482A8/en
Application granted granted Critical
Publication of GB2336482B publication Critical patent/GB2336482B/en
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop

Abstract

A phase lock loop (PLL) comprises a phase comparator 2 operably coupled to a first charge pump 3 and a second charge pump 4, a loop filter 5 and a voltage controlled oscillator 6 for providing a variable frequency signal. The PLL is characterised in that the first and second charge pumps provide differential voltage to a voltage controlled device 7 and to the loop filter 5 for varying the frequency of the voltage controlled oscillator 6. The first and second charge pumps (fig.2 not shown) each include first and second current sources coupled via a respective switch to a corresponding end of the filter 5. The voltage controlled device may be constituted by a Metal Insulator Silicon capacitor or by another voltage variable capacitor.

Description

2336482 PHASE LOCK LOOP AND Dln MENTIAL CHARGE PUMP
Field of the Invention
This invention relates to a Phase Lock Loop circuit and to a charge pump for use with a Phase Lock Loop circuit. The invention is particularly applicable to, but not limited to, a differential charge pump and differential Phase Lock Loop circuit.
Backeround of the Invention In low power, battery operated radio devices, the frequency synthesizer performance is often limited by the supply voltage. The reason for this is that the amount of tuning allowed by the variable capacitance diodes (varactors) which are employed in the Voltage Controlled Oscillator (VCO), is limited by the supply voltage of the Phase Lock Loop (PLL) charge pump. To utilise the full capacitance range, a charge pump with a high voltage level, for example, a voltage level with the range of 10 volts should be used. A capacitance ratio of the varactor (defined as the ratio of capacitance in the lowest and highest voltages supplied by the PLL), determines the tuning ratio of the VCO.
The disadvantage of known PLLs is that: since the high voltage is limited by the supply voltage and the low voltage is limited by the varactor forward biasing voltage, for example 0.7 volts, a DC biasing voltage greater than the varactor forward biasing voltage will limit the RF voltage from a high supply voltage to the varactor forward biasing voltage. Furthermore, as is known to a man skilled in the art, utilising the varactor to provide all of the WO capacitance by maximising the tuning range of the varactor will cause a decrement of the WO quality factor and an increment of the phase noise.
In order to overcome the above mentioned disadvantages, some PLL devices use a separate power supply for the charge pump. Thus, the charge pump voltage may be supplied from a higher voltage source than that which can be supplied by capacitive multiplier power supplies or by other types of power supplies.
4 CM00712S- Mor In this manner, the control line of the first switch of the first charge pump is operably coupled to the control fine of the second switch of the second charge pump for increasing the frequency of the PLL and the control line of the second switch on the first charge pump is operably coupled to the control line of the first switch of the second charge pump for decreasing the frequency of the PLL.
Furthermore, the control line for increasing the frequency engages the first switch of the first current source of the first charge pump and the second switch of the second current source of the second charge pump, to enable charging of the loop filter. The control line for decreasing the frequency of the PLL engages the second switch of the first charge pump and the first switch of the second charge pump, to enable discharge of the loop filter.
In a second aspect of the present invention, a differential charge pump for use with a Phase Lock Loop is provided. The differential charge pump includes a first current source operably coupled to a first switch, a second current source operably coupled to a second switch, a third current source operably coupled to a third switch, a fourth current source operably coupled to a fourth switch, a loop filter having a first node operably coupled to the first and the second switch and a second node operably coupled to the third and the fourth switches, a control line for increasing a frequency of the PLL operably coupled to the first and the fourth switch and a control line for decreasing the frequency of the PLL, operably coupled to the second and the third switch. The differential charge pump is characterised in that it utilises a differential voltage to vary the frequency of the PLL to which it is connected.
In the preferred embodiment of the invention, the first and the second current sources and the first and the second switches are a first charge pump and the first and the fourth current sources and the third and the fourth switches are a second charge pump.
In the preferred embodiment of the invention, the first and the second charge pumps are identical and the third switch is a first switch of the second charge pump and the fourth switch is a second switch of the second charge pump.
3 CM00712S- Mor first node of a voltage controlled device and a second node operably coupled to the second charge pump and to a second node of a voltage controlled device and a voltage controlled oscillator operably coupled to an output of the voltage controlled device for providing a variable frequency signal. The PLL is characterised in that: the first and the second charge pumps provide differential voltage to the voltage controlled device and to the loop filter for varying the frequency of the voltage controlled oscillator. In order to increase the frequency of the voltage controlled oscillator, a positive potential is provided to the first node of the voltage controlled device and a negative potential to the second node of the voltage controlled device. In order to decrease the frequency of the voltage controlled oscillator, a negative potential is provided to the first node of the voltage controlled device and a positive potential to the second node of the voltage controlled device.
Advantageously, a positive and a negative voltage is provided to the nodes of the voltage controlled device from a single power supply.
In the preferred embodiment of the invention, the I'LL is powered by a single power supply.
Preferably, the first and the second charge pumps are combined to provide a differential voltage which covers the dynamic voltage range of the voltage controlled device.
In this manner, the dynamic voltage range comprises, a voltage which varies from a negative to a positive voltage potential.
In the preferred embodiment of the invention, the voltage controlled device is a Metal Insulator Silicon capacitor or a Voltage Variable Capacitor (VVC).
Preferably, the first and thebecond charge pumps are identical and each one of the charge pumps includes a first switch having a first node operably coupled to a first current source, a second node and a control line for engaging and or disengaging the first current source from the loop filter and a second tch having a first node operably coupled to a second current source. a second node operably coupled to the first node of the first switch and to the loop filter and a control line for engaging and or disengaging the second current source from the loop filter.
6 CM00712S- Mor and 12. The operation of the first and the second charge pumps will be described in detail later.
The voltage controlled device 7 is, for example, a Metal Insulator Silicon capacitor (MIScap) or a Voltage Variable Capacitor (VVC). A variation in the capacitance of the loop filter 5 will cause the voltage controlled device 7 to vary its output voltage. The voltage controlled device 7 is operably coupled to the oscillator 8. The voltage which is output from the voltage controlled device will cause a frequency variation of the oscillator 8 and hence a variation of the output frequency 9.
In the preferred embodiment of the invention, the first and the second charge pumps provide a differential voltage to the voltage controlled device 7 and to the loop filter 5 for varying the frequency of the voltage controlled oscillator 6.
The operation of a differential charge pump will now be described with reference to FIG. 2.
The differential charge pump 20 includes the first charge pump 3, the second charge pump 4 and the loop filter 5. The first and the second charge pumps are identical.
The first charge pump 3 includes a first current source 21 operably coupled to a first switch 22, a second current source 23 operably coupled to a second switch 24, a control line 25 for increasing the frequency of the PLL. The control line 25 is operably coupled to the first switch 22. The first charge pump 3 further includes a control line 26 for decreasing the frequency of the PLL and an output 27. The control line 26 is operably coupled to the second switch 24 which is operably coupled to a first node 28 of the loop filter 5.
The second charge pump 4 includes a third current source 29 operably coupled to a third switch 30, a fourth current source 31 operably coupled to a fourth switch 32, control line 25 operably coupled to the third switch 30, control line 26 operably coupled to the fourth switch 32, and an output 33 which is operably coupled to a second node 34 of the loop filter 5.
The differential charge pump 20 provides a differential voltage for varying the output frequency of the PLL 1.
CM00712S- Mor A preferred embodiment of the invention will now be described by way of example only, with reference to the drawing.
Brief Description of the Drawings
FIG. 1 is a block diagram of Phase Lock Loop circuit according to the preferred embodiment of the invention; FIG. 2 is a block diagram of a differential charge pump according to a preferred embodiment of the invention; and FIG. 3 is a voltage curve of a Voltage Variable Capacitor.
Detailed Description of the Drawinga
Referring firstly to FIG. 1, a block diagram of a Phase Lock Loop (PLL) circuit is shown. The PLL 1 includes a phase comparator 2, a first charge pump 3, a second charge pump 4, a loop filter 5 and a Voltage Controlled Oscillator (VCO) 6. The WO 6 includes a voltage controlled device 7 and an oscillator 8. The PLL 1 is powered by a single power supply 10 which, is a 3 volt battery.
In operation, the phase comparator 2 receives frequencyf[Nand a feed-back frequency fFEEDBACK' The phase comparator 2 compares the phases of fIN and fFEEDBACK and outputs an increment (INC) signal for increasing an output frequency 9 or decrement (DEC) signal for decreasing the output frequency 9. Whenever, the phase difference is positive, the phase comparator 2 outputs the INC signal and whenever the phase difference is negative the phase comparator 2 outputs the DEC signal. To increase the output fequency, the first charge pump 3 provides a high voltage level to junction 11 and the second charge pump 4 provides a low voltage level to junction 12. To decrease the output frequency 9, the first charge pump 3 provides a low voltage level to junction 11 and the second charge,pump 4 provides a high voltage level to junction 12. Thus, a negative and a positive potential are provided to the loop filter 5 and to the voltage controlled device 7. The loop filter 5 is connected in parallel to the voltage control device 7 and to junctions 11 8 CM00712S- Mor In the preferred embodiment of the invention, the MIScap is "floated" from DC ground by a large RF bypass capacitor. The charge pump is configured as a differential output so that it can supply positive voltage to either side of the MIScap, thus, in effect, allowing negative 5 voltage across the MIScap.
Advantageously, supplying positive voltage to either side of the MIScap has the same effect as a negative supply to the charge pump, but without the need for generating an actual negative voltage. Thus, only one supply is required The advantage of the differential charge pump is that the configuration offered is less susceptible to external interference and ground currents.
Furthermore, this implementation of the differential charge pump may also easily be integrated into future PLL chips because a MIScap is a semiconductor device.
7 CM00712S- Mor In operation, an INC signal on the control line 25 activates the first switch 22 and the fourth switch 32. The first switch 22 connects the first current source 21 to the output 27 and to first node 28 of the loop filter 5, and the fourth switch 32 connects the fourth current source 31 to the output 33 and to the second node 34 of the loop filter 5. The first current source 21 charges the loop filter 5 and provides a positive potential to the first node 28. The fourth current source 31 discharges the loop filter 5 and provides a zero potential to the second node 34.
A DEC signal on the control line 26 activates the second switch 24 and the third switch 30. The second switch 24 connects the second current source 23 to the output 27 and to first node 28 of the loop filter 5. The third switch 30 connects the third current source 29 to the output 33 and to the second node 34 of the loop filter 5. The second current source 23 discharges the loop filter 5 and provides a zero potential to its first node 28. The third current source 29 charges the loop filter 5 and provides a positive potential to its second node 34. Thus, by alternating the potential at the nodes of the loop filter 5, the differential charge pump 20 provides a differential voltage which covers the dynamic voltage range of the voltage controlled device 7. The voltage on the voltage controlled device 7 can therefore vary from negative to positive voltage potential.
In the preferred embodiment of the invention, the MIScap is used as the voltage controlled device 7 in the WO 6 in place of a varactor. In order to utilise the full range of the MIScap, the differential charge pump 20 provides a negative voltage across the MIscap.
FIG. 3 shows a characteristic curve of the MIScap. The curve 40 shows that the dynamic range of the MIScap is from -0.5 volt to 1 volt. Variation of the voltage changes the capacitance of the MIScap. The MIScap is connected to the oscillator 8, thus, variation of capacitance varies the frequency of the oscillator 8.
To provide the negative voltage range from -2V to OV, 2 volts are provided at junction 12 and 0 volt at junction 11. To provide the positive voltage from 0 V to 2 V, 2 volts are provided at junction 11 and 0 volt at junction 12.
CM00712S- Mor a first switch having a first node operably coupled to a first current source, a second node and a control line for engaging and or disengaging the first current source from the loop filter; and a second switch having a first node operably coupled to a second current source, second node operably coupled to the first node of the first switch and to the loop filter and a control line for engaging and or disengaging the second current source from the loop filter.
8. A PLL as claimed in claim 7, wherein the control line of the first switch of the first charge pump is operably coupled to the control line of the second switch of the second charge pump for increasing the frequency of the PLL; and the control line of the second switch on a first charge pump is operably coupled to the control line of the first switch of the second charge pump for decreasing the frequency of the PLL.
9. A PLL as claimed in any one of claims 7 or 8, wherein the control line for increasing is engaging the first switch of the first current source of the first charge pump and the second switch of the current source of the second charge pump, for providing a high voltage level to the first node of the loop filter and the voltage controlled device and a low voltage level to the second node of the loop filter and the voltage controlled device; and the control line for decreasing the frequency of the PLL is engaging the second switch of the first charge pump and the first switch of the second charge pump, for providing a low voltage level to the first node of the loop filter and the voltage controlled device and a high voltage level to the second node of the loop filter and the voltage controlled device.
10. A differential charge pump, in use with a Phase Lock Loop, comprising:
first current source operably coupled to a first switch; second current source operably coupled to a second switch; third current source operably coupled to a third switch; 9

Claims (1)

  1. Claims
    CM00712S- Mor 1. A Phase Lock loop (PLL) comprising: a phase comparator operably coupled to a first charge pump and a second charge pump; a loop filter having a first node operably coupled to the first charge pump and to a first node of a voltage controlled device and a second node operably coupled to the second charge pump and to a second node of a voltage controlled device; and a voltage controlled oscillator operably coupled to an output of the voltage controlled device for providing a variable frequency signal; and the PLL being characterised in that:
    the first and the second charge pumps provide differential voltage to the voltage controlled device and to the loop filter for varying the frequency of the voltage controlled oscillator.
    2. A PLL as claimed in claim 1, wherein the PLL is powered by a single power supply.
    3. A PLL as claimed in claims 1 or 2, wherein the first and the second charge pumps are combined for providing difFerential voltage which covers the dynamic voltage range of the voltage controlled device.
    4. A PLL as claimed in any one of claims 1,2 or 3 wherein the dynamic voltage range varies from negative to positive voltage potential.
    5. A PLL as claimed in any one of claims 1,2,3 or 4, wherein the voltage controlled device is a MetaI Insulator Silicon capacitor.
    6. A PLL as claimed in any one of claims 1 to 5 wherein the voltage controlled device is a voltage variable capacitor.
    7. A PLL as claimed in any one of claims 1 to 6, wherein the first and the second charge pumps are identical and each one of the charge pump 35 comprises:
    11 CM00712S- Mor fourth current source operably coupled to a fourth switch; loop filter having a first node operably coupled to the first and the second switch and a second node operably coupled to the third and the forth switches; a control line for increasing a frequency of the PLL operably coupled to the first and the fourth switch; and a control line for decreasing the frequency of the PLL, operably coupled to the second and the third switch; and the differential charge pump is characterising by that:
    providing differential voltage for varying the frequency of the PLL.
    11. A differential charge pump. as claimed in claim 10, wherein the first and the second current sources and the first and the second switches are a first charge pump; and the first and the fourth current sources and the third and the fourth switches are a second charge pump.
    12. A differential charge pump as claimed in claim 10 or claim 11, wherein the first and the second charge pumps are identical; and 20 the third switch is a first of the second charge pump and the fourth switch is a second switch of the second charge pump.
    13. A differential charge pump as claimed in claims 10, 11 or 12, wherein, the control line for increasing the frequency of the PLL increases the frequency by providing a high voltage level to the first node of the loop filter and the voltage controlled device and a low voltage level to the second node of the loop filter and the voltage controlled device; and the control line for decreasing the frequency of the decreases th frequency by providing a low voltage level to the first node of the loop filter and the voltage controlled device and a high voltage level to the second node of the loop filter and the voltage controlled device.
GB9807679A 1998-04-14 1998-04-14 Phase lock loop and differential charge pump Expired - Fee Related GB2336482B (en)

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GB2336482A true GB2336482A (en) 1999-10-20
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GB2336482B GB2336482B (en) 2000-06-07

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1282234A1 (en) * 2001-07-31 2003-02-05 Texas Instruments Incorporated Loop filter architecture
GB2416634A (en) * 2004-07-22 2006-02-01 Samsung Electronics Co Ltd Phase locked loop with fast locking characteristics
CN109716655A (en) * 2016-09-22 2019-05-03 高通股份有限公司 Switched-capacitor circuit in PLL

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0206816A2 (en) * 1985-06-26 1986-12-30 Data General Corporation Apparatus for increasing the switching speed of diodes
EP0674392A1 (en) * 1994-03-24 1995-09-27 Discovision Associates Phase locked loop
US5477193A (en) * 1994-10-21 1995-12-19 Cyrix Corporation Current source loop filter with automatic gain control
US5650754A (en) * 1995-02-15 1997-07-22 Synergy Microwave Corporation Phase-loched loop circuits and voltage controlled oscillator circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0206816A2 (en) * 1985-06-26 1986-12-30 Data General Corporation Apparatus for increasing the switching speed of diodes
EP0674392A1 (en) * 1994-03-24 1995-09-27 Discovision Associates Phase locked loop
US5477193A (en) * 1994-10-21 1995-12-19 Cyrix Corporation Current source loop filter with automatic gain control
US5650754A (en) * 1995-02-15 1997-07-22 Synergy Microwave Corporation Phase-loched loop circuits and voltage controlled oscillator circuits

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1282234A1 (en) * 2001-07-31 2003-02-05 Texas Instruments Incorporated Loop filter architecture
US6600351B2 (en) 2001-07-31 2003-07-29 Texas Instruments Incorporated Loop filter architecture
GB2416634A (en) * 2004-07-22 2006-02-01 Samsung Electronics Co Ltd Phase locked loop with fast locking characteristics
GB2416634B (en) * 2004-07-22 2006-11-15 Samsung Electronics Co Ltd Phase locked loop integrated circuits having fast locking characteristics and methods of operating same
US7292078B2 (en) 2004-07-22 2007-11-06 Samsung Electronics Co., Ltd. Phase locked loop integrated circuits having fast locking characteristics and methods of operating same
CN109716655A (en) * 2016-09-22 2019-05-03 高通股份有限公司 Switched-capacitor circuit in PLL

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Publication number Publication date
GB2336482A8 (en) 2000-03-01
GB9807679D0 (en) 1998-06-10
GB2336482B (en) 2000-06-07

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Effective date: 20040414